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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Anirban, Sk <sk.anirban@intel.com><br>
<b>Sent:</b> Thursday, February 20, 2025 12:10 PM<br>
<b>To:</b> intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Gupta, Anshuman <anshuman.gupta@intel.com>; Nilawar, Badal <badal.nilawar@intel.com>; Tauro, Riana <riana.tauro@intel.com>; Poosa, Karthik <karthik.poosa@intel.com>; Gupta, Varun <varun.gupta@intel.com>; Anirban, Sk <sk.anirban@intel.com><br>
<b>Subject:</b> [PATCH] drm/i915/selftests: Re-enable power gating after live_selftest</font>
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<div class="PlainText">From: Sk Anirban <sk.anirban@intel.com><br>
<br>
The current implementation of live_rc6_manual disables power gating<br>
after execution due to the deactivation of RC6.<br>
This update aims to re-enable power gating following the completion<br>
of the self-test. However, as a temporary workaround<br>
for forcewake timeouts, power gating will remain disabled for MTL.<br>
<br>
Signed-off-by: Sk Anirban <sk.anirban@intel.com><br>
---<br>
drivers/gpu/drm/i915/gt/selftest_rc6.c | 37 ++++++++++++++++++++++++++<br>
1 file changed, 37 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c<br>
index 30bc2ff040ce..b24d3d7de67b 100644<br>
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c<br>
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c<br>
@@ -34,6 +34,7 @@ int live_rc6_manual(void *arg)<br>
struct intel_gt *gt = arg;<br>
struct intel_rc6 *rc6 = >->rc6;<br>
struct intel_rps *rps = >->rps;<br>
+ struct intel_uncore *uncore = rc6_to_uncore(rc6);<br>
intel_wakeref_t wakeref;<br>
u64 sleep_time = 1000;<br>
u32 rc0_freq = 0;<br>
@@ -42,10 +43,12 @@ int live_rc6_manual(void *arg)<br>
u64 rc6_power[3];<br>
bool has_power;<br>
u64 threshold;<br>
+ u32 pg_enable;<br>
ktime_t dt;<br>
u64 res[2];<br>
int err = 0;<br>
u64 diff;<br>
+ int i;<br>
<br>
<br>
/*<br>
@@ -148,6 +151,40 @@ int live_rc6_manual(void *arg)<br>
intel_rc6_unpark(rc6);<br>
<br>
out_unlock:<br>
+ if (GRAPHICS_VER(gt->i915) >= 9) {<br>
+ if (!intel_guc_rc_enable(gt_to_guc(gt)))<br>
+ rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;<br>
+ else<br>
+ rc6->ctl_enable =<br>
+ GEN6_RC_CTL_HW_ENABLE |<br>
+ GEN6_RC_CTL_RC6_ENABLE |<br>
+ GEN6_RC_CTL_EI_MODE(1);<br>
+<br>
+ if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))<br>
+ pg_enable =<br>
+ GEN9_MEDIA_PG_ENABLE |<br>
+ GEN11_MEDIA_SAMPLER_PG_ENABLE;<br>
+ else<br>
+ pg_enable =<br>
+ GEN9_RENDER_PG_ENABLE |<br>
+ GEN9_MEDIA_PG_ENABLE |<br>
+ GEN11_MEDIA_SAMPLER_PG_ENABLE;<br>
+<br>
+ if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {<br>
+ for (i = 0; i < I915_MAX_VCS; i++)<br>
+ if (HAS_ENGINE(gt, _VCS(i)))<br>
+ pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |<br>
+ VDN_MFX_POWERGATE_ENABLE(i));<br>
+ }<br>
+<br>
+ if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)) &&<br>
+ GRAPHICS_VER(gt->i915) < 11)<br>
+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,<br>
+ GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);<br>
+ else<br>
+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);<br>
+ }<br>
+<br>
intel_runtime_pm_put(gt->uncore->rpm, wakeref);<br>
return err;<br>
}<br>
-- <br>
2.34.1<br>
<br>
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