[PATCH] drm/i915/gvt: Align render mmio list to cacheline

[Zhenyu Wang]

On 2017.04.06 10:55:02 +0800, changbin.du at intel.com wrote:
> From: Changbin Du <changbin.du at intel.com>
> 
> Make the global mmio list be cacheline aligned to improve performance.
> 
> Signed-off-by: Changbin Du <changbin.du at intel.com>
> ---

applied, thanks!

-- 
Open Source Technology Center, Intel ltd.

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