[PATCH] drm/i915/gvt: Add support for PCIe extended configuration space

[Laszlo Ersek]

Hi,

On 08/23/17 08:08, changbin.du at intel.com wrote:
> From: Changbin Du <changbin.du at intel.com>
> 
> IGD is PCIe device and has extended configuration space. Checking
> the binary dump, we can see we have Caps located out of PCI compatible
> Configuration Space range.
> 
> 0x000: 86 80 12 19 17 04 10 00 06 00 00 03 00 00 00 00
> 0x010: 04 00 00 10 08 00 00 00 0c 00 00 00 08 00 00 00
> 0x020: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b9 06
> 0x030: 00 f8 ff ff 40 00 00 00 00 00 00 00 0b 01 00 00
> 0x040: 09 70 0c 01 71 26 01 62 c8 00 04 84 00 00 00 00
> 0x050: c1 00 00 00 39 00 00 00 00 00 00 00 01 00 00 a2
> 0x060: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x070: 10 ac 92 00 00 80 00 10 00 00 00 00 00 00 00 00
> 0x080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x0a0: 00 00 00 00 00 00 00 00 00 00 00 00 05 d0 01 00
> 0x0b0: 18 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00
> 0x0c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x0d0: 01 00 22 00 00 80 00 00 00 00 00 00 00 00 00 00
> 0x0e0: 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00
> 0x0f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x100: 1b 00 01 20 02 14 00 00 00 00 00 00 00 00 00 00
> ...
> 
> Currently, we only emulate the PCI compatible Configuration Space.
> This is okay if we attach vGPU to PCI bus. But when we attach to
> a PCI Express bus (when Qemu emulates a Intel Q35 chipset which has
> PCIe slot), it will not work. Extended Configuration Space is required
> for a PCIe device.
> 
> This patch extended the virtual configuration space from 256 bytes
> to 4KB bytes. So we are to be a *real* PCIe device. And for the
> Extended CapList we keep same to physical GPU.
> 
> Cc: Laszlo Ersek <lersek at redhat.com>
> Signed-off-by: Changbin Du <changbin.du at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/cfg_space.c | 4 ++--
>  drivers/gpu/drm/i915/gvt/gvt.c       | 2 +-
>  drivers/gpu/drm/i915/gvt/gvt.h       | 3 +--
>  drivers/gpu/drm/i915/gvt/kvmgt.c     | 2 +-
>  4 files changed, 5 insertions(+), 6 deletions(-)

Assuming I can find the time to test this, which kernel tree (git URL)
and branch should I apply the patch to?

Thanks,
Laszlo

> diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
> index ce71b58..ab19545 100644
> --- a/drivers/gpu/drm/i915/gvt/cfg_space.c
> +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
> @@ -101,7 +101,7 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
>  	if (WARN_ON(bytes > 4))
>  		return -EINVAL;
>  
> -	if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
> +	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
>  		return -EINVAL;
>  
>  	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
> @@ -289,7 +289,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
>  	if (WARN_ON(bytes > 4))
>  		return -EINVAL;
>  
> -	if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
> +	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
>  		return -EINVAL;
>  
>  	/* First check if it's PCI_COMMAND */
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
> index c27c683..aaa347f 100644
> --- a/drivers/gpu/drm/i915/gvt/gvt.c
> +++ b/drivers/gpu/drm/i915/gvt/gvt.c
> @@ -111,7 +111,7 @@ static void init_device_info(struct intel_gvt *gvt)
>  	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
>  		|| IS_KABYLAKE(gvt->dev_priv)) {
>  		info->max_support_vgpus = 8;
> -		info->cfg_space_size = 256;
> +		info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
>  		info->mmio_size = 2 * 1024 * 1024;
>  		info->mmio_bar = 0;
>  		info->gtt_start_offset = 8 * 1024 * 1024;
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> index 2fe22e1..c096526 100644
> --- a/drivers/gpu/drm/i915/gvt/gvt.h
> +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> @@ -100,7 +100,6 @@ struct intel_vgpu_mmio {
>  	bool disable_warn_untrack;
>  };
>  
> -#define INTEL_GVT_MAX_CFG_SPACE_SZ 256
>  #define INTEL_GVT_MAX_BAR_NUM 4
>  
>  struct intel_vgpu_pci_bar {
> @@ -109,7 +108,7 @@ struct intel_vgpu_pci_bar {
>  };
>  
>  struct intel_vgpu_cfg_space {
> -	unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
> +	unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
>  	struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
>  };
>  
> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index ae65268..9606092 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -978,7 +978,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd,
>  		switch (info.index) {
>  		case VFIO_PCI_CONFIG_REGION_INDEX:
>  			info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index);
> -			info.size = INTEL_GVT_MAX_CFG_SPACE_SZ;
> +			info.size = vgpu->gvt->device_info.cfg_space_size;
>  			info.flags = VFIO_REGION_INFO_FLAG_READ |
>  				     VFIO_REGION_INFO_FLAG_WRITE;
>  			break;
>