[PATCH v2 7/9] drm/i915/gvt: add basic function for weight control

[Ping Gao]

This method tries to guarantee precision in second level, with the
adjustment conducted in every 100ms. At the end of each vGPU switch
calculate the sched time and subtract it from the time slice
allocated; the dedicate time slice for every 100ms together with
remaining timeslice, will be used to decide how much timeslice
allocated to this vGPU in the next 100ms slice, with the end goal
to guarantee weight ratio in second level.

Signed-off-by: Ping Gao <ping.a.gao at intel.com>
---
 drivers/gpu/drm/i915/gvt/sched_policy.c | 78 +++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c
index 4dcbdc3..081a512 100644
--- a/drivers/gpu/drm/i915/gvt/sched_policy.c
+++ b/drivers/gpu/drm/i915/gvt/sched_policy.c
@@ -69,6 +69,79 @@ struct tbs_sched_data {
 	struct list_head lru_vgpu_head;
 };
 
+/* Calc the sched_time during vGPU switch, subtract it
+ * from the time slice allocated correspondingly.
+ */
+static void stat_timeslice_usage(struct intel_vgpu *pre_vgpu)
+{
+	int64_t ts_delta;
+	struct tbs_vgpu_data *vgpu_data = pre_vgpu->sched_data;
+
+	ts_delta = vgpu_data->sched_out_time - vgpu_data->sched_in_time;
+
+	vgpu_data->sched_time += ts_delta;
+	vgpu_data->ts_usage -= ts_delta;
+}
+
+#define GVT_TS_BALANCE_PERIOD_MS 100
+#define GVT_TS_BALANCE_PERIOD_CYC ((cycles_t)tsc_khz * GVT_TS_BALANCE_PERIOD_MS)
+
+/* This function executed every 100ms, to alloc time slice
+ * for next 100ms.
+ */
+static void gvt_timeslice_balance(struct tbs_sched_data *sched_data)
+{
+	struct tbs_vgpu_data *vgpu_data;
+	struct list_head *pos;
+	static uint64_t stage_check;
+	int stage = stage_check++ % 10;
+
+	if (stage == 0) {
+		int total_weight = 0;
+		int64_t fair_timeslice;
+
+		/* Every vgpu should set valid weight at the same time */
+		list_for_each(pos, &sched_data->runq_head) {
+			vgpu_data = container_of(pos, struct tbs_vgpu_data, list);
+
+			if (vgpu_data->vgpu->id == 0)
+				continue;
+
+			if (vgpu_data->sched_ctl.weight == 0) {
+				total_weight = 0;
+				break;
+			}
+			total_weight += vgpu_data->sched_ctl.weight;
+		}
+
+		/* The timeslice accumulation will reset every second */
+		list_for_each(pos, &sched_data->runq_head) {
+			vgpu_data = container_of(pos, struct tbs_vgpu_data, list);
+			if (total_weight)
+				fair_timeslice = GVT_TS_BALANCE_PERIOD_CYC *
+					vgpu_data->sched_ctl.weight /
+						total_weight;
+			else
+				fair_timeslice = GVT_TS_BALANCE_PERIOD_CYC;
+
+			vgpu_data->ts_alloc = fair_timeslice;
+			vgpu_data->ts_usage = vgpu_data->ts_alloc;
+
+			/* sched_in_time need reset every second also */
+			vgpu_data->sched_in_time = get_cycles();
+		}
+	} else {
+		list_for_each(pos, &sched_data->runq_head) {
+			vgpu_data = container_of(pos, struct tbs_vgpu_data, list);
+
+			/* timeslice for next 100ms should add the left/debt
+			 * slice of previous stages.
+			 */
+			vgpu_data->ts_usage += vgpu_data->ts_alloc;
+		}
+	}
+}
+
 static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
 {
 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
@@ -105,6 +178,7 @@ static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
 	if (scheduler->current_vgpu) {
 		vgpu_data = scheduler->current_vgpu->sched_data;
 		vgpu_data->sched_out_time = cur_cycles;
+		stat_timeslice_usage(scheduler->current_vgpu);
 	}
 	vgpu_data = scheduler->next_vgpu->sched_data;
 	vgpu_data->sched_in_time = cur_cycles;
@@ -238,6 +312,10 @@ static void tbs_sched_func(struct tbs_sched_data *sched_data)
 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 	struct tbs_vgpu_data *vgpu_data;
 	struct intel_vgpu *vgpu = NULL;
+	static uint64_t timer_check;
+
+	if (!(timer_check++ % GVT_TS_BALANCE_PERIOD_MS))
+		gvt_timeslice_balance(sched_data);
 
 	/* no vgpu or has already had a target */
 	if (gvt->num_vgpu_sched <= 1 || scheduler->next_vgpu)
-- 
2.7.4