[PATCH] drm/i915/gvt: optimize the inhibit context mmio load

[Zhenyu Wang]

On 2017.02.14 15:14:05 +0800, Chuanxiao Dong wrote:
> For the inhibit ctx, load all mmio in render mmio list
> into HW by MMIO write for ctx initialization.
> 
> For the none-inhibit ctx, only load the render mmio which
> is not in_context into HW by MMIO write. Skip the MMIO write
> for in_context mmio as context image will load it.
> 
> Signed-off-by: Chuanxiao Dong <chuanxiao.dong at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/render.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
> index 44136b1..2b3a642 100644
> --- a/drivers/gpu/drm/i915/gvt/render.c
> +++ b/drivers/gpu/drm/i915/gvt/render.c
> @@ -236,12 +236,18 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
>  	}
>  }
>  
> +#define CTX_CONTEXT_CONTROL_VAL	0x03

This offset seems wrong, don't re-invent, but use i915 definition
for CTX_CONTEXT_CONTROL.

> +
>  void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, int ring_id)
>  {
>  	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
>  	struct render_mmio *mmio;
>  	u32 v;
>  	int i, array_size;
> +	u32 *reg_state = vgpu->shadow_ctx->engine[ring_id].lrc_reg_state;
> +	u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
> +	u32 inhibit_mask =
> +		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>  
>  	if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
>  		mmio = gen9_render_mmio_list;
> @@ -257,6 +263,17 @@ void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, int ring_id)
>  			continue;
>  
>  		mmio->value = I915_READ(mmio->reg);
> +
> +		/*
> +		 * if it is an inhibit context, load in_context mmio
> +		 * into HW by mmio write. If it is not, skip this mmio
> +		 * write.
> +		 */
> +		if (mmio->in_context &&
> +				((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
> +				i915.enable_execlists)
> +			continue;
> +
>  		if (mmio->mask)
>  			v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
>  		else
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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