[PATCH] drm/i915/gvt: introduced failsafe mode into vgpu

[He, Min]

在 2/15/2017 3:46 PM, Du, Changbin 写道:
> On Wed, Feb 15, 2017 at 03:28:43PM +0800, Min He wrote:
>> New failsafe mode is introduced, when we detect guest not supporting
>> GVTg.
>> In failsafe mode, we will ignore all the MMIO and cfg space read/write
>> from guest.
>>
>> Signed-off-by: Min He <min.he at intel.com>
>> Signed-off-by: Pei Zhang <pei.zhang at intel.com>
>> ---
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index 1d45062..6089a1e 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -154,6 +154,17 @@ static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
>>   		unsigned int fence_num, void *p_data, unsigned int bytes)
>>   {
>>   	if (fence_num >= vgpu_fence_sz(vgpu)) {
>> +		if (!vgpu->pv_notified) {
>> +			/* When guest access oob fence regs without access
>> +			 * pv_info first, we treat guest not supporting GVT,
>> +			 * and we will let vgpu enter failsafe mode.
>> +			 */
>> +			vgpu->failsafe = true;
>> +			pr_err("***Detected guest not supporting GVT-g***\n");
>> +			pr_err("***Please update your guest driver*******\n");
>> +			pr_err("***Entering failsafe mode****************\n");
>> +			return -EINVAL;
>> +		}
>>   		gvt_err("vgpu%d: found oob fence register access\n",
>>   				vgpu->id);
> Mine, this slice would be a function like gvt_enter_failsafe_mode()? It
> duplicate with below block.
Here the error log may vary due to different situations, that's why I 
didn't encapsule them with
an function.

>
>>   		gvt_err("vgpu%d: total fence num %d access fence num %d\n",
>> @@ -1001,6 +1012,7 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
>>   	if (invalid_read)
>>   		gvt_err("invalid pvinfo read: [%x:%x] = %x\n",
>>   				offset, bytes, *(u32 *)p_data);
>> +	vgpu->pv_notified = true;
>>   	return 0;
>>   }
>>   
>> @@ -1318,6 +1330,20 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
>>   	bool enable_execlist;
>>   
>>   	write_vreg(vgpu, offset, p_data, bytes);
>> +
>> +	if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
>> +			(data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
>> +			&& !vgpu->pv_notified) {
>> +		/* when PPGTT mode enabled, we will check if guest has called
>> +		 * pvinfo, if not, we will treat this guest as non-gvtg-aware
>> +		 * guest, and stop emulating its cfg space, mmio, gtt, etc.
>> +		 */
>> +		vgpu->failsafe = true;
>> +		pr_err("***Detected guest not supporting GVT-g***\n");
>> +		pr_err("***Please update your guest driver*******\n");
>> +		pr_err("***Entering failsafe mode****************\n");
>> +		return 0;
>> +	}
>>   	if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
>>   			|| (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
>>   		enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
>> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
>> index 67d471c..0d1851a 100644
>> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
>> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
>> @@ -224,6 +224,8 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
>>   		goto out_free_vgpu;
>>   
>>   	vgpu->id = ret;
>> +	vgpu->failsafe = false;
>> +	vgpu->pv_notified = false;
> not need, since vgpu is alloced with zalloc.
Agree with you, it only to explicitly set the default value. I can 
remove it.
>> -- 
>> 1.9.1
>>
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>> intel-gvt-dev at lists.freedesktop.org
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