[PATCH v2] drm/i915/gvt: enter failsafe mode when guest requires more resources

He, Min min.he at intel.com
Thu Feb 16 06:14:36 UTC 2017


Sent a wrong patch.  Please ignore this one and I'll send out it again.

> -----Original Message-----
> From: He, Min
> Sent: Thursday, February 16, 2017 2:02 PM
> To: intel-gvt-dev at lists.freedesktop.org
> Cc: He, Min <min.he at intel.com>; Zhang, Pei <pei.zhang at intel.com>
> Subject: [PATCH v2] drm/i915/gvt: enter failsafe mode when guest requires
> more resources
> 
> Windows guest will notitfy GVT-g to request more resources through g2v
> interface, when its resources are not enough.
> This patch is to handle this case and let vgpu enter failsafe mode to
> avoid too many error messages.
> 
> Signed-off-by: Min He <min.he at intel.com>
> Signed-off-by: Pei Zhang <pei.zhang at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
> b/drivers/gpu/drm/i915/gvt/handlers.c
> index 03f52a1..51c1c57 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -152,6 +152,7 @@ static int render_mmio_to_ring_id(struct intel_gvt *gvt,
> unsigned int reg)
> 
>  enum {
>  	UNSUPPORTED_GUESTS,
> +	INSUFFICIENT_RESOURCE,
>  } FAILSAFE_REASON;
> 
>  static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
> @@ -161,6 +162,9 @@ static void enter_failsafe_mode(struct intel_vgpu *vgpu,
> int reason)
>  		pr_err("***Detected guest not supporting GVT-g***\n");
>  		pr_err("***Please update your guest driver*******\n");
>  		break;
> +	case INSUFFICIENT_RESOURCE:
> +		pr_err("***Guest requests more resource**********\n");
> +		pr_err("***Please try another VGPU type**********\n");
>  	default:
>  		break;
>  	}
> @@ -1105,6 +1109,9 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu,
> unsigned int offset,
>  	case _vgtif_reg(execlist_context_descriptor_lo):
>  	case _vgtif_reg(execlist_context_descriptor_hi):
>  		break;
> +	case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[4]):
> +		enter_failsafe_mode(vgpu, INSUFFICIENT_RESOURCE);
> +		break;
>  	default:
>  		gvt_err("invalid pvinfo write offset %x bytes %x data %x\n",
>  				offset, bytes, data);
> --
> 1.9.1



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