[PATCH] drm/915/gvt: add pcode read/write emulation of BDW

[Zhenyu Wang]

On 2017.02.17 15:47:30 +0800, Weinan Li wrote:
> Add pcode read/write emulation in gvt for BDW. The pcode read or write from
> guest won't real write to hardware, host maintain it.
> 
> Signed-off-by: Weinan Li <weinan.z.li at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index ab2ea15..b4bd514 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1203,7 +1203,7 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
>  	u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
>  
>  	switch (cmd) {
> -	case 0x6:
> +	case GEN9_PCODE_READ_MEM_LATENCY:
>  		/**
>  		 * "Read memory latency" command on gen9.
>  		 * Below memory latency values are read
> @@ -1214,7 +1214,7 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
>  		else
>  			*data0 = 0x61514b3d;
>  		break;
> -	case 0x5:
> +	case GEN6_PCODE_READ_RC6VIDS:
>  		*data0 |= 0x1;
>  		break;
>  	}
> @@ -2159,7 +2159,6 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  	MMIO_D(0x1a054, D_ALL);
>  
>  	MMIO_D(0x44070, D_ALL);
> -
>  	MMIO_D(0x215c, D_HSW_PLUS);
>  	MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
>  	MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
> @@ -2331,6 +2330,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
>  	MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>  	MMIO_D(0x1c054, D_BDW_PLUS);
>  
> +	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> +

There seems multiple entries for this, that will cause a dup error message.

-- 
Open Source Technology Center, Intel ltd.

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