[PATCH 2/2] drm/i915/gvt: implement override and restore call back for GFX_MODE

[Chuanxiao Dong]

When host and guest are using different ring submission, host cannot
use the GFX_MODE register value from guest. So implement the override
and restore call backs to handle GFX_MODE properly

Signed-off-by: Chuanxiao Dong <chuanxiao.dong at intel.com>
---
 drivers/gpu/drm/i915/gvt/render.c | 74 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 70 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index 7997d70..11f2507 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -48,8 +48,68 @@ struct render_mmio {
 	u32 original_bits;
 };
 
+static void render_mmio_override(struct render_mmio *mmio,
+		u32 *v, u32 mask, u32 override_bits)
+{
+	u32 temp_v = *v;
+
+	if ((temp_v & mask) == override_bits) {
+		mmio->override_mask = 0;
+		mmio->original_bits = 0;
+		return;
+	}
+
+	/* record which bits are changed */
+	mmio->original_bits = temp_v & mask;
+	mmio->override_mask = mask;
+
+	/* set the new value */
+	temp_v &= ~mask;
+	*v = (temp_v | override_bits);
+}
+
+static void render_mmio_override_gfx_mode(struct render_mmio *mmio, u32 *v)
+{
+	u32 mask, override_bits;
+
+	if (!v || !mmio)
+		return;
+
+	if (i915.enable_guc_submission) {
+		mask = GFX_FORWARD_VBLANK_MASK | GFX_INTERRUPT_STEERING;
+		override_bits = GFX_FORWARD_VBLANK_NEVER |
+			GFX_INTERRUPT_STEERING;
+	} else {
+		mask = GFX_INTERRUPT_STEERING;
+		override_bits = 0;
+	}
+
+	render_mmio_override(mmio, v, mask, override_bits);
+}
+
+static void render_mmio_restore(struct render_mmio *mmio, u32 *v)
+{
+	u32 temp_v;
+
+	if (!v || !mmio || !mmio->override_mask)
+		return;
+
+	/*
+	 * remove the host override bits and
+	 * restore back the guest mmio
+	 */
+	temp_v = *v;
+	temp_v &= ~mmio->override_mask;
+	*v = temp_v | mmio->original_bits;
+
+	mmio->override_mask = 0;
+	mmio->original_bits = 0;
+}
+
 static struct render_mmio gen8_render_mmio_list[] = {
-	{RCS, _MMIO(0x229c), 0xffff, false},
+	{RCS, _MMIO(0x229c), 0xffff, false,
+		render_mmio_override_gfx_mode,
+		render_mmio_restore},
 	{RCS, _MMIO(0x2248), 0x0, false},
 	{RCS, _MMIO(0x2098), 0x0, false},
 	{RCS, _MMIO(0x20c0), 0xffff, true},
@@ -72,7 +132,9 @@ static struct render_mmio gen8_render_mmio_list[] = {
 	{RCS, _MMIO(0x7300), 0xffff, true},
 	{RCS, _MMIO(0x83a4), 0xffff, true},
 
-	{BCS, _MMIO(0x2229c), 0xffff, false},
+	{BCS, _MMIO(0x2229c), 0xffff, false,
+		render_mmio_override_gfx_mode,
+		render_mmio_restore},
 	{BCS, _MMIO(0x2209c), 0xffff, false},
 	{BCS, _MMIO(0x220c0), 0xffff, false},
 	{BCS, _MMIO(0x22098), 0x0, false},
@@ -80,7 +142,9 @@ static struct render_mmio gen8_render_mmio_list[] = {
 };
 
 static struct render_mmio gen9_render_mmio_list[] = {
-	{RCS, _MMIO(0x229c), 0xffff, false},
+	{RCS, _MMIO(0x229c), 0xffff, false,
+		render_mmio_override_gfx_mode,
+		render_mmio_restore},
 	{RCS, _MMIO(0x2248), 0x0, false},
 	{RCS, _MMIO(0x2098), 0x0, false},
 	{RCS, _MMIO(0x20c0), 0xffff, true},
@@ -121,7 +185,9 @@ static struct render_mmio gen9_render_mmio_list[] = {
 	{RCS, _MMIO(0x4df0), 0, false},
 	{RCS, _MMIO(0x4df4), 0, false},
 
-	{BCS, _MMIO(0x2229c), 0xffff, false},
+	{BCS, _MMIO(0x2229c), 0xffff, false,
+		render_mmio_override_gfx_mode,
+		render_mmio_restore},
 	{BCS, _MMIO(0x2209c), 0xffff, false},
 	{BCS, _MMIO(0x220c0), 0xffff, false},
 	{BCS, _MMIO(0x22098), 0x0, false},
-- 
2.7.4