[PATCH v2 2/2] drm/i915/gvt: Audit and shadow workload during ELSP writing

[Zhi Wang]

Reviewed-by: Zhi Wang <zhi.a.wang at intel.com>

Thanks for the patch! :P

On 06/22/17 09:19, Gao, Ping A wrote:
> Ping for review!
>
>
> On 2017/6/20 15:46, Gao, Ping A wrote:
>> Hi Zhi,
>>
>>   
>>
>> Thanks for giving review by to [PATCH v3 1/2] drm/i915/gvt: Factor out
>> scan and shadow from workload dispatch.
>>
>>   
>>
>> How about this patch? Any further comments?
>>
>>   
>>
>> --Ping
>>
>>
>> On 2017/6/8 10:34, Ping Gao wrote:
>>> Let the workload audit and shadow ahead of vGPU scheduling, that
>>> will eliminate GPU idle time and improve performance for multi-VM.
>>>
>>> The performance of Heaven running simultaneously in 3VMs has
>>> improved 20% after this patch.
>>>
>>> v2:Remove condition current->vgpu==vgpu when shadow during ELSP
>>> writing.
>>>
>>> Signed-off-by: Ping Gao <ping.a.gao at intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/gvt/execlist.c  | 11 +++++++++++
>>>   drivers/gpu/drm/i915/gvt/scheduler.c |  7 +++++++
>>>   drivers/gpu/drm/i915/gvt/scheduler.h |  1 +
>>>   3 files changed, 19 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
>>> index dca989e..42c63ec 100644
>>> --- a/drivers/gpu/drm/i915/gvt/execlist.c
>>> +++ b/drivers/gpu/drm/i915/gvt/execlist.c
>>> @@ -605,6 +605,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
>>>   	struct list_head *q = workload_q_head(vgpu, ring_id);
>>>   	struct intel_vgpu_workload *last_workload = get_last_workload(q);
>>>   	struct intel_vgpu_workload *workload = NULL;
>>> +	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
>>>   	u64 ring_context_gpa;
>>>   	u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
>>>   	int ret;
>>> @@ -668,6 +669,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
>>>   	workload->complete = complete_execlist_workload;
>>>   	workload->status = -EINPROGRESS;
>>>   	workload->emulate_schedule_in = emulate_schedule_in;
>>> +	workload->shadowed = false;
>>>   
>>>   	if (ring_id == RCS) {
>>>   		intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
>>> @@ -701,6 +703,15 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
>>>   		return ret;
>>>   	}
>>>   
>>> +	/* Only scan and shadow the first workload in the queue
>>> +	 * as there is only one pre-allocated buf-obj for shadow.
>>> +	 */
>>> +	if (list_empty(workload_q_head(vgpu, ring_id))) {
>>> +		mutex_lock(&dev_priv->drm.struct_mutex);
>>> +		intel_gvt_scan_and_shadow_workload(workload);
>>> +		mutex_unlock(&dev_priv->drm.struct_mutex);
>>> +	}
>>> +
>>>   	queue_workload(workload);
>>>   	return 0;
>>>   }
>>> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
>>> index 3a78e7e..f77abd4 100644
>>> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
>>> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
>>> @@ -189,6 +189,9 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
>>>   	struct intel_vgpu *vgpu = workload->vgpu;
>>>   	int ret;
>>>   
>>> +	if (workload->shadowed)
>>> +		return 0;
>>> +
>>>   	shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
>>>   	shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
>>>   				    GEN8_CTX_ADDRESSING_MODE_SHIFT;
>>> @@ -216,6 +219,10 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
>>>   	}
>>>   
>>>   	ret = populate_shadow_context(workload);
>>> +	if (ret)
>>> +		goto out;
>>> +
>>> +	workload->shadowed = true;
>>>   
>>>   out:
>>>   	return ret;
>>> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
>>> index 2cd725c..575659e 100644
>>> --- a/drivers/gpu/drm/i915/gvt/scheduler.h
>>> +++ b/drivers/gpu/drm/i915/gvt/scheduler.h
>>> @@ -78,6 +78,7 @@ struct intel_vgpu_workload {
>>>   	struct drm_i915_gem_request *req;
>>>   	/* if this workload has been dispatched to i915? */
>>>   	bool dispatched;
>>> +	bool shadowed;
>>>   	int status;
>>>   
>>>   	struct intel_vgpu_mm *shadow_mm;
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