[PATCH] drm/i915/gvt: remove untracked mmio warnings

[Zhao Yan]

correct some registers' platform attribute and add more registers into
tracked list

Signed-off-by: Zhao Yan <yan.y.zhao at intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 548aedf..3e4ed8a 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2196,7 +2196,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(GEN6_PMINTRMSK, D_ALL);
 	MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
 	MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
-	MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
+	MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW | D_SKL, NULL,
+			power_well_ctl_mmio_write);
 	MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
 	MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
 	MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
@@ -2570,6 +2571,14 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
 	MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+	MMIO_D(0x42080, D_BDW);
+	MMIO_D(0x42090, D_BDW);
+	MMIO_DFH(_REG_VCS2_EXCC, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+	MMIO_D(0x2b20, D_BDW_PLUS);
+	MMIO_D(0xd00, D_BDW | D_SKL);
+	MMIO_D(0xd40, D_BDW | D_SKL);
+	MMIO_D(0x6e544, D_BDW | D_SKL_PLUS);
 	return 0;
 }
 
@@ -2777,12 +2786,10 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(0x67054, D_SKL);
 	MMIO_D(0x6e560, D_SKL);
 	MMIO_D(0x6e554, D_SKL);
-	MMIO_D(0x2b20, D_SKL);
 	MMIO_D(0x65f00, D_SKL);
 	MMIO_D(0x65f08, D_SKL);
 	MMIO_D(0x320f0, D_SKL);
 
-	MMIO_DFH(_REG_VCS2_EXCC, D_SKL, F_CMD_ACCESS, NULL, NULL);
 	MMIO_D(0x70034, D_SKL);
 	MMIO_D(0x71034, D_SKL);
 	MMIO_D(0x72034, D_SKL);
@@ -2798,6 +2805,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 	MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL, F_MODE_MASK | F_CMD_ACCESS,
 		NULL, NULL);
+	MMIO_D(0x4540c, D_SKL);
+	MMIO_D(FBC_LLC_READ_CTRL, D_SKL);
 	return 0;
 }
 
-- 
1.9.1