[PATCH v4] drm/i915/gvt: handle force-nonpriv registers, cmd parser part

[Zhenyu Wang]

On 2017.03.09 10:09:44 +0800, Zhao Yan wrote:
> this patch adds force non-priv registers check in LRI cmds handler
> 
> v4:
> transform is_force_nonpriv_mmio() from macro to inline fuction to eliminate
> checkpatch warning
> 
> v3:
> per zhenyu's comment, fix some style warnings
> 
> v2:
> per zhenyu's comment, refine the code to remove cascaded ifs
> 
> Signed-off-by: Zhao Yan <yan.y.zhao at intel.com>
> ---

applied, thanks!

>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/gvt/handlers.c   | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/gvt/mmio.h       |  3 +++
>  3 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 81076d8..f48b5d0 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -817,6 +817,25 @@ static bool is_shadowed_mmio(unsigned int offset)
>  	return ret;
>  }
>  
> +static inline bool is_force_nonpriv_mmio(unsigned int offset)
> +{
> +	return (offset >= 0x24d0 && offset < 0x2500);
> +}
> +
> +static int force_nonpriv_reg_handler(struct parser_exec_state *s,
> +				     unsigned int offset, unsigned int index)
> +{
> +	struct intel_gvt *gvt = s->vgpu->gvt;
> +	unsigned int data = cmd_val(s, index + 1);
> +
> +	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
> +		gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
> +			offset, data);
> +		return -EINVAL;
> +	}
> +	return 0;
> +}
> +
>  static int cmd_reg_handler(struct parser_exec_state *s,
>  	unsigned int offset, unsigned int index, char *cmd)
>  {
> @@ -841,6 +860,10 @@ static int cmd_reg_handler(struct parser_exec_state *s,
>  		return 0;
>  	}
>  
> +	if (is_force_nonpriv_mmio(offset) &&
> +	    force_nonpriv_reg_handler(s, offset, index))
> +		return -EINVAL;
> +
>  	if (offset == i915_mmio_reg_offset(DERRMR) ||
>  		offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
>  		/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 450072c..2048572 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2998,3 +2998,20 @@ int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
>  	write_vreg(vgpu, offset, p_data, bytes);
>  	return 0;
>  }
> +
> +/**
> + * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
> + * force-nopriv register
> + *
> + * @gvt: a GVT device
> + * @offset: register offset
> + *
> + * Returns:
> + * True if the register is in force-nonpriv whitelist;
> + * False if outside;
> + */
> +bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
> +					  unsigned int offset)
> +{
> +	return in_whitelist(offset);
> +}
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
> index 3bc620f..a3a0270 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.h
> +++ b/drivers/gpu/drm/i915/gvt/mmio.h
> @@ -107,4 +107,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
>  				 void *p_data, unsigned int bytes);
>  int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
>  				  void *p_data, unsigned int bytes);
> +
> +bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
> +					  unsigned int offset);
>  #endif
> -- 
> 1.9.1
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
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