[PATCH v5 7/9] drm/i915/gvt: define weight according to vGPU type
Tian, Kevin
kevin.tian at intel.com
Wed Mar 15 03:28:15 UTC 2017
> From: Ping Gao
> Sent: Thursday, March 9, 2017 8:46 AM
>
> The weight define proportional control of the vGPU resource between
> vGPUs, different vGPU types has different fixed weight definition.
> If different type vGPUs been created at the same time, the vGPU resource
> ratio between them is equal with ratio of weight.
better give some examples here.
Also please add a TODO - we'll allow user controlled weight setting
in the future.
>
> v4: rebase on the fixed vGPU type
> v5: rebase on the newest code and add inline comments for weight.
>
> Signed-off-by: Ping Gao <ping.a.gao at intel.com>
> ---
> drivers/gpu/drm/i915/gvt/gvt.h | 4 ++++
> drivers/gpu/drm/i915/gvt/kvmgt.c | 6 ++++--
> drivers/gpu/drm/i915/gvt/sched_policy.c | 1 +
> drivers/gpu/drm/i915/gvt/vgpu.c | 21 ++++++++++++++++-----
> 4 files changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> index 563ed22..0f53f5d 100644
> --- a/drivers/gpu/drm/i915/gvt/gvt.h
> +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> @@ -151,6 +151,7 @@ struct intel_vgpu {
> bool failsafe;
> bool resetting;
> void *sched_data;
> + struct intel_sched_ctl sched_ctl;
>
> struct intel_vgpu_fence fence;
> struct intel_vgpu_gm gm;
> @@ -221,6 +222,7 @@ struct intel_vgpu_type {
> unsigned int low_gm_size;
> unsigned int high_gm_size;
> unsigned int fence;
> + unsigned int weight;
do we need this field? Can we automatically calculate based on
type and then apply to the field in vgpu structure?
> enum intel_vgpu_edid resolution;
> };
>
> @@ -330,6 +332,8 @@ struct intel_vgpu_creation_params {
> __u64 resolution;
> __s32 primary;
> __u64 vgpu_id;
> +
> + __u32 weight;
> };
>
> int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, diff --git
> a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index 84d8016..55be2f2 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -295,10 +295,12 @@ static ssize_t description_show(struct kobject
> *kobj, struct device *dev,
> return 0;
>
> return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n"
> - "fence: %d\nresolution: %s\n",
> + "fence: %d\nresolution: %s\n"
> + "weight: %d\n",
> BYTES_TO_MB(type->low_gm_size),
> BYTES_TO_MB(type->high_gm_size),
> - type->fence, vgpu_edid_str(type->resolution));
> + type->fence, vgpu_edid_str(type->resolution),
> + type->weight);
> }
>
> static MDEV_TYPE_ATTR_RO(available_instances);
> diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c
> b/drivers/gpu/drm/i915/gvt/sched_policy.c
> index e0311c8..8fd1fa3 100644
> --- a/drivers/gpu/drm/i915/gvt/sched_policy.c
> +++ b/drivers/gpu/drm/i915/gvt/sched_policy.c
> @@ -340,6 +340,7 @@ static int tbs_sched_init_vgpu(struct intel_vgpu
> *vgpu)
> if (!data)
> return -ENOMEM;
>
> + data->sched_ctl.weight = vgpu->sched_ctl.weight;
> data->vgpu = vgpu;
> INIT_LIST_HEAD(&data->list);
> INIT_LIST_HEAD(&data->lru_list);
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c
> b/drivers/gpu/drm/i915/gvt/vgpu.c index 150c26d..3e652e2 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -68,14 +68,21 @@ static struct {
> unsigned int low_mm;
> unsigned int high_mm;
> unsigned int fence;
> +
> + /* A vGPU with a weight of 8 will get twice as much GPU
> + * as a vGPU with a weight of 4 on a contended host. Legal
> + * weights range from 1 to 65535 and different vGPU type
> + * has different weight set.
> + */
> + unsigned int weight;
please define a macro for such range limitation
> enum intel_vgpu_edid edid;
> char *name;
> } vgpu_types[] = {
> /* Fixed vGPU type table */
> - { MB_TO_BYTES(64), MB_TO_BYTES(512), 4, GVT_EDID_1024_768,
> "8" },
> - { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, GVT_EDID_1920_1200,
> "4" },
> - { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4,
> GVT_EDID_1920_1200, "2" },
> - { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4,
> GVT_EDID_1920_1200, "1" },
> + { MB_TO_BYTES(64), MB_TO_BYTES(512), 4, 1, GVT_EDID_1024_768,
> "8" },
> + { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, 2,
> GVT_EDID_1920_1200, "4" },
> + { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, 4,
> GVT_EDID_1920_1200, "2" },
> + { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, 8,
> GVT_EDID_1920_1200, "1"
> +},
> };
>
> /**
> @@ -120,6 +127,7 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
> gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
> gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
> gvt->types[i].fence = vgpu_types[i].fence;
> + gvt->types[i].weight = vgpu_types[i].weight;
> gvt->types[i].resolution = vgpu_types[i].edid;
> gvt->types[i].avail_instance = min(low_avail /
> vgpu_types[i].low_mm,
> high_avail /
> vgpu_types[i].high_mm); @@ -131,11 +139,12 @@ int
> intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
> sprintf(gvt->types[i].name, "GVTg_V5_%s",
> vgpu_types[i].name);
>
> - gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence
> %u res %s\n",
> + gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence
> %u weight %u
> +res %s\n",
> i, gvt->types[i].name,
> gvt->types[i].avail_instance,
> gvt->types[i].low_gm_size,
> gvt->types[i].high_gm_size, gvt->types[i].fence,
> + gvt->types[i].weight,
> vgpu_edid_str(gvt->types[i].resolution));
> }
>
> @@ -290,6 +299,7 @@ static struct intel_vgpu
> *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
> vgpu->id = ret;
> vgpu->handle = param->handle;
> vgpu->gvt = gvt;
> + vgpu->sched_ctl.weight = param->weight;
> bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
>
> intel_vgpu_init_cfg_space(vgpu, param->primary); @@ -376,6 +386,7
> @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
> param.low_gm_sz = type->low_gm_size;
> param.high_gm_sz = type->high_gm_size;
> param.fence_sz = type->fence;
> + param.weight = type->weight;
> param.resolution = type->resolution;
>
> /* XXX current param based on MB */
> --
> 2.7.4
>
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