[PATCH] drm/i915/gvt: add write handler for mmio mbctl

[Zhenyu Wang]

On 2017.03.17 17:28:08 +0800, Pei Zhang wrote:
> Guest will write mmio mbctl which need a special handler in gvt to
> clear the bit 4 to inidcate the write operation success.
> 
> Signed-off-by: Pei Zhang <pei.zhang at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 37ac507..a63b2e6 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -971,6 +971,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
>  	return 0;
>  }
>  
> +static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
> +		void *p_data, unsigned int bytes)
> +{
> +	*(u32 *)p_data &= ~0x10;
> +	write_vreg(vgpu, offset, p_data, bytes);
> +	return 0;

Should just use GEN6_MBCTL_ENABLE_BOOT_FETCH

> +}
> +
>  static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
>  		void *p_data, unsigned int bytes)
>  {
> @@ -2224,7 +2232,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  	MMIO_D(0x7180, D_ALL);
>  	MMIO_D(0x7408, D_ALL);
>  	MMIO_D(0x7c00, D_ALL);
> -	MMIO_D(GEN6_MBCTL, D_ALL);
> +	MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>  	MMIO_D(0x911c, D_ALL);
>  	MMIO_D(0x9120, D_ALL);
>  	MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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