[PATCH v2] drm/i915/gvt: set shadow entry point to scratch page while p2m failed

[Zhenyu Wang]

On 2017.03.17 10:29:58 +0800, Xiaoguang Chen wrote:
> Sometimes guest driver will write part of the GGTT entry(4 bytes)then
> use it which will lead to a failure while trying to translate the gpa
> to hpa.
> Now in this situation we let the shadow entry pointing to a scratch page.
>

This seems ignore previous noted guest entry partial update issue,
shouldn't drop that info. And as noted on irc, we need to add code
comment on this p2m failure handling.

> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> Signed-off-by: Xiaoguang Chen <xiaoguang.chen at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index da73127..3bae2e5 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -1837,11 +1837,11 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
>  		ret = gtt_entry_p2m(vgpu, &e, &m);
>  		if (ret) {
>  			gvt_vgpu_err("fail to translate guest gtt entry\n");
> -			return ret;
> +			ops->set_pfn(&m, vgpu->gtt.scratch_pt[GTT_TYPE_GGTT_PTE].page_mfn);
>  		}
>  	} else {
>  		m = e;
> -		m.val64 = 0;
> +		ops->set_pfn(&m, vgpu->gtt.scratch_pt[GTT_TYPE_GGTT_PTE].page_mfn);
>  	}
>  
>  	ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index);
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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