[PATCH] drm/i915/gvt: update guest page table even p2m faild

Zhi Wang zhi.a.wang at intel.com
Fri Mar 17 07:23:50 UTC 2017


Hi Min:
     What do you mean about our PPGTT issue happened in the last level 
PPGTT entry? :)

 From my view, the new solution is better than the old solution as it 
doesn't introduce assumptions and cause any other side effects. The old 
solution relies on the guest to follow the assumptions, if guest doesn't 
follow the assumptions, we have to dig guest driver.

For the PPGTT partial write issue, the upstream branch introduces a 
"post-sync" list, every PPGTT page table page has a post-sync bitmap to 
indicate the page table entry need to be shadowed when submission.

Thanks,
Zhi.

于 03/17/17 10:58, He, Min 写道:
> Zhi,
> Unfortunately, our PPGTT issue happened in the last level PPGTT entry.
> For this GGTT case, I think we can still use the old solution, if guest updates
> both high and low DWs of an entry, then we will update its shadow. If not,
> we will store a scratch entry or not update it.
>
>> -----Original Message-----
>> From: Wang, Zhi A
>> Sent: Thursday, March 16, 2017 7:34 PM
>> To: He, Min <min.he at intel.com>; Chen, Xiaoguang
>> <xiaoguang.chen at intel.com>; intel-gvt-dev at lists.freedesktop.org
>> Subject: Re: [PATCH] drm/i915/gvt: update guest page table even p2m faild
>>
>> Hi Min:
>>       I also thought about this. If we did the same thing to PPGTT page
>> table, the effort could be worse as PPGTT is multi-level page table, if
>> we fail in one branch, we have to rewind everything we did in one trap.
>> But GGTT is only one-level page table. It should be easier to follow
>> this approach. For post-sync in GGTT, we have to specifically deal with
>> aperture e.g. we try to translate and update partial GGTT writes for
>> aperture and leave the high GM to post-sync. :P
>>
>> Thanks,
>> Zhi.
>>
>> 于 03/17/17 10:34, He, Min 写道:
>>> Zhi,
>>> But we should do our best to avoid this situation. We had partial entry update
>> in
>>> ppgtt table, just because we updated wrong value into the PPGTT table.
>>>
>>>> -----Original Message-----
>>>> From: Wang, Zhi A
>>>> Sent: Wednesday, March 15, 2017 11:00 PM
>>>> To: He, Min <min.he at intel.com>; Chen, Xiaoguang
>>>> <xiaoguang.chen at intel.com>; intel-gvt-dev at lists.freedesktop.org
>>>> Cc: Chen, Xiaoguang <xiaoguang.chen at intel.com>
>>>> Subject: RE: [PATCH] drm/i915/gvt: update guest page table even p2m faild
>>>>
>>>> Hi Min:
>>>>       Even the GGTT entry is not correct, it's caused by guest itself. E.g. guest
>> just
>>>> writes part of the entry then use it, it's a fault of guest not us. For us, we try
>> to
>>>> translate the "partial" GPA when guest write the entry, if succeed, it means,
>> the
>>>> GPA is a part of guest RAM, we update the shadow GGTT, if guest use it, then
>> it's
>>>> a fault of guest. If the GPA is not a part of guest RAM we set the shadow to
>>>> scratch page.
>>>>
>>>> Thanks,
>>>> Zhi.
>>>>
>>>> -----Original Message-----
>>>> From: intel-gvt-dev [mailto:intel-gvt-dev-bounces at lists.freedesktop.org] On
>>>> Behalf Of He, Min
>>>> Sent: Thursday, March 16, 2017 11:52 AM
>>>> To: Chen, Xiaoguang <xiaoguang.chen at intel.com>; intel-gvt-
>>>> dev at lists.freedesktop.org
>>>> Cc: Chen, Xiaoguang <xiaoguang.chen at intel.com>
>>>> Subject: RE: [PATCH] drm/i915/gvt: update guest page table even p2m faild
>>>>
>>>> This patch may cause an incorrect value to be written to the GTT table.
>>>> Do we have better solutions? For example, change back to the partial mode
>> of
>>>> the old vgt mode?
>>>>
>>>> Thanks.
>>>>
>>>>> -----Original Message-----
>>>>> From: intel-gvt-dev
>>>>> [mailto:intel-gvt-dev-bounces at lists.freedesktop.org] On Behalf Of
>>>>> Xiaoguang Chen
>>>>> Sent: Wednesday, March 15, 2017 7:09 PM
>>>>> To: intel-gvt-dev at lists.freedesktop.org
>>>>> Cc: Chen, Xiaoguang <xiaoguang.chen at intel.com>
>>>>> Subject: [PATCH] drm/i915/gvt: update guest page table even p2m faild
>>>>>
>>>>> Sometimes guest driver will write the gtt mmio page table with length
>>>>> of 4 while the entry size is 8. In this situation the p2m may failed.
>>>>> Even the p2m failed we should update the guest gtt mmio page table but
>>>>> not update the shadow gtt mmio page table.
>>>>>
>>>>> Signed-off-by: Xiaoguang Chen<xiaoguang.chen at intel.com>
>>>>> Reviewed-by: Zhi Wang <zhi.a.wang at intel.com>
>>>> _______________________________________________
>>>> intel-gvt-dev mailing list
>>>> intel-gvt-dev at lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
>


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