[PATCH] drm/i915/gvt: set shadow entry to scratch page while p2m failed

[Tian, Kevin]

> From: Xiaoguang Chen
> Sent: Tuesday, March 21, 2017 10:54 AM
> 
> Sometimes guest driver will only update partial of the GGTT entry then access
> it. In this situation a failure will happen while translating the gpa to hpa.
> Now in this situation we let the corresponding shadow entry pointing to a
> scratch page.

You might want to make this story complete, e.g. translation will happen
when guest updates the other part of the entry, etc.

> 
> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> Signed-off-by: Xiaoguang Chen <xiaoguang.chen at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index da73127..b832bea 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -1837,11 +1837,15 @@ static int emulate_gtt_mmio_write(struct
> intel_vgpu *vgpu, unsigned int off,
>  		ret = gtt_entry_p2m(vgpu, &e, &m);
>  		if (ret) {
>  			gvt_vgpu_err("fail to translate guest gtt entry\n");
> -			return ret;
> +			/* guest driver may read/write the entry when partial
> +			 * update the entry in this situation p2m will fail
> +			 * settting the shadow entry to point to a scratch
> page
> +			 */

Similarly this comment needs elaboration. Also it's not a 'failure',
but an intermediate state when handling such guest programming
pattern.

> +			ops->set_pfn(&m, gvt->gtt.scratch_ggtt_mfn);
>  		}
>  	} else {
>  		m = e;
> -		m.val64 = 0;
> +		ops->set_pfn(&m, gvt->gtt.scratch_ggtt_mfn);
>  	}
> 
>  	ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index);
> --
> 2.7.4
> 
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