[PATCH] drm/i915/gvt: exclude cfg space from failsafe mode

[Zhenyu Wang]

On 2017.03.30 10:35:19 +0800, changbin.du at intel.com wrote:
> From: Changbin Du <changbin.du at intel.com>
> 
> When test GVTg as below scenario:
>   VM boot --> failsafe --> kill qemu --> VM boot.
> Qemu report error at the second boot:
>   ERROR: PCI region size must be pow2 type=0x0, size=0x1fa1000
> 
> Qemu need access PCI_ROM_ADDRESS reg to determine the size of expansion
> PCI rom. The mechanism just like the BAR reg (write-read) and we should
> return the size 0 since we have no rom. If we reject the write to
> PCI_ROM_ADDRESS, Qemu cannot get the correct size of rom.
> 
> Essentially, GVTg failsafe mode should not break PCI function. So we
> exclude cfg space from failsafe mode. This can fix above issue.
> 
> Signed-off-by: Changbin Du <changbin.du at intel.com>
> ---

I need a Fixes: line and better to have fd.o bug number this fixes.

>  drivers/gpu/drm/i915/gvt/cfg_space.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
> index b7d7721..40af17e 100644
> --- a/drivers/gpu/drm/i915/gvt/cfg_space.c
> +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
> @@ -285,9 +285,6 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
>  {
>  	int ret;
>  
> -	if (vgpu->failsafe)
> -		return 0;
> -
>  	if (WARN_ON(bytes > 4))
>  		return -EINVAL;
>  
> -- 
> 2.7.4
> 
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> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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