[RESEND][PATCH v2] drm/i915/gvt: Disable compression workaround for Gen9

[Zhenyu Wang]

On 2017.05.17 15:49:01 +0800, Chuanxiao Dong wrote:
> With enabling this workaround, can observe GPU hang issue on Gen9. As
> currently host side doesn't have this workaround, disable it from GVT
> side.
> 
> v2:
> - Fix indent error.(Zhenyu)
>

Pushed, thx!

> Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> Signed-off-by: Chuanxiao Dong <chuanxiao.dong at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 30 +++++++++++++++++++++---------
>  1 file changed, 21 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index c995e54..0ffd696 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1366,18 +1366,28 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
>  		void *p_data, unsigned int bytes)
>  {
>  	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> -	i915_reg_t reg = {.reg = offset};
> +	u32 v = *(u32 *)p_data;
> +
> +	if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
> +		return intel_vgpu_default_mmio_write(vgpu,
> +				offset, p_data, bytes);
>  
>  	switch (offset) {
>  	case 0x4ddc:
> -		vgpu_vreg(vgpu, offset) = 0x8000003c;
> -		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */
> -		I915_WRITE(reg, vgpu_vreg(vgpu, offset));
> +		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
> +		vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
>  		break;
>  	case 0x42080:
> -		vgpu_vreg(vgpu, offset) = 0x8000;
> -		/* WaCompressedResourceDisplayNewHashMode:skl */
> -		I915_WRITE(reg, vgpu_vreg(vgpu, offset));
> +		/* bypass WaCompressedResourceDisplayNewHashMode */
> +		vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
> +		break;
> +	case 0xe194:
> +		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
> +		vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
> +		break;
> +	case 0x7014:
> +		/* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
> +		vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
>  		break;
>  	default:
>  		return -EINVAL;
> @@ -1634,7 +1644,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  	MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>  	MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>  		NULL, NULL);
> -	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
> +		 skl_misc_ctl_write);
>  	MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
>  	MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>  	MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
> @@ -2568,7 +2579,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
>  	MMIO_D(0x6e570, D_BDW_PLUS);
>  	MMIO_D(0x65f10, D_BDW_PLUS);
>  
> -	MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +	MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
> +		 skl_misc_ctl_write);
>  	MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>  	MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>  	MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -- 
> 2.7.4
> 

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 195 bytes
Desc: not available
URL: <https://lists.freedesktop.org/archives/intel-gvt-dev/attachments/20170517/c8c8527a/attachment.sig>