[PATCH 1/2] drm/i915/gvt: Add read handler for GDRST register
Zhenyu Wang
zhenyuw at linux.intel.com
Mon May 22 08:52:23 UTC 2017
On 2017.05.22 16:09:25 +0800, fred gao wrote:
> emulating the GDRST read behavior to ack the guest
> reset request.
>
> v2: split the original patch into two:
> GDRST read handler and virtual gpu reset by Zhengyu
>
> Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> Reviewed-by: Zhang Yulei <yulei.zhang at intel.com>
Again people gave you comment doesn't mean you can add r-b, not
to say it wasn't on public list.
> Signed-off-by: fred gao <fred.gao at intel.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 973396b..4db20ec 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -300,6 +300,14 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
> return 0;
> }
>
> +static int gdrst_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
> + void *p_data, unsigned int bytes)
> +{
> + *(u32 *)p_data = 0;
> +
> + return 0;
> +}
It looks not the correct way to fix this, as the problem is in GDRST write
handler, we didn't set correct vreg value after reset is done.
> +
> static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
> void *p_data, unsigned int bytes)
> {
> @@ -2221,7 +2229,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>
> MMIO_D(RSTDBYCTL, D_ALL);
>
> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> + MMIO_DH(GEN6_GDRST, D_ALL, gdrst_mmio_read, gdrst_mmio_write);
> MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write);
> MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> --
> 2.7.4
>
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> intel-gvt-dev at lists.freedesktop.org
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