[PATCH 2/2] drm/i915/gvt: Refine virtual reset function

[Zhenyu Wang]

On 2017.05.25 15:33:52 +0800, fred gao wrote:
> during the emulation of virtual reset:
> 1. only reset the engine related mmio ending with MMIO
>    offset Master_IRQ, not include display stuff.
> 
> 2. fences are not required to set default
>    value as well to prevent screen flicking.
> 
> this will fix the issue of Guest screen hang while running
> Force tdr in Linux guest.
> 
> v2:
> - only reset the engine related mmio. (Zhenyu & Zhiyuan)
> v3:
> - IMR/Ring mode registers are not save/restored. (Changbin)
> v4:
> - redefine the MMIO reset offset for easy understanding. (Zhenyu)
> - pvinfo can be reset. (Zhenyu)
> v5:
> - add more comments for mmio reset. (Zhenyu)
> 
> Cc: Changbin Du <changbin.du at intel.com>
> Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> Cc: Lv zhiyuan <zhiyuan.lv at intel.com>
> Cc: Zhang Yulei <yulei.zhang at intel.com>
> Signed-off-by: fred gao <fred.gao at intel.com>

Besides adding changelog in commit message, you need to specify patch version
as well, and in such update series with --in-reply-to to help me to reference.

Pushed, thx!

>  drivers/gpu/drm/i915/gvt/mmio.c | 28 ++++++++++++++++++++--------
>  drivers/gpu/drm/i915/gvt/mmio.h |  2 +-
>  drivers/gpu/drm/i915/gvt/vgpu.c |  9 +++++++--
>  3 files changed, 28 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
> index 35f6c47..9337cac 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio.c
> @@ -365,20 +365,32 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
>   * @vgpu: a vGPU
>   *
>   */
> -void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu)
> +void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
>  {
>  	struct intel_gvt *gvt = vgpu->gvt;
>  	const struct intel_gvt_device_info *info = &gvt->device_info;
> +	void  *mmio = gvt->firmware.mmio;
>  
> -	memcpy(vgpu->mmio.vreg, gvt->firmware.mmio, info->mmio_size);
> -	memcpy(vgpu->mmio.sreg, gvt->firmware.mmio, info->mmio_size);
> +	if (dmlr) {
> +		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
> +		memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
>  
> -	vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
> +		vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
>  
> -	/* set the bit 0:2(Core C-State ) to C0 */
> -	vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;
> +		/* set the bit 0:2(Core C-State ) to C0 */
> +		vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;
> +
> +		vgpu->mmio.disable_warn_untrack = false;
> +	} else {
> +#define GVT_GEN8_MMIO_RESET_OFFSET		(0x44200)
> +		/* only reset the engine related, so starting with 0x44200
> +		 * interrupt include DE,display mmio related will not be
> +		 * touched
> +		 */
> +		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
> +		memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
> +	}
>  
> -	vgpu->mmio.disable_warn_untrack = false;
>  }
>  
>  /**
> @@ -398,7 +410,7 @@ int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
>  
>  	vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
>  
> -	intel_vgpu_reset_mmio(vgpu);
> +	intel_vgpu_reset_mmio(vgpu, true);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
> index 7edd66f..36200f9 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.h
> +++ b/drivers/gpu/drm/i915/gvt/mmio.h
> @@ -88,7 +88,7 @@ struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
>  })
>  
>  int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
> -void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu);
> +void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
>  void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
>  
>  int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index 6e3cbd8..90c14e6 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -501,9 +501,14 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
>  
>  	/* full GPU reset or device model level reset */
>  	if (engine_mask == ALL_ENGINES || dmlr) {
> +
>  		intel_vgpu_reset_gtt(vgpu, dmlr);
> -		intel_vgpu_reset_resource(vgpu);
> -		intel_vgpu_reset_mmio(vgpu);
> +
> +		/*fence will not be reset during virtual reset */
> +		if (dmlr)
> +			intel_vgpu_reset_resource(vgpu);
> +
> +		intel_vgpu_reset_mmio(vgpu, dmlr);
>  		populate_pvinfo_page(vgpu);
>  		intel_vgpu_reset_display(vgpu);
>  
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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