[PATCH] drm/i915/gvt: Add runtime_pm get/put to proctect MMIO accessing
Dong, Chuanxiao
chuanxiao.dong at intel.com
Fri May 26 08:57:29 UTC 2017
> -----Original Message-----
> From: Zhenyu Wang [mailto:zhenyuw at linux.intel.com]
> Sent: Friday, May 26, 2017 4:20 PM
> To: Dong, Chuanxiao <chuanxiao.dong at intel.com>
> Cc: intel-gvt-dev at lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/gvt: Add runtime_pm get/put to proctect
> MMIO accessing
>
> On 2017.05.26 13:30:43 +0800, Chuanxiao Dong wrote:
> > In some cases, GVT-g is accessing MMIO without holding runtime_pm and
> > this patch can add the runtime_pm get/put to make sure when accessing
> > MMIO the i915 HW is really powered on.
> >
> > Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> > Signed-off-by: Chuanxiao Dong <chuanxiao.dong at intel.com>
> > ---
> > drivers/gpu/drm/i915/gvt/gtt.c | 2 ++
> > drivers/gpu/drm/i915/gvt/mmio.c | 4 ++++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c
> > b/drivers/gpu/drm/i915/gvt/gtt.c index c6f0077..13bfe09 100644
> > --- a/drivers/gpu/drm/i915/gvt/gtt.c
> > +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> > @@ -251,8 +251,10 @@ static void write_pte64(struct drm_i915_private
> > *dev_priv,
> >
> > writeq(pte, addr);
> >
> > + intel_runtime_pm_get(dev_priv);
> > I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
> > POSTING_READ(GFX_FLSH_CNTL_GEN6);
> > + intel_runtime_pm_put(dev_priv);
> > }
> >
> > static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt,
> > diff --git a/drivers/gpu/drm/i915/gvt/mmio.c
> > b/drivers/gpu/drm/i915/gvt/mmio.c index 35f6c47..22700ae 100644
> > --- a/drivers/gpu/drm/i915/gvt/mmio.c
> > +++ b/drivers/gpu/drm/i915/gvt/mmio.c
> > @@ -195,7 +195,9 @@ int intel_vgpu_emulate_mmio_read(struct
> intel_vgpu *vgpu, uint64_t pa,
> > if (WARN_ON(mmio->offset != offset))
> > goto err;
> > }
> > + intel_runtime_pm_get(gvt->dev_priv);
> > ret = mmio->read(vgpu, offset, p_data, bytes);
> > + intel_runtime_pm_put(gvt->dev_priv);
> > } else {
> > ret = intel_vgpu_default_mmio_read(vgpu, offset, p_data,
> bytes);
> >
> > @@ -315,7 +317,9 @@ int intel_vgpu_emulate_mmio_write(struct
> intel_vgpu *vgpu, uint64_t pa,
> > }
> >
> > if (!ro_mask) {
> > + intel_runtime_pm_get(gvt->dev_priv);
> > ret = mmio->write(vgpu, offset, p_data, bytes);
> > + intel_runtime_pm_put(gvt->dev_priv);
> > } else {
> > /* Protect RO bits like HW */
> > u64 data = 0;
>
> I still think we shouldn't have big hammer here as mostly our handlers won't
> invoke hw, might just take care for each specific case.
Sure. Will re-work on this and send out v2.
Thanks
Chuanxiao
>
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