[PATCH] drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition

[Zhenyu Wang]

On 2017.11.25 09:14:57 +0800, Xiong Zhang wrote:
> Signed-off-by: Xiong Zhang <xiong.y.zhang at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 3d6008b..71a0f2b 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -331,9 +331,9 @@ static inline int gtt_set_entry64(void *pt,
>  
>  #define GTT_HAW 46
>  
> -#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30)
> -#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21)
> -#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12)
> +#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30)) - 1) << 30)
> +#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21)) - 1) << 21)
> +#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12)) - 1) << 12)
>

could you add Fixes: line and commit description? and should cc stable?
yeah, I took wrongly on width vs. bit...

>  static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
>  {
> -- 
> 2.7.4
> 

-- 
Open Source Technology Center, Intel ltd.

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