[PATCH] drm/i915/gvt: handle untracked mmio

[Zhao Xinda]

The warning messages "untracked MMIO ..." are printed out from time
to time, add these MMIO registers into gvt track list to avoid the
warning message.

Signed-off-by: Zhao Xinda <xinda.zhao at intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 38 +++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 94fc0421..5ae17dd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1766,6 +1766,10 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(CURBASE(PIPE_B), D_ALL);
 	MMIO_D(CURBASE(PIPE_C), D_ALL);
 
+	MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
+	MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
+	MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
+
 	MMIO_D(0x700ac, D_ALL);
 	MMIO_D(0x710ac, D_ALL);
 	MMIO_D(0x720ac, D_ALL);
@@ -2277,6 +2281,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
 	MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
 	MMIO_D(GEN6_PMINTRMSK, D_ALL);
+
 	/*
 	 * Use an arbitrary power well controlled by the PWR_WELL_CTL
 	 * register.
@@ -2428,6 +2433,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 	MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
 	return 0;
 }
 
@@ -2555,6 +2561,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
 	MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
 
+	MMIO_D(CHICKEN_MISC_2, D_BDW_PLUS);
+
 	MMIO_D(WM_MISC, D_BDW);
 	MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
 
@@ -2615,6 +2623,22 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
 	MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+	MMIO_D(FBC_LLC_READ_CTRL, D_BDW_PLUS);
+
+	MMIO_D(GUC_BCS_RCS_IER, D_BDW_PLUS);
+	MMIO_D(GUC_VCS2_VCS1_IER, D_BDW_PLUS);
+	MMIO_D(GUC_WD_VECS_IER, D_BDW_PLUS);
+
+	MMIO_D(RPM_CONFIG0, D_BDW_PLUS);
+	MMIO_D(RC6_LOCATION, D_BDW_PLUS);
+
+	MMIO_D(0x4084, D_BDW_PLUS);
+
+	MMIO_D(0x4a50, D_BDW_PLUS);
+	MMIO_D(0x4a54, D_BDW_PLUS);
+	MMIO_D(0x4a58, D_BDW_PLUS);
+
 	return 0;
 }
 
@@ -2644,6 +2668,10 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
 	MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
 		skl_power_well_ctl_write);
+	MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_SKL_PLUS, NULL,
+		skl_power_well_ctl_write);
+	MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
+		skl_power_well_ctl_write);
 
 	MMIO_D(0xa210, D_SKL_PLUS);
 	MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
@@ -2845,6 +2873,10 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS);
 	MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS);
 
+	MMIO_D(_PLANE_KEYMAX_1(PIPE_A), D_SKL_PLUS);
+	MMIO_D(_PLANE_KEYMAX_1(PIPE_B), D_SKL_PLUS);
+	MMIO_D(_PLANE_KEYMAX_1(PIPE_C), D_SKL_PLUS);
+
 	MMIO_D(0x44500, D_SKL_PLUS);
 	MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
@@ -2853,6 +2885,12 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(0x4ab8, D_KBL);
 	MMIO_D(0x2248, D_SKL_PLUS | D_KBL);
 
+	MMIO_D(0x12058, D_SKL_PLUS);
+	MMIO_D(0x22058, D_SKL_PLUS);
+	MMIO_D(0x1a058, D_SKL_PLUS);
+
+	MMIO_D(CTC_MODE, D_SKL_PLUS);
+
 	return 0;
 }
 
-- 
2.7.4