[gvt-linux:gvt-next 40/41] drivers/gpu/drm/i915/gvt/vgpu.c:48:42: error: 'VGT_CAPS_HWSP_EMULATION' undeclared

[Li, Weinan Z]

It depends on this patch which already in gvt-staging/upstream.
commit 1fd51d9d97059cb7dd0bf7a3b6f7cb609d485718
    drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

Regards
Weinan
-----Original Message-----
From: Wu, Fengguang 
Sent: Saturday, October 21, 2017 7:44 PM
To: Li, Weinan Z <weinan.z.li at intel.com>
Cc: kbuild-all at 01.org; Wang, Zhenyu Z <zhenyu.z.wang at intel.com>; Zhu, Libo <libo.zhu at intel.com>; Xu, Terrence <terrence.xu at intel.com>; intel-gvt-dev at lists.freedesktop.org; Zhenyu Wang <zhenyuw at linux.intel.com>
Subject: [gvt-linux:gvt-next 40/41] drivers/gpu/drm/i915/gvt/vgpu.c:48:42: error: 'VGT_CAPS_HWSP_EMULATION' undeclared

tree:   https://github.com/01org/gvt-linux.git gvt-next
head:   e407bc575e24158b2b3844f934c8a2cdec8ae8e4
commit: 95ebdc1738c3d705e0c14d15f6a62d22cf1724c1 [40/41] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP
config: x86_64-randconfig-s5-10211749 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        git checkout 95ebdc1738c3d705e0c14d15f6a62d22cf1724c1
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/gvt/vgpu.c: In function 'populate_pvinfo_page':
>> drivers/gpu/drm/i915/gvt/vgpu.c:48:42: error: 'VGT_CAPS_HWSP_EMULATION' undeclared (first use in this function)
     vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
                                             ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/vgpu.c:48:42: note: each undeclared identifier is reported only once for each function it appears in

vim +/VGT_CAPS_HWSP_EMULATION +48 drivers/gpu/drm/i915/gvt/vgpu.c

    37	
    38	void populate_pvinfo_page(struct intel_vgpu *vgpu)
    39	{
    40		/* setup the ballooning information */
    41		vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
    42		vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
    43		vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
    44		vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
    45		vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
    46	
    47		vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
  > 48		vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
    49	
    50		vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
    51			vgpu_aperture_gmadr_base(vgpu);
    52		vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
    53			vgpu_aperture_sz(vgpu);
    54		vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
    55			vgpu_hidden_gmadr_base(vgpu);
    56		vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
    57			vgpu_hidden_sz(vgpu);
    58	
    59		vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
    60	
    61		gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
    62		gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
    63			vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
    64		gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
    65			vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
    66		gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
    67	
    68		WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
    69	}
    70	

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