[Intel-gfx] [PATCH] drm/i915: Fix DPLL warning when starting guest VM

[Zhao, Xinda]

> -----Original Message-----
> From: Zhenyu Wang [mailto:zhenyuw at linux.intel.com]
> Sent: Tuesday, October 31, 2017 2:52 PM
> To: Zhao, Xinda <xinda.zhao at intel.com>
> Cc: ville.syrjala at linux.intel.com; intel-gfx at lists.freedesktop.org;
> intel-gvt-dev at lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix DPLL warning when starting
> guest VM
> 
> On 2017.10.31 03:09:04 +0000, Zhao, Xinda wrote:
> > >
> > > On Mon, Oct 30, 2017 at 03:49:28PM +0200, Ville Syrjälä wrote:
> > > > On Mon, Oct 30, 2017 at 04:17:06PM +0800, Zhao, Xinda wrote:
> > > > > The warning is occurred in guest VM when trying to get clock in
> > > > > encoder initialization.
> > >
> > > What does guest VM mean here? gvt? If so, why do you claim to have
> > > an enabled port without an enabled pipe?
> >
> > [xinda]
> > Yes, gvt-g.
> >
> > We emulate a DP device on port B that is fixed to pipe A for each guest VM
> by setting following register, it is mandatory.
> > TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= (PORT_B <<
> TRANS_DDI_PORT_SHIFT);
> >
> > We don't emulate the status of pipe, whether it is enabled or not, it
> depends on the i915 setting in guest VM, it is optional.
> > The PIPECONF register will be trapped, but the behavior will not be
> emulated.
> >
> 
> Looks that's wrong behavior which means full virtualized display brokenness
> that still depends on some real hw status?

[xinda] 
Yes, consider the situation that PIPE A may be disabled in real hw, PIPE A should also be emulated in gvt, I will cook a new patch for this.
 
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