[PATCH] drm/i915/gvt: Add more tracked display and debug MMIOs

[changbin.du at intel.com]

From: Changbin Du <changbin.du at intel.com>

Add more display and debug registers to suppress below error storm.

[ 1040.871877] gvt: vgpu 6: untracked MMIO 00068260 len 4
[ 1040.871882] gvt: vgpu 6: untracked MMIO 000682d0 len 4
[ 1040.871887] gvt: vgpu 6: untracked MMIO 00068960 len 4
[ 1040.871888] gvt: vgpu 7: untracked MMIO 00070020 len 4
[ 1040.871892] gvt: vgpu 6: untracked MMIO 000689d0 len 4
[ 1040.871897] gvt: vgpu 6: untracked MMIO 00068a60 len 4
[ 1040.871902] gvt: vgpu 7: untracked MMIO 00070050 len 4
[ 1040.871907] gvt: vgpu 6: untracked MMIO 00068ad0 len 4
[ 1040.871913] gvt: vgpu 7: untracked MMIO 00071020 len 4
[ 1040.871914] gvt: vgpu 6: untracked MMIO 00069160 len 4
[ 1040.871919] gvt: vgpu 6: untracked MMIO 000691d0 len 4
[ 1040.871923] gvt: vgpu 7: untracked MMIO 00072020 len 4
[ 1040.871970] gvt: vgpu 6: untracked MMIO 00064c00 len 4
[ 1040.871976] gvt: vgpu 6: untracked MMIO 00064c10 len 4
[ 1040.871982] gvt: vgpu 6: untracked MMIO 00064c20 len 4
[ 1040.871994] gvt: vgpu 6: untracked MMIO 00064c80 len 4
[ 1040.872001] gvt: vgpu 6: untracked MMIO 00064c90 len 4
[ 1040.872009] gvt: vgpu 6: untracked MMIO 00064ca0 len 4
[ 1040.872023] gvt: vgpu 6: untracked MMIO 00051010 len 4
[ 1040.872029] gvt: vgpu 6: untracked MMIO 00051020 len 4
[ 1040.872037] gvt: vgpu 6: untracked MMIO 00051080 len 4
[ 1040.872055] gvt: vgpu 6: untracked MMIO 0004540c len 4
[ 1040.872062] gvt: vgpu 6: untracked MMIO 00060800 len 4
[ 1040.872068] gvt: vgpu 6: untracked MMIO 00061800 len 4
[ 1040.872074] gvt: vgpu 6: untracked MMIO 00062800 len 4
[ 1040.872080] gvt: vgpu 6: untracked MMIO 0006f800 len 4
[ 1040.872086] gvt: vgpu 6: untracked MMIO 0006f900 len 4
[ 1040.872115] gvt: vgpu 6: untracked MMIO 00070480 len 4
[ 1040.872133] gvt: vgpu 6: untracked MMIO 00071480 len 4
[ 1040.872171] gvt: vgpu 3: untracked MMIO 0001c238 len 4
[ 1040.872174] gvt: vgpu 4: untracked MMIO 0001c238 len 4
[ 1040.872175] gvt: vgpu 6: untracked MMIO 00060050 len 4
[ 1040.872179] gvt: vgpu 4: untracked MMIO 0001c370 len 4
[ 1040.872180] gvt: vgpu 3: untracked MMIO 0001c370 len 4
[ 1040.872181] gvt: vgpu 6: untracked MMIO 00060060 len 4
[ 1040.872183] gvt: vgpu 4: untracked MMIO 0001c374 len 4
[ 1040.872185] gvt: vgpu 3: untracked MMIO 0001c374 len 4
[ 1040.872186] gvt: vgpu 6: untracked MMIO 00060080 len 4
[ 1040.872187] gvt: vgpu 4: untracked MMIO 0001c378 len 4
[ 1040.872189] gvt: vgpu 3: untracked MMIO 0001c378 len 4

Signed-off-by: Changbin Du <changbin.du at intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 58 +++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a33c1c3e..f51b3b2 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2623,6 +2623,49 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
 	MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+	/* Transcoder debug regs. */
+	MMIO_D(_MMIO(0x70050), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x71050), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x72050), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x73050), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7B050), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7B850), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7D050), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7E050), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7F050), D_BDW_PLUS);
+
+	/* Transcoder 3D ctrl regs. */
+	MMIO_D(_MMIO(0x70020), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x71020), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x72020), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x73020), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7B020), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7B820), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x7F020), D_BDW_PLUS);
+
+	MMIO_D(_MMIO(_PHY_CTL_FAMILY_EDP), D_BDW_PLUS);
+	MMIO_D(_MMIO(_PHY_CTL_FAMILY_DDI), D_BDW_PLUS);
+	MMIO_D(_MMIO(_PHY_CTL_FAMILY_DDI_C), D_BDW_PLUS);
+
+	MMIO_D(HSW_PWR_WELL_CTL5, D_BDW_PLUS);
+	MMIO_D(HSW_PWR_WELL_CTL6, D_BDW_PLUS);
+
+	MMIO_D(_MMIO(0x60800), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x61800), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x62800), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x63800), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x6F800), D_BDW_PLUS);
+
+	MMIO_D(_MMIO(0x1C238), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x1C370), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x1C374), D_BDW_PLUS);
+	MMIO_D(_MMIO(0x1C378), D_BDW_PLUS);
+
+	MMIO_D(PIPE_CRC_CTL(PIPE_A), D_BDW_PLUS);
+	MMIO_D(PIPE_CRC_CTL(PIPE_B), D_BDW_PLUS);
+	MMIO_D(PIPE_CRC_CTL(PIPE_C), D_BDW_PLUS);
+
 	return 0;
 }
 
@@ -2859,6 +2902,21 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
 	MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
 
+	MMIO_D(SKL_PS_PWR_GATE(PIPE_A, 0), D_SKL_PLUS);
+	MMIO_D(SKL_PS_PWR_GATE(PIPE_A, 1), D_SKL_PLUS);
+	MMIO_D(SKL_PS_PWR_GATE(PIPE_B, 0), D_SKL_PLUS);
+	MMIO_D(SKL_PS_PWR_GATE(PIPE_B, 1), D_SKL_PLUS);
+	MMIO_D(SKL_PS_PWR_GATE(PIPE_C, 0), D_SKL_PLUS);
+	MMIO_D(SKL_PS_PWR_GATE(PIPE_C, 1), D_SKL_PLUS);
+
+	MMIO_D(_MMIO(_PS_ECC_STAT_1A), D_SKL_PLUS);
+	MMIO_D(_MMIO(_PS_ECC_STAT_2A), D_SKL_PLUS);
+	MMIO_D(_MMIO(_PS_ECC_STAT_1B), D_SKL_PLUS);
+	MMIO_D(_MMIO(_PS_ECC_STAT_2B), D_SKL_PLUS);
+	MMIO_D(_MMIO(_PS_ECC_STAT_1C), D_SKL_PLUS);
+
+	MMIO_D(EDP_PSR2_CTL, D_SKL_PLUS);
+
 	MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
 	MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
 	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
-- 
2.7.4