[PATCH v2] drm/i915/gvt: Fix drm_format_mod value for vGPU plane
Zhenyu Wang
zhenyuw at linux.intel.com
Thu Aug 30 02:29:53 UTC 2018
On 2018.08.30 08:37:00 +0800, Colin Xu wrote:
> On 8/29/18 10:43 AM, Zhenyu Wang wrote:
> > ping for comments...
> >
> > On 2018.08.21 14:29:47 +0800, Zhenyu Wang wrote:
> > > Physical plane's tiling mode value is given directly as
> > > drm_format_mod for plane query, which is not correct fourcc
> > > code. Fix it by using correct intel tiling fourcc mod definition.
> > >
> > > Current qemu seems also doesn't correctly utilize drm_format_mod
> > > for plane object setting. Anyway this is required to fix the usage.
> > >
> > > v2: Fix missed old 'tiled' use for stride calculation
> > >
> > > Fixes: e546e281d33d ("drm/i915/gvt: Dmabuf support for GVT-g")
> > > Cc: Tina Zhang <tina.zhang at intel.com>
> > > Cc: Gerd Hoffmann <kraxel at redhat.com>
> > > Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gvt/dmabuf.c | 33 +++++++++++++++++++++------
> > > drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 ++--
> > > drivers/gpu/drm/i915/gvt/fb_decoder.h | 2 +-
> > > 3 files changed, 29 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
> > > index 6e3f56684f4e..c022060797de 100644
> > > --- a/drivers/gpu/drm/i915/gvt/dmabuf.c
> > > +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
> > > @@ -170,20 +170,22 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev,
> > > unsigned int tiling_mode = 0;
> > > unsigned int stride = 0;
> > > - switch (info->drm_format_mod << 10) {
> > > - case PLANE_CTL_TILED_LINEAR:
> > > + switch (info->drm_format_mod) {
> > > + case 0:
>
> Will it be better to use pre-defined DRM_FORMAT_MOD_LINEAR instead of 0 as already did in i915,
> like referred intel_tile_width_bytes()?
>
yeah, good suggestion.
> > > tiling_mode = I915_TILING_NONE;
> > > break;
> > > - case PLANE_CTL_TILED_X:
> > > + case I915_FORMAT_MOD_X_TILED:
> > > tiling_mode = I915_TILING_X;
> > > stride = info->stride;
> > > break;
> > > - case PLANE_CTL_TILED_Y:
> > > + case I915_FORMAT_MOD_Y_TILED:
> > > + case I915_FORMAT_MOD_Yf_TILED:
> > > tiling_mode = I915_TILING_Y;
> > > stride = info->stride;
> > > break;
> > > default:
> > > - gvt_dbg_core("not supported tiling mode\n");
> > > + gvt_dbg_core("invalid drm_format_mod %llx for tiling\n",
> > > + info->drm_format_mod);
> > > }
> > > obj->tiling_and_stride = tiling_mode | stride;
> > > } else {
> > > @@ -222,9 +224,26 @@ static int vgpu_get_plane_info(struct drm_device *dev,
> > > info->height = p.height;
> > > info->stride = p.stride;
> > > info->drm_format = p.drm_format;
> > > - info->drm_format_mod = p.tiled;
> > > +
> > > + switch (p.tiled) {
> > > + case PLANE_CTL_TILED_LINEAR:
> > > + info->drm_format_mod = 0;
>
> Ditto.
Sure.
>
> > > + break;
> > > + case PLANE_CTL_TILED_X:
> > > + info->drm_format_mod = I915_FORMAT_MOD_X_TILED;
> > > + break;
> > > + case PLANE_CTL_TILED_Y:
> > > + info->drm_format_mod = I915_FORMAT_MOD_Y_TILED;
> > > + break;
> > > + case PLANE_CTL_TILED_YF:
> > > + info->drm_format_mod = I915_FORMAT_MOD_Yf_TILED;
> > > + break;
> > > + default:
> > > + gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);
> > > + }
> > > +
> > > info->size = (((p.stride * p.height * p.bpp) / 8) +
> > > - (PAGE_SIZE - 1)) >> PAGE_SHIFT;
> > > + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
> > > } else if (plane_id == DRM_PLANE_TYPE_CURSOR) {
> > > ret = intel_vgpu_decode_cursor_plane(vgpu, &c);
> > > if (ret)
> > > diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> > > index face664be3e8..481896fb712a 100644
> > > --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> > > +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> > > @@ -220,8 +220,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
> > > if (IS_SKYLAKE(dev_priv)
> > > || IS_KABYLAKE(dev_priv)
> > > || IS_BROXTON(dev_priv)) {
> > > - plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
> > > - _PLANE_CTL_TILED_SHIFT;
> > > + plane->tiled = val & PLANE_CTL_TILED_MASK;
> > > fmt = skl_format_to_drm(
> > > val & PLANE_CTL_FORMAT_MASK,
> > > val & PLANE_CTL_ORDER_RGBX,
> > > @@ -260,7 +259,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
> > > return -EINVAL;
> > > }
> > > - plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
> > > + plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
> > > (IS_SKYLAKE(dev_priv)
> > > || IS_KABYLAKE(dev_priv)
> > > || IS_BROXTON(dev_priv)) ?
> > > diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h
> > > index cb055f3c81a2..54e92321c538 100644
> > > --- a/drivers/gpu/drm/i915/gvt/fb_decoder.h
> > > +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h
> > > @@ -101,7 +101,7 @@ struct intel_gvt;
> > > /* color space conversion and gamma correction are not included */
> > > struct intel_vgpu_primary_plane_format {
> > > u8 enabled; /* plane is enabled */
> > > - u8 tiled; /* X-tiled */
> > > + u32 tiled; /* X-tiled */
>
> Seems like inaccurate comments inherited from origianl version. Tiling mode could be other than x-tiled.
Will fix the comment.
> And there is also "tiled" filed in intel_vgpu_sprite_plane_format(), can define to u32 as well since it should
> align with drm_format_mod as well, if we add support later.
hmm, current dmabuf has no support for sprite, and looks current fb decoder
part for that is really fragile. So I think this should be seperate one when
we have real sprite plane support.
Thanks for the comment!
>
> > > u8 bpp; /* bits per pixel */
> > > u32 hw_format; /* format field in the PRI_CTL register */
> > > u32 drm_format; /* format in DRM definition */
> > > --
> > > 2.18.0
> > >
> > > _______________________________________________
> > > intel-gvt-dev mailing list
> > > intel-gvt-dev at lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
> >
> > _______________________________________________
> > intel-gvt-dev mailing list
> > intel-gvt-dev at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
>
> --
> Best Regards,
> Colin Xu
>
--
Open Source Technology Center, Intel ltd.
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