[PATCH v3 1/3] drm/i915/gvt: add define GEN9_MOCS_SIZE
Tian, Kevin
kevin.tian at intel.com
Mon Feb 12 07:48:39 UTC 2018
> From: Weinan Li
> Sent: Monday, February 12, 2018 3:08 PM
>
> No functional change. This define will also be used in future patches.
define -> definition
>
> Signed-off-by: Weinan Li <weinan.z.li at intel.com>
> ---
> drivers/gpu/drm/i915/gvt/mmio_context.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c
> b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 256f1bb5..99bc148 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -50,6 +50,8 @@
> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
> #define VF_GUARDBAND _MMIO(0x83a4)
>
> +#define GEN9_MOCS_SIZE 64
> +
> /* Raw offset is appened to each line for convenience. */
> static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned =
> {
> {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
> @@ -152,8 +154,8 @@
>
> static struct {
> bool initialized;
> - u32 control_table[I915_NUM_ENGINES][64];
> - u32 l3cc_table[32];
> + u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
> + u32 l3cc_table[GEN9_MOCS_SIZE / 2];
> } gen9_render_mocs;
>
> static void load_render_mocs(struct drm_i915_private *dev_priv)
> @@ -170,7 +172,7 @@ static void load_render_mocs(struct
> drm_i915_private *dev_priv)
>
> for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
> offset.reg = regs[ring_id];
> - for (i = 0; i < 64; i++) {
> + for (i = 0; i < GEN9_MOCS_SIZE; i++) {
> gen9_render_mocs.control_table[ring_id][i] =
> I915_READ_FW(offset);
> offset.reg += 4;
> @@ -178,7 +180,7 @@ static void load_render_mocs(struct
> drm_i915_private *dev_priv)
> }
>
> offset.reg = 0xb020;
> - for (i = 0; i < 32; i++) {
> + for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
> gen9_render_mocs.l3cc_table[i] =
> I915_READ_FW(offset);
> offset.reg += 4;
> @@ -256,7 +258,7 @@ static void switch_mocs(struct intel_vgpu *pre,
> struct intel_vgpu *next,
> load_render_mocs(dev_priv);
>
> offset.reg = regs[ring_id];
> - for (i = 0; i < 64; i++) {
> + for (i = 0; i < GEN9_MOCS_SIZE; i++) {
> if (pre)
> old_v = vgpu_vreg_t(pre, offset);
> else
> @@ -274,7 +276,7 @@ static void switch_mocs(struct intel_vgpu *pre,
> struct intel_vgpu *next,
>
> if (ring_id == RCS) {
> l3_offset.reg = 0xb020;
> - for (i = 0; i < 32; i++) {
> + for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
> if (pre)
> old_v = vgpu_vreg_t(pre, l3_offset);
> else
> --
> 1.9.1
>
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