[PATCH v2] drm/i915/gvt: add 0xe4f0 into gen9 render list

[Zhenyu Wang]

On 2018.02.09 16:01:34 +0800, Weinan Li wrote:
> Guest may set this register on KBL platform, it can impact hardware
> behavior, so add it into the gen9 render list. Otherwise gpu hang issue may
> happen during different vgpu switch.
> 
> v2: separate it from patch set.
> 
> Cc: Zhi Wang <zhi.a.wang at intel.com>
> Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> Signed-off-by: Weinan Li <weinan.z.li at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 1c42ece..62a43b0 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -120,6 +120,7 @@
>  	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
>  	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
>  	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
> +	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
>  	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
>  	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
>  	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
> -- 

Pushed, thanks!

-- 
Open Source Technology Center, Intel ltd.

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