[PATCH v3] drm/i915/gvt: Support BAR0 8-byte reads/writes

[Zhenyu Wang]

On 2018.02.11 14:59:19 +0800, Tina Zhang wrote:
> GGTT is in BAR0 with 8 bytes aligned. With a qemu patch (commit:
> 38d49e8c1523d97d2191190d3f7b4ce7a0ab5aa3), VFIO can use 8-byte reads/
> writes to access it.
> 
> This patch is to support the 8-byte GGTT reads/writes.
> 
> Ideally, we would like to support 8-byte reads/writes for the total BAR0.
> But it needs more work for handling 8-byte MMIO reads/writes.
> 
> This patch can fix the issue caused by partial updating GGTT entry, during
> guest booting up.
> 
> v3:
> - Use intel_vgpu_get_bar_gpa() stead. (Zhenyu)
> - Include all the GGTT checking logic in gtt_entry(). (Zhenyu)
> 
> v2:
> - Limit to GGTT entry. (Zhenyu)
> 
> Signed-off-by: Tina Zhang <tina.zhang at intel.com>
> ---

Pushed, thanks!

-- 
Open Source Technology Center, Intel ltd.

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