[PATCH] drm/i915/gvt: Add mmio handler for RING_MI_MODE

[Zhenyu Wang]

On 2018.01.19 13:31:21 +0800, fred gao wrote:
> With the introduction of new logic for stoping engines before
> reset, the RING_MI_MODE should be handled accordingly.
> 
> Signed-off-by: fred gao <fred.gao at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 38f3b00..90a1e1a 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1585,6 +1585,23 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
>  	return 0;
>  }
>  
> +static int ring_mi_mode_write(struct intel_vgpu *vgpu,
> +	unsigned int offset, void *p_data, unsigned int bytes)
> +{
> +	u32 data;
> +
> +	write_vreg(vgpu, offset, p_data, bytes);
> +	data = vgpu_vreg(vgpu, offset);
> +
> +	if (data & _MASKED_BIT_ENABLE(STOP_RING)) {
> +		data |= MODE_IDLE;
> +		data &= ~STOP_RING;
> +	}

We can't assume target ring is always idle right? Looks need some help
from submission to check ring state before turn to idle state.

> +
> +	vgpu_vreg(vgpu, offset) = data;
> +	return 0;
> +}
> +
>  #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>  	ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>  		f, s, am, rm, d, r, w); \
> @@ -1685,7 +1702,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  #undef RING_REG
>  
>  	MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> -		NULL, NULL);
> +		NULL, ring_mi_mode_write);
>  	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>  			NULL, NULL);
>  	MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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