[bug report] drm/i915/gvt: vGPU HW resource management

[Dan Carpenter]

Hello Zhi Wang,

The patch 28a60dee2ce6: "drm/i915/gvt: vGPU HW resource management"
from Sep 2, 2016, leads to the following static checker warning:

	drivers/gpu/drm/i915/gvt/aperture_gm.c:137 intel_vgpu_write_fence()
	warn: array off by one? 'vgpu->fence.regs[fence]'

drivers/gpu/drm/i915/gvt/aperture_gm.c
   124  void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
   125                  u32 fence, u64 value)
   126  {
   127          struct intel_gvt *gvt = vgpu->gvt;
   128          struct drm_i915_private *dev_priv = gvt->dev_priv;
   129          struct drm_i915_fence_reg *reg;
   130          i915_reg_t fence_reg_lo, fence_reg_hi;
   131  
   132          assert_rpm_wakelock_held(dev_priv);
   133  
   134          if (WARN_ON(fence > vgpu_fence_sz(vgpu)))
                            ^^^^^^^^^^^^^^^^^^^^^^^^^^^
I think this should be >= but the code was slightly hard for me to
follow so I'm not positive.

   135                  return;
   136  
   137          reg = vgpu->fence.regs[fence];
   138          if (WARN_ON(!reg))
   139                  return;
   140  
   141          fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
   142          fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
   143  
   144          I915_WRITE(fence_reg_lo, 0);
   145          POSTING_READ(fence_reg_lo);
   146  
   147          I915_WRITE(fence_reg_hi, upper_32_bits(value));
   148          I915_WRITE(fence_reg_lo, lower_32_bits(value));
   149          POSTING_READ(fence_reg_lo);
   150  }

regards,
dan carpenter