[PATCH 07/10] drm/i915/gvt: Enable cmd_parser support for BXT.

[Zhenyu Wang]

On 2018.06.01 10:12:36 +0800, Colin Xu wrote:
> Handle BXT cmd_parser as SKL/KBL.
> 
> Signed-off-by: Colin Xu <colin.xu at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 24 +++++++++++++++++-------
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index f65cf4515783..3c185193f1e7 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -1257,7 +1257,9 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s,
>  	if (!info->async_flip)
>  		return 0;
>  
> -	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> +	if (IS_SKYLAKE(dev_priv)
> +		|| IS_KABYLAKE(dev_priv)
> +		|| IS_BROXTON(dev_priv)) {
>  		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
>  		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
>  				GENMASK(12, 10)) >> 10;
> @@ -1285,7 +1287,9 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
>  
>  	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
>  		      info->surf_val << 12);
> -	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> +	if (IS_SKYLAKE(dev_priv)
> +		|| IS_KABYLAKE(dev_priv)
> +		|| IS_BROXTON(dev_priv)) {
>  		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
>  			      info->stride_val);
>  		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
> @@ -1309,7 +1313,9 @@ static int decode_mi_display_flip(struct parser_exec_state *s,
>  
>  	if (IS_BROADWELL(dev_priv))
>  		return gen8_decode_mi_display_flip(s, info);
> -	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> +	if (IS_SKYLAKE(dev_priv)
> +		|| IS_KABYLAKE(dev_priv)
> +		|| IS_BROXTON(dev_priv))
>  		return skl_decode_mi_display_flip(s, info);
>  
>  	return -ENODEV;
> @@ -1322,7 +1328,8 @@ static int check_mi_display_flip(struct parser_exec_state *s,
>  
>  	if (IS_BROADWELL(dev_priv)
>  		|| IS_SKYLAKE(dev_priv)
> -		|| IS_KABYLAKE(dev_priv))
> +		|| IS_KABYLAKE(dev_priv)
> +		|| IS_BROXTON(dev_priv))
>  		return gen8_check_mi_display_flip(s, info);
>  	return -ENODEV;

If all our supported chips need that, why still keep that check?

>  }
> @@ -1335,7 +1342,8 @@ static int update_plane_mmio_from_mi_display_flip(
>  
>  	if (IS_BROADWELL(dev_priv)
>  		|| IS_SKYLAKE(dev_priv)
> -		|| IS_KABYLAKE(dev_priv))
> +		|| IS_KABYLAKE(dev_priv)
> +		|| IS_BROXTON(dev_priv))
>  		return gen8_update_plane_mmio_from_mi_display_flip(s, info);

ditto

>  	return -ENODEV;
>  }
> @@ -1618,8 +1626,10 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s)
>  {
>  	struct intel_gvt *gvt = s->vgpu->gvt;
>  
> -	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
> -		|| IS_KABYLAKE(gvt->dev_priv)) {
> +	if (IS_BROADWELL(gvt->dev_priv)
> +		|| IS_SKYLAKE(gvt->dev_priv)
> +		|| IS_KABYLAKE(gvt->dev_priv)
> +		|| IS_BROXTON(gvt->dev_priv)) {

ditto

>  		/* BDW decides privilege based on address space */
>  		if (cmd_val(s, 0) & (1 << 8) &&
>  			!(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
> -- 
> 2.17.1
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

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