[PATCH v2] drm/i915/gvt: Correct the previlege shadow batch buffer address

[Zhenyu Wang]

Pls fix typo in title.

On 2018.03.12 15:21:14 +0800, fred gao wrote:
> Once the ring buffer is copied to ring_scan_buffer and scanned,
> the shadow batch buffer start address is only updated into
> ring_scan_buffer, not the real ring address allocated through
> intel_ring_begin in later copy_workload_to_ring_buffer.
> 
> This patch is only to set the right shadow batch buffer address
> from Ring buffer, not include the shadow_wa_ctx.
> 
> v2:
> - refine some comments. (Zhenyu)
> 
> Fixes: 0a53bc07f044 ("drm/i915/gvt: Separate cmd scan from request allocation")
> Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> Cc: Yulei Zhang <yulei.zhang at intel.com>
> Signed-off-by: fred gao <fred.gao at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 +++++++++
>  drivers/gpu/drm/i915/gvt/scheduler.c  | 4 ++++
>  drivers/gpu/drm/i915/gvt/scheduler.h  | 1 +
>  3 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index c8454ac..d32edde 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -471,6 +471,8 @@ struct parser_exec_state {
>  	 * used when ret from 2nd level batch buffer
>  	 */
>  	int saved_buf_addr_type;
> +	/* identify the workload source */
> +	bool is_ctx_wa;

This comment might not be necessary as the variable name is already good to tell.

>  
>  	struct cmd_info *info;
>  
> @@ -1715,6 +1717,11 @@ static int perform_bb_shadow(struct parser_exec_state *s)
>  	bb->accessing = true;
>  	bb->bb_start_cmd_va = s->ip_va;
>  
> +	if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
> +		bb->bb_offset = s->ip_va - s->rb_va;
> +	else
> +		bb->bb_offset = 0;
> +
>  	/*
>  	 * ip_va saves the virtual address of the shadow batch buffer, while
>  	 * ip_gma saves the graphics address of the original batch buffer.
> @@ -2571,6 +2578,7 @@ static int scan_workload(struct intel_vgpu_workload *workload)
>  	s.ring_tail = gma_tail;
>  	s.rb_va = workload->shadow_ring_buffer_va;
>  	s.workload = workload;
> +	s.is_ctx_wa = false;
>  
>  	if ((bypass_scan_mask & (1 << workload->ring_id)) ||
>  		gma_head == gma_tail)
> @@ -2624,6 +2632,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
>  	s.ring_tail = gma_tail;
>  	s.rb_va = wa_ctx->indirect_ctx.shadow_va;
>  	s.workload = workload;
> +	s.is_ctx_wa = true;
>  
>  	if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
>  		ret = -EINVAL;
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index 6a1f7ed..bf480f9 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -431,6 +431,10 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
>  			goto err;
>  		}
>  
> +		if (bb->bb_offset)
> +			bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
> +				+ bb->bb_offset;

Better adding a comment here to say that this is actually real ctx
ring buffer instead of shadow ring which I was confused. And better we
can have some cleanup later.

> +
>  		/* relocate shadow batch buffer */
>  		bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
>  		if (gmadr_bytes == 8)
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
> index 2cfc639..486ed57 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.h
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.h
> @@ -124,6 +124,7 @@ struct intel_vgpu_shadow_bb {
>  	u32 *bb_start_cmd_va;
>  	unsigned int clflush;
>  	bool accessing;
> +	unsigned long bb_offset;
>  };
>  
>  #define workload_q_head(vgpu, ring_id) \
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

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