[PATCH v4 04/14] drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE

[Zhenyu Wang]

On 2018.05.04 17:50:30 +0800, changbin.du at intel.com wrote:
>
> @@ -934,6 +944,20 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
>  	return ret;
>  }
>  
> +static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
> +{
> +	if (INTEL_GEN(vgpu->gvt->dev_priv) == 9) {
> +		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
> +			GAMW_ECO_ENABLE_64K_IPS_FIELD;
> +
> +		return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;

Should 64K will always be required to enable for all engines or we
should only check if any engine has 64K ppgtt enabled?


> +	} else if (INTEL_GEN(vgpu->gvt->dev_priv) >= 10) {
> +		/* 64K paging only controlled by IPS bit in PTE now. */
> +		return true;
> +	} else
> +		return false;
> +}
> +
>  static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
>  
>  static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(

-- 
Open Source Technology Center, Intel ltd.

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