[PATCH v2 3/4] drm/i915/gvt: do not return error on handling force_to_nonpriv registers

[Zhao Yan]

Return error will cause vm hang and enter failsafe mode.
However, we don't want that happen on detecting an wrong force_to_nonpriv
register write.
Therefore, we just omit the wrong write or patch it to default value.

Signed-off-by: Zhao Yan <yan.y.zhao at intel.com>
Reviewed-by: Zhang Yulei <yulei.zhang at intel.com>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c | 3 ++-
 drivers/gpu/drm/i915/gvt/handlers.c   | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 4f36e2f..907b4f8 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -831,6 +831,7 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 			data != nopid) {
 		gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 			offset, data);
+		patch_value(s, cmd_ptr(s, index), nopid);
 		return -EPERM;
 	}
 	return 0;
@@ -880,7 +881,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
 
 	if (is_force_nonpriv_mmio(s, offset) &&
 		force_nonpriv_reg_handler(s, offset, index))
-		return -EPERM;
+		return 0;
 
 	if (offset == i915_mmio_reg_offset(DERRMR) ||
 		offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 08f96f9..2c14fd6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -498,7 +498,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
 		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
 			vgpu->id, reg_nonpriv, offset);
 
-	return ret;
+	return 0;
 }
 
 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
-- 
1.9.1