[Intel-gfx] [PATCH v6 04/14] drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE

[Zhenyu Wang]

On 2018.05.10 16:17:35 +0100, Matthew Auld wrote:
> > @@ -934,6 +944,20 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
> >         return ret;
> >  }
> >
> > +static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
> > +{
> > +       if (INTEL_GEN(vgpu->gvt->dev_priv) == 9) {
> > +               u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
> > +                       GAMW_ECO_ENABLE_64K_IPS_FIELD;
> > +
> > +               return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
> > +       } else if (INTEL_GEN(vgpu->gvt->dev_priv) >= 10) {
> > +               /* 64K paging only controlled by IPS bit in PTE now. */
> > +               return true;
> 
> AFAIK the funny business with having to enable the IPS bit through
> mmio is also needed on GEN10.

yeah, looks it only won't be needed from Gen11.

Thanks for review! Will update that.

-- 
Open Source Technology Center, Intel ltd.

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