[Intel-gfx] [PATCH v6 10/14] drm/i915/kvmgt: Support setting dma map for huge pages

[Du, Changbin]

Hi Auld,
Thanks for your review.

On Thu, May 10, 2018 at 03:31:03PM +0100, Matthew Auld wrote:
> On 8 May 2018 at 10:05,  <changbin.du at intel.com> wrote:
> > From: Changbin Du <changbin.du at intel.com>

> > +static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn,
> > +               dma_addr_t *dma_addr, unsigned long size)
> > +{
> > +       struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
> > +       struct page *page = NULL;
> > +       int ret;
> > +
> > +       ret = gvt_pin_guest_page(vgpu, gfn, size, &page);
> > +       if (ret)
> > +               return ret;
> > +
> >         /* Setup DMA mapping. */
> > -       page = pfn_to_page(pfn);
> > -       *dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE,
> > -                                PCI_DMA_BIDIRECTIONAL);
> > -       if (dma_mapping_error(dev, *dma_addr)) {
> > -               gvt_vgpu_err("DMA mapping failed for gfn 0x%lx\n", gfn);
> > -               vfio_unpin_pages(mdev_dev(vgpu->vdev.mdev), &gfn, 1);
> > -               return -ENOMEM;
> > +       *dma_addr = dma_map_page(dev, page, 0, size, PCI_DMA_BIDIRECTIONAL);
> 
> Do we not need to check if the dma addr we get back is not aligned to
> the requested page-size, where we would then fall back to splitting
> the 2M shadow entry?
AFAIK, our IOMMU driver always allocates size aligned base IOVA. So the dma addr must
align to the requested page-size. Thanks!

-- 
Thanks,
Changbin Du