[PATCH] drm/i915/gvt: Fix shadow ctx ppgtt destroy function
Zhenyu Wang
zhenyuw at linux.intel.com
Thu Nov 29 02:09:41 UTC 2018
On 2018.11.29 09:50:19 +0800, Xiong Zhang wrote:
> Recently gvt shadow ctx create ppgtt table and this ppgtt's root
> pointer is modified at workload dispatch, then we lose the original
> ppgtt's root pointer, this causes the ppgtt destroy function abnormal
> as it will release the wrong root table.
>
> This patch save i915 context ppgtt root pointer at shadow
> ctx creation and restore it at shadow ctx destruction.
>
> Fixes:4f15665ccbba("drm/i915: Add ppgtt to GVT GEM context")
>
Good catch! But could we split it into save and restore function?
I really like to follow one function to do one thing style.
> Signed-off-by: Xiong Zhang <xiong.y.zhang at intel.com>
> ---
> drivers/gpu/drm/i915/gvt/gvt.h | 4 ++++
> drivers/gpu/drm/i915/gvt/scheduler.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> index 4970325..7948cc7 100644
> --- a/drivers/gpu/drm/i915/gvt/gvt.h
> +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> @@ -160,6 +160,10 @@ struct intel_vgpu_submission {
> struct kmem_cache *workloads;
> atomic_t running_workload_num;
> struct i915_gem_context *shadow_ctx;
> + union {
> + u64 i915_context_pml4;
> + u64 i915_context_pdps[GEN8_3LVL_PDPES];
> + };
> DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
> DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
> void *ring_scan_buffer[I915_NUM_ENGINES];
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index b8fbe3fa..c108533 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1079,6 +1079,30 @@ int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
> return ret;
> }
>
> +static void
> +i915_context_ppgtt_root_save_restore(struct intel_vgpu_submission *s,
> + bool restore)
> +{
> + struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
> + int i;
> +
> + if (i915_vm_is_48bit(&i915_ppgtt->vm)) {
> + if (restore)
> + px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
> + else
> + s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
> + } else {
> + for (i = 0; i < GEN8_3LVL_PDPES; i++) {
> + if (restore)
> + px_dma(i915_ppgtt->pdp.page_directory[i]) =
> + s->i915_context_pdps[i];
> + else
> + s->i915_context_pdps[i] =
> + px_dma(i915_ppgtt->pdp.page_directory[i]);
> + }
> + }
> +}
> +
> /**
> * intel_vgpu_clean_submission - free submission-related resource for vGPU
> * @vgpu: a vGPU
> @@ -1091,6 +1115,7 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
> struct intel_vgpu_submission *s = &vgpu->submission;
>
> intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
> + i915_context_ppgtt_root_save_restore(s, true);
> i915_gem_context_put(s->shadow_ctx);
> kmem_cache_destroy(s->workloads);
> }
> @@ -1138,6 +1163,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
> if (IS_ERR(s->shadow_ctx))
> return PTR_ERR(s->shadow_ctx);
>
> + i915_context_ppgtt_root_save_restore(s, false);
> +
> bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
>
> s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
> --
> 2.7.4
>
--
Open Source Technology Center, Intel ltd.
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