[PATCH] drm/i915/gvt: addressed guest GPU hang with HWS index mode

[Zhang, Xiaolin]

On 04/03/2019 11:59 AM, Zhenyu Wang wrote:
> On 2019.04.03 11:31:17 +0800, Xiaolin Zhang wrote:
>> with the introduce of "switch to use HWS indices rather than address",
>> guest GPU hang observed when running workloads which will update the
>> seqno to the real HW HWSP, not vitural GPU HWSP and then cause GPU hang.
>>
>> this patch is to revoke index mode in PIPE_CTRL and MI_FLUSH_DW and
>> patch guest GPU HWSP address value to these commands.
>>
>> Fixes: 54939ea0b("drm/i915: Switch to use HWS indices rather than
>> addresses")
>>
>> Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
>> ---
>>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 25 ++++++++++++++++++++++---
>>  1 file changed, 22 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
>> index b420919279c7..f976777d7bd5 100644
>> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
>> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
>> @@ -1070,6 +1070,18 @@ static struct cmd_interrupt_event cmd_interrupt_events[] = {
>>  	},
>>  };
>>  
>> +static int index_mode_to_gma(struct parser_exec_state *s, u32 index)
>> +{
>> +	u32 gma;
>> +	u32 val;
>> +
>> +	gma = s->vgpu->hws_pga[s->ring_id] + index;
>> +	patch_value(s, cmd_ptr(s, 2), gma);
>> +	val = cmd_val(s, 1) & (~PIPE_CONTROL_STORE_DATA_INDEX);
>> +	patch_value(s, cmd_ptr(s, 1), val);
> MI_FLUSH_DW uses dword 1 for GMA address or index instead of dword 2, although
> index mode flag for them is both at dword 1, but address offset is different,
> and MI_FLUSH_DW has GGTT/PPGTT flag value in dword 1 which should be preserved.
> Looks better just handle in their handlers.
thanks your great point. I missed this detail information in my patch.
will be corrected in patch V2.
>
>> +	return 0;
>> +}
>> +
>>  static int cmd_handler_pipe_control(struct parser_exec_state *s)
>>  {
>>  	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
>> @@ -1098,8 +1110,11 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s)
>>  				/* Store Data Index */
>>  				if (cmd_val(s, 1) & (1 << 21))
>>  					index_mode = true;
>> -				ret |= cmd_address_audit(s, gma, sizeof(u64),
>> -						index_mode);
>> +				if (index_mode)
>> +					ret = index_mode_to_gma(s, gma);
>> +				else
>> +					ret |= cmd_address_audit(s, gma,
>> +						sizeof(u64), index_mode);
>>  			}
>>  		}
>>  	}
>> @@ -1607,7 +1622,11 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
>>  		/* Store Data Index */
>>  		if (cmd_val(s, 0) & (1 << 21))
>>  			index_mode = true;
>> -		ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
>> +		if (index_mode)
>> +			ret = index_mode_to_gma(s, gma);
>> +		else
>> +			ret = cmd_address_audit(s, gma,
>> +					sizeof(u64), index_mode);
>>  	}
>>  	/* Check notify bit */
>>  	if ((cmd_val(s, 0) & (1 << 8)))
>> -- 
>> 2.15.1
>>