[PATCH V2] drm/i915/gvt: addressed guest GPU hang with HWS index mode

[Yuan, Hang]

> -----Original Message-----
> From: intel-gvt-dev [mailto:intel-gvt-dev-bounces at lists.freedesktop.org] On
> Behalf Of Xiaolin Zhang
> Sent: Wednesday, April 3, 2019 1:01 PM
> To: intel-gvt-dev at lists.freedesktop.org
> Cc: Zhang, Xiaolin <xiaolin.zhang at intel.com>; zhenyuw at linux.intel.com
> Subject: [PATCH V2] drm/i915/gvt: addressed guest GPU hang with HWS
> index mode
> 
> with the introduce of "switch to use HWS indices rather than address", guest
> GPU hang observed when running workloads which will update the seqno to
> the real HW HWSP, not vitural GPU HWSP and then cause GPU hang.
> 
> this patch is to revoke index mode in PIPE_CTRL and MI_FLUSH_DW and
> patch guest GPU HWSP address value to these commands.
> 
> Fixes: 54939ea0b("drm/i915: Switch to use HWS indices rather than
> addresses")
> 
> v2: PIPE_CTRL and MI_FLUSH_DW has different address offset, offset is also
> passed for gma address update. <zhenyu>
> 
> Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 25 ++++++++++++++++++++++---
>  1 file changed, 22 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index b420919279c7..2716fd349ecc 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -1070,6 +1070,18 @@ static struct cmd_interrupt_event
> cmd_interrupt_events[] = {
>  	},
>  };
> 
> +static int index_mode_to_gma(struct parser_exec_state *s, u32 offset,
> +u32 index) {
> +	u32 gma;
> +	u32 val;
> +
> +	gma = s->vgpu->hws_pga[s->ring_id] + index;
[Yuan, Hang] the destination address may be in GGTT, does global hardware status page need to be considered here?

> +	patch_value(s, cmd_ptr(s, offset), gma);
> +	val = cmd_val(s, offset - 1) & (~PIPE_CONTROL_STORE_DATA_INDEX);
> +	patch_value(s, cmd_ptr(s, offset - 1), val);
> +	return 0;
> +}
> +
>  static int cmd_handler_pipe_control(struct parser_exec_state *s)  {
>  	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
> @@ -1098,8 +1110,11 @@ static int cmd_handler_pipe_control(struct
> parser_exec_state *s)
>  				/* Store Data Index */
>  				if (cmd_val(s, 1) & (1 << 21))
>  					index_mode = true;
> -				ret |= cmd_address_audit(s, gma, sizeof(u64),
> -						index_mode);
> +				if (index_mode)
> +					ret = index_mode_to_gma(s, 2, gma);
> +				else
> +					ret |= cmd_address_audit(s, gma,
> +						sizeof(u64), index_mode);
>  			}
>  		}
>  	}
> @@ -1607,7 +1622,11 @@ static int cmd_handler_mi_flush_dw(struct
> parser_exec_state *s)
>  		/* Store Data Index */
>  		if (cmd_val(s, 0) & (1 << 21))
>  			index_mode = true;
> -		ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
> +		if (index_mode)
> +			ret = index_mode_to_gma(s, 1, gma);
> +		else
> +			ret = cmd_address_audit(s, gma,
> +					sizeof(u64), index_mode);
>  	}
>  	/* Check notify bit */
>  	if ((cmd_val(s, 0) & (1 << 8)))
> --
> 2.15.1