[PATCH v5] drm/i915/gvt: addressed guest GPU hang with HWS index mode
Zhenyu Wang
zhenyuw at linux.intel.com
Wed Apr 3 08:14:39 UTC 2019
On 2019.04.03 16:07:28 +0800, Xiaolin Zhang wrote:
> with the introduce of "switch to use HWS indices rather than address",
> guest GPU hang observed when running workloads which will update the
> seqno to the real HW HWSP, not vitural GPU HWSP and then cause GPU hang.
>
> this patch is to revoke index mode in PIPE_CTRL and MI_FLUSH_DW and
> patch guest GPU HWSP address value to these commands.
>
> Fixes: 54939ea0b("drm/i915: Switch to use HWS indices rather than
> addresses")
>
> v5: refine code logic to handle index_mode.
> v4: call cmd_address_audit for new address converted from index.
> v3: handle index mode to gma conversion within cmd handler itself.
> v2: PIPE_CTRL and MI_FLUSH_DW has different address offset, offset is
> also passed for gma address update. <zhenyu>
>
> Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
> ---
Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index b420919279c7..083ba64c8f5d 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -1077,6 +1077,8 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s)
> bool index_mode = false;
> unsigned int post_sync;
> int ret = 0;
> + u32 hws_gpa;
> + u32 val;
>
> post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
>
> @@ -1100,6 +1102,15 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s)
> index_mode = true;
> ret |= cmd_address_audit(s, gma, sizeof(u64),
> index_mode);
> + if (ret)
> + return ret;
> + if (index_mode) {
> + hws_gpa = s->vgpu->hws_pga[s->ring_id];
> + gma = hws_gpa + gma;
> + patch_value(s, cmd_ptr(s, 2), gma);
> + val = cmd_val(s, 1) & (~(1 << 21));
> + patch_value(s, cmd_ptr(s, 1), val);
> + }
> }
> }
> }
> @@ -1598,6 +1609,8 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
> unsigned long gma;
> bool index_mode = false;
> int ret = 0;
> + u32 hws_gpa;
> + u32 val;
>
> /* Check post-sync and ppgtt bit */
> if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
> @@ -1608,6 +1621,15 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
> if (cmd_val(s, 0) & (1 << 21))
> index_mode = true;
> ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
> + if (ret)
> + return ret;
> + if (index_mode) {
> + hws_gpa = s->vgpu->hws_pga[s->ring_id];
> + gma = hws_gpa + gma;
> + patch_value(s, cmd_ptr(s, 1), gma);
> + val = cmd_val(s, 0) & (~(1 << 21));
> + patch_value(s, cmd_ptr(s, 0), val);
> + }
> }
> /* Check notify bit */
> if ((cmd_val(s, 0) & (1 << 8)))
> --
> 2.15.1
>
--
Open Source Technology Center, Intel ltd.
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