[PATCH] drm/i915/gvt: Revert "drm/i915/gvt: Refine the snapshort range of I915 MCHBAR to optimize gvt-g boot time"

[Zhenyu Wang]

On 2019.04.25 17:04:54 +0800, Zhao Yakui wrote:
> This reverts commit f74a6d9a2c427b6656bc93eacfa6d329ba54d611.
> 
> BXT needs to access 0x141000-0x1417ff register to obtain the dram info.
> But after the snapshot range of I915_MCHBAR is refined in f74a6d9a2c,
> it only initializes the range of 0x144000-0x147fff for VGPU and then
> causes that the guest GPU can't get the initialized value for dram
> detection on BXT.
> 
> Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
> ---

Acked-by: Zhenyu Wang <zhenyuw at linux.intel.com>

>  drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
>  drivers/gpu/drm/i915/gvt/reg.h      | 3 ---
>  2 files changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 34129ea..90673fc 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -3303,7 +3303,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
>  /* Special MMIO blocks. */
>  static struct gvt_mmio_block mmio_blocks[] = {
>  	{D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
> -	{D_ALL, MCHBAR_MIRROR_REG_BASE, 0x4000, NULL, NULL},
> +	{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
>  	{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
>  		pvinfo_mmio_read, pvinfo_mmio_write},
>  	{D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index 3de5b64..33aaa14 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -126,7 +126,4 @@
>  #define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
>  #define VF_GUARDBAND		_MMIO(0x83a4)
>  
> -/* define the effective range of MCHBAR register on Sandybridge+ */
> -#define MCHBAR_MIRROR_REG_BASE	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
> -
>  #endif
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
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