[PATCH v2] drm/i915/gvt: Add in context mmio 0x20D8 to gen9 mmio list

[Zhenyu Wang]

On 2019.02.22 14:13:42 +0800, Colin Xu wrote:
> Depends on GEN family and I915_PARAM_HAS_CONTEXT_ISOLATION, Mesa driver
> will decide whether constant buffer 0 address is relative or absolute,
> and load GPU initial state by lri to context mmio INSTPM (GEN8)
> or 0x20D8 (>=GEN9).
> Mesa Commit fa8a764b62
> ("i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.")
> 
> INSTPM is already added to gen8_engine_mmio_list, but 0x20D8 is missed
> in gen9_engine_mmio_list. From GVT point of view, different guest could
> have different context so should switch those mmio accordingly.
> 
> Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
> 
> v2: Update fixes commit ID.
> 
> Signed-off-by: Colin Xu <colin.xu at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 7d84cfb9051a..7902fb162d09 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -132,6 +132,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
>  
>  	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
>  	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
> +	{RCS, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
>  
>  	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
>  	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
> -- 

Fine for me.

Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>

-- 
Open Source Technology Center, Intel ltd.

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