[intel-gvt-linux:topic/gvt-xengt 21/41] drivers/gpu/drm/i915/i915_reg.h:185:46: warning: initialization makes integer from pointer without a cast

kbuild test robot lkp at intel.com
Mon Jul 22 13:11:03 UTC 2019


tree:   https://github.com/intel/gvt-linux topic/gvt-xengt
head:   91f813747858ede8f67aa95236a5bf5822c3873d
commit: e9c16f9e76a7e14a393694bc50435926fd4012d7 [21/41] drm/i915/gvt: Implement vGPU status save and restore through new VFIO subregion VFIO_REGION_SUBTYPE_DEVICE_STATE
config: x86_64-rhel-7.6 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-10) 7.4.0
reproduce:
        git checkout e9c16f9e76a7e14a393694bc50435926fd4012d7
        # save the attached .config to linux build tree
        make ARCH=x86_64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp at intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/gvt/migrate.c: In function 'sreg_save':
   drivers/gpu/drm/i915/gvt/migrate.c:291:25: error: 'struct intel_vgpu_mmio' has no member named 'sreg'; did you mean 'vreg'?
     void *src = vgpu->mmio.sreg;
                            ^~~~
                            vreg
   drivers/gpu/drm/i915/gvt/migrate.c: In function 'sreg_load':
   drivers/gpu/drm/i915/gvt/migrate.c:306:26: error: 'struct intel_vgpu_mmio' has no member named 'sreg'; did you mean 'vreg'?
     void *dest = vgpu->mmio.sreg;
                             ^~~~
                             vreg
   In file included from drivers/gpu/drm/i915/i915_drv.h:63:0,
                    from drivers/gpu/drm/i915/gvt/migrate.c:28:
   drivers/gpu/drm/i915/gvt/migrate.c: In function 'workload_load':
>> drivers/gpu/drm/i915/i915_reg.h:185:46: warning: initialization makes integer from pointer without a cast [-Wint-conversion]
    #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
                                                 ^
   drivers/gpu/drm/i915/gt/intel_lrc.h:38:28: note: in expansion of macro '_MMIO'
    #define RING_ELSP(base)    _MMIO((base) + 0x230)
                               ^~~~~
   drivers/gpu/drm/i915/gvt/migrate.c:490:30: note: in expansion of macro 'RING_ELSP'
      off = i915_mmio_reg_offset(RING_ELSP(engine));
                                 ^~~~~~~~~
   drivers/gpu/drm/i915/i915_reg.h:185:46: note: (near initialization for '(anonymous).reg')
    #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
                                                 ^
   drivers/gpu/drm/i915/gt/intel_lrc.h:38:28: note: in expansion of macro '_MMIO'
    #define RING_ELSP(base)    _MMIO((base) + 0x230)
                               ^~~~~
   drivers/gpu/drm/i915/gvt/migrate.c:490:30: note: in expansion of macro 'RING_ELSP'
      off = i915_mmio_reg_offset(RING_ELSP(engine));
                                 ^~~~~~~~~

vim +185 drivers/gpu/drm/i915/i915_reg.h

f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    184  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   @185  #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    186  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    187  #define INVALID_MMIO_REG _MMIO(0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    188  
739f3abdbfcf8c9 Jani Nikula                   2019-01-16    189  static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    190  {
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    191  	return reg.reg;
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    192  }
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    193  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    194  static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    195  {
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    196  	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    197  }
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    198  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    199  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    200  {
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    201  	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    202  }
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    203  
ed5eb1b78a88302 Jani Nikula                   2018-12-31    204  #define VLV_DISPLAY_BASE		0x180000
ed5eb1b78a88302 Jani Nikula                   2018-12-31    205  #define VLV_MIPI_BASE			VLV_DISPLAY_BASE
ed5eb1b78a88302 Jani Nikula                   2018-12-31    206  #define BXT_MIPI_BASE			0x60000
ed5eb1b78a88302 Jani Nikula                   2018-12-31    207  
ed5eb1b78a88302 Jani Nikula                   2018-12-31    208  #define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display_mmio_offset)
ed5eb1b78a88302 Jani Nikula                   2018-12-31    209  
e67005e59a74613 Jani Nikula                   2018-06-29    210  /*
e67005e59a74613 Jani Nikula                   2018-06-29    211   * Given the first two numbers __a and __b of arbitrarily many evenly spaced
e67005e59a74613 Jani Nikula                   2018-06-29    212   * numbers, pick the 0-based __index'th value.
e67005e59a74613 Jani Nikula                   2018-06-29    213   *
e67005e59a74613 Jani Nikula                   2018-06-29    214   * Always prefer this over _PICK() if the numbers are evenly spaced.
e67005e59a74613 Jani Nikula                   2018-06-29    215   */
e67005e59a74613 Jani Nikula                   2018-06-29    216  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
e67005e59a74613 Jani Nikula                   2018-06-29    217  
e67005e59a74613 Jani Nikula                   2018-06-29    218  /*
e67005e59a74613 Jani Nikula                   2018-06-29    219   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
e67005e59a74613 Jani Nikula                   2018-06-29    220   *
e67005e59a74613 Jani Nikula                   2018-06-29    221   * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
e67005e59a74613 Jani Nikula                   2018-06-29    222   */
ce64645d86ac555 Jani Nikula                   2017-01-27    223  #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
ce64645d86ac555 Jani Nikula                   2017-01-27    224  
e67005e59a74613 Jani Nikula                   2018-06-29    225  /*
e67005e59a74613 Jani Nikula                   2018-06-29    226   * Named helper wrappers around _PICK_EVEN() and _PICK().
e67005e59a74613 Jani Nikula                   2018-06-29    227   */
e67005e59a74613 Jani Nikula                   2018-06-29    228  #define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)
e67005e59a74613 Jani Nikula                   2018-06-29    229  #define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)
e67005e59a74613 Jani Nikula                   2018-06-29    230  #define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)
e67005e59a74613 Jani Nikula                   2018-06-29    231  #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
e67005e59a74613 Jani Nikula                   2018-06-29    232  #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
8d97b4a93646343 Jani Nikula                   2018-10-31    233  
8d97b4a93646343 Jani Nikula                   2018-10-31    234  #define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
8d97b4a93646343 Jani Nikula                   2018-10-31    235  #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
8d97b4a93646343 Jani Nikula                   2018-10-31    236  #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
8d97b4a93646343 Jani Nikula                   2018-10-31    237  #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
a927c927de34652 Rodrigo Vivi                  2017-06-09    238  #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
8d97b4a93646343 Jani Nikula                   2018-10-31    239  
ce64645d86ac555 Jani Nikula                   2017-01-27    240  #define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
8d97b4a93646343 Jani Nikula                   2018-10-31    241  
8d97b4a93646343 Jani Nikula                   2018-10-31    242  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
8d97b4a93646343 Jani Nikula                   2018-10-31    243  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02    244  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
36ca5335f202bd5 Lucas De Marchi               2019-07-11    245  #define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
2b139522008b824 Eugeni Dodonov                2012-03-29    246  
a7c0149f1678d1d Jani Nikula                   2018-10-31    247  /*
a7c0149f1678d1d Jani Nikula                   2018-10-31    248   * Device info offset array based helpers for groups of registers with unevenly
a7c0149f1678d1d Jani Nikula                   2018-10-31    249   * spaced base offsets.
a7c0149f1678d1d Jani Nikula                   2018-10-31    250   */
a0f04cc27c50a89 Jani Nikula                   2018-12-31    251  #define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
a0f04cc27c50a89 Jani Nikula                   2018-12-31    252  					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
ed5eb1b78a88302 Jani Nikula                   2018-12-31    253  					      DISPLAY_MMIO_BASE(dev_priv))
a0f04cc27c50a89 Jani Nikula                   2018-12-31    254  #define _MMIO_TRANS2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
a0f04cc27c50a89 Jani Nikula                   2018-12-31    255  					      INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
ed5eb1b78a88302 Jani Nikula                   2018-12-31    256  					      DISPLAY_MMIO_BASE(dev_priv))
a0f04cc27c50a89 Jani Nikula                   2018-12-31    257  #define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
a0f04cc27c50a89 Jani Nikula                   2018-12-31    258  					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
ed5eb1b78a88302 Jani Nikula                   2018-12-31    259  					      DISPLAY_MMIO_BASE(dev_priv))
a7c0149f1678d1d Jani Nikula                   2018-10-31    260  
5ee4a7a6db8eb46 Chris Wilson                  2018-06-18    261  #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
98533251b0bbfa5 Damien Lespiau                2014-12-08    262  #define _MASKED_FIELD(mask, value) ({					   \
98533251b0bbfa5 Damien Lespiau                2014-12-08    263  	if (__builtin_constant_p(mask))					   \
98533251b0bbfa5 Damien Lespiau                2014-12-08    264  		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
98533251b0bbfa5 Damien Lespiau                2014-12-08    265  	if (__builtin_constant_p(value))				   \
98533251b0bbfa5 Damien Lespiau                2014-12-08    266  		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
98533251b0bbfa5 Damien Lespiau                2014-12-08    267  	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
98533251b0bbfa5 Damien Lespiau                2014-12-08    268  		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
98533251b0bbfa5 Damien Lespiau                2014-12-08    269  				 "Incorrect value for mask");		   \
5ee4a7a6db8eb46 Chris Wilson                  2018-06-18    270  	__MASKED_FIELD(mask, value); })
98533251b0bbfa5 Damien Lespiau                2014-12-08    271  #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
98533251b0bbfa5 Damien Lespiau                2014-12-08    272  #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
98533251b0bbfa5 Damien Lespiau                2014-12-08    273  
237ae7c79e26837 Michal Wajdeczko              2017-03-01    274  /* Engine ID */
98533251b0bbfa5 Damien Lespiau                2014-12-08    275  
8a68d464366efb5 Chris Wilson                  2019-03-05    276  #define RCS0_HW		0
8a68d464366efb5 Chris Wilson                  2019-03-05    277  #define VCS0_HW		1
8a68d464366efb5 Chris Wilson                  2019-03-05    278  #define BCS0_HW		2
8a68d464366efb5 Chris Wilson                  2019-03-05    279  #define VECS0_HW	3
8a68d464366efb5 Chris Wilson                  2019-03-05    280  #define VCS1_HW		4
8a68d464366efb5 Chris Wilson                  2019-03-05    281  #define VCS2_HW		6
8a68d464366efb5 Chris Wilson                  2019-03-05    282  #define VCS3_HW		7
8a68d464366efb5 Chris Wilson                  2019-03-05    283  #define VECS1_HW	12
6b26c86d615747f Daniel Vetter                 2012-04-24    284  
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    285  /* Engine class */
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    286  
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    287  #define RENDER_CLASS		0
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    288  #define VIDEO_DECODE_CLASS	1
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    289  #define VIDEO_ENHANCEMENT_CLASS	2
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    290  #define COPY_ENGINE_CLASS	3
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    291  #define OTHER_CLASS		4
b46a33e271ed81b Tvrtko Ursulin                2017-11-21    292  #define MAX_ENGINE_CLASS	4
b46a33e271ed81b Tvrtko Ursulin                2017-11-21    293  
54c52a8412501fe Oscar Mateo                   2019-05-27    294  #define OTHER_GUC_INSTANCE	0
d02b98b8e28278f Oscar Mateo                   2018-04-05    295  #define OTHER_GTPM_INSTANCE	1
022d3093a9102a8 Tvrtko Ursulin                2018-02-28    296  #define MAX_ENGINE_INSTANCE    3
0908180b9a1cf8c Daniele Ceraolo Spurio        2017-04-10    297  
585fb111348f7cd Jesse Barnes                  2008-07-29    298  /* PCI config space */
585fb111348f7cd Jesse Barnes                  2008-07-29    299  
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    300  #define MCHBAR_I915 0x44
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    301  #define MCHBAR_I965 0x48
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    302  #define MCHBAR_SIZE (4 * 4096)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    303  
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    304  #define DEVEN 0x54
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    305  #define   DEVEN_MCHBAR_EN (1 << 28)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    306  
40006c4355e3469 Joonas Lahtinen               2016-10-12    307  /* BSM in include/drm/i915_drm.h */
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    308  
1b1d27160dad547 Ville Syrjälä                 2015-05-22    309  #define HPLLCC	0xc0 /* 85x only */
1b1d27160dad547 Ville Syrjälä                 2015-05-22    310  #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29    311  #define   GC_CLOCK_133_200		(0 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29    312  #define   GC_CLOCK_100_200		(1 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29    313  #define   GC_CLOCK_100_133		(2 << 0)
1b1d27160dad547 Ville Syrjälä                 2015-05-22    314  #define   GC_CLOCK_133_266		(3 << 0)
1b1d27160dad547 Ville Syrjälä                 2015-05-22    315  #define   GC_CLOCK_133_200_2		(4 << 0)
1b1d27160dad547 Ville Syrjälä                 2015-05-22    316  #define   GC_CLOCK_133_266_2		(5 << 0)
1b1d27160dad547 Ville Syrjälä                 2015-05-22    317  #define   GC_CLOCK_166_266		(6 << 0)
1b1d27160dad547 Ville Syrjälä                 2015-05-22    318  #define   GC_CLOCK_166_250		(7 << 0)
1b1d27160dad547 Ville Syrjälä                 2015-05-22    319  
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    320  #define I915_GDRST 0xc0 /* PCI config register */
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    321  #define   GRDOM_FULL		(0 << 2)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    322  #define   GRDOM_RENDER		(1 << 2)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    323  #define   GRDOM_MEDIA		(3 << 2)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    324  #define   GRDOM_MASK		(3 << 2)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    325  #define   GRDOM_RESET_STATUS	(1 << 1)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    326  #define   GRDOM_RESET_ENABLE	(1 << 0)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    327  
8fdded8215f460c Ville Syrjälä                 2016-12-07    328  /* BSpec only has register offset, PCI device and bit found empirically */
8fdded8215f460c Ville Syrjälä                 2016-12-07    329  #define I830_CLOCK_GATE	0xc8 /* device 0 */
8fdded8215f460c Ville Syrjälä                 2016-12-07    330  #define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
8fdded8215f460c Ville Syrjälä                 2016-12-07    331  
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    332  #define GCDGMBUS 0xcc
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    333  
f97108d1d0facc7 Jesse Barnes                  2010-01-29    334  #define GCFGC2	0xda
585fb111348f7cd Jesse Barnes                  2008-07-29    335  #define GCFGC	0xf0 /* 915+ only */
585fb111348f7cd Jesse Barnes                  2008-07-29    336  #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
585fb111348f7cd Jesse Barnes                  2008-07-29    337  #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
6248017ae5301cc Arthur Heymans                2017-02-01    338  #define   GC_DISPLAY_CLOCK_333_320_MHZ	(4 << 4)
257a7ffcfaf6871 Daniel Vetter                 2013-07-26    339  #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
257a7ffcfaf6871 Daniel Vetter                 2013-07-26    340  #define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
257a7ffcfaf6871 Daniel Vetter                 2013-07-26    341  #define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
257a7ffcfaf6871 Daniel Vetter                 2013-07-26    342  #define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
257a7ffcfaf6871 Daniel Vetter                 2013-07-26    343  #define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
257a7ffcfaf6871 Daniel Vetter                 2013-07-26    344  #define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29    345  #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
652c393a3368af8 Jesse Barnes                  2009-08-17    346  #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    347  #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    348  #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    349  #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    350  #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    351  #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    352  #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    353  #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    354  #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    355  #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    356  #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    357  #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    358  #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    359  #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    360  #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    361  #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    362  #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    363  #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17    364  #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
7f1bdbcb325b5cd Daniel Vetter                 2014-01-16    365  
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    366  #define ASLE	0xe4
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    367  #define ASLS	0xfc
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    368  
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    369  #define SWSCI	0xe8
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    370  #define   SWSCI_SCISEL	(1 << 15)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    371  #define   SWSCI_GSSCIE	(1 << 0)
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    372  
e10fa551ae37b79 Joonas Lahtinen               2016-04-15    373  #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
eeccdcac07c1e21 Kenneth Graunke               2010-09-11    374  
585fb111348f7cd Jesse Barnes                  2008-07-29    375  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    376  #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
b3a3f03d7b1cfec Ville Syrjälä                 2014-05-19    377  #define  ILK_GRDOM_FULL		(0 << 1)
b3a3f03d7b1cfec Ville Syrjälä                 2014-05-19    378  #define  ILK_GRDOM_RENDER	(1 << 1)
b3a3f03d7b1cfec Ville Syrjälä                 2014-05-19    379  #define  ILK_GRDOM_MEDIA	(3 << 1)
b3a3f03d7b1cfec Ville Syrjälä                 2014-05-19    380  #define  ILK_GRDOM_MASK		(3 << 1)
b3a3f03d7b1cfec Ville Syrjälä                 2014-05-19    381  #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
b3a3f03d7b1cfec Ville Syrjälä                 2014-05-19    382  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    383  #define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
07b7ddd9b7f17a5 Jesse Barnes                  2011-08-03    384  #define   GEN6_MBC_SNPCR_SHIFT	21
07b7ddd9b7f17a5 Jesse Barnes                  2011-08-03    385  #define   GEN6_MBC_SNPCR_MASK	(3 << 21)
07b7ddd9b7f17a5 Jesse Barnes                  2011-08-03    386  #define   GEN6_MBC_SNPCR_MAX	(0 << 21)
07b7ddd9b7f17a5 Jesse Barnes                  2011-08-03    387  #define   GEN6_MBC_SNPCR_MED	(1 << 21)
07b7ddd9b7f17a5 Jesse Barnes                  2011-08-03    388  #define   GEN6_MBC_SNPCR_LOW	(2 << 21)
07b7ddd9b7f17a5 Jesse Barnes                  2011-08-03    389  #define   GEN6_MBC_SNPCR_MIN	(3 << 21) /* only 1/16th of the cache is shared */
07b7ddd9b7f17a5 Jesse Barnes                  2011-08-03    390  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    391  #define VLV_G3DCTL		_MMIO(0x9024)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    392  #define VLV_GSCKGCTL		_MMIO(0x9028)
9e72b46c0d92735 Imre Deak                     2014-05-05    393  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    394  #define GEN6_MBCTL		_MMIO(0x0907c)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    395  #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    396  #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    397  #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    398  #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    399  #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    400  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    401  #define GEN6_GDRST	_MMIO(0x941c)
cff458c21063de9 Eric Anholt                   2010-11-18    402  #define  GEN6_GRDOM_FULL		(1 << 0)
cff458c21063de9 Eric Anholt                   2010-11-18    403  #define  GEN6_GRDOM_RENDER		(1 << 1)
cff458c21063de9 Eric Anholt                   2010-11-18    404  #define  GEN6_GRDOM_MEDIA		(1 << 2)
cff458c21063de9 Eric Anholt                   2010-11-18    405  #define  GEN6_GRDOM_BLT			(1 << 3)
ee4b6faf96a990d Mika Kuoppala                 2016-03-16    406  #define  GEN6_GRDOM_VECS		(1 << 4)
6b332fa20f67126 Arun Siluvery                 2016-04-04    407  #define  GEN9_GRDOM_GUC			(1 << 5)
ee4b6faf96a990d Mika Kuoppala                 2016-03-16    408  #define  GEN8_GRDOM_MEDIA2		(1 << 7)
e34b0345e6a531f Michel Thierry                2018-04-05    409  /* GEN11 changed all bit defs except for FULL & RENDER */
e34b0345e6a531f Michel Thierry                2018-04-05    410  #define  GEN11_GRDOM_FULL		GEN6_GRDOM_FULL
e34b0345e6a531f Michel Thierry                2018-04-05    411  #define  GEN11_GRDOM_RENDER		GEN6_GRDOM_RENDER
e34b0345e6a531f Michel Thierry                2018-04-05    412  #define  GEN11_GRDOM_BLT		(1 << 2)
e34b0345e6a531f Michel Thierry                2018-04-05    413  #define  GEN11_GRDOM_GUC		(1 << 3)
e34b0345e6a531f Michel Thierry                2018-04-05    414  #define  GEN11_GRDOM_MEDIA		(1 << 5)
e34b0345e6a531f Michel Thierry                2018-04-05    415  #define  GEN11_GRDOM_MEDIA2		(1 << 6)
e34b0345e6a531f Michel Thierry                2018-04-05    416  #define  GEN11_GRDOM_MEDIA3		(1 << 7)
e34b0345e6a531f Michel Thierry                2018-04-05    417  #define  GEN11_GRDOM_MEDIA4		(1 << 8)
e34b0345e6a531f Michel Thierry                2018-04-05    418  #define  GEN11_GRDOM_VECS		(1 << 13)
e34b0345e6a531f Michel Thierry                2018-04-05    419  #define  GEN11_GRDOM_VECS2		(1 << 14)
f513ac76530c276 Oscar Mateo                   2018-12-13    420  #define  GEN11_GRDOM_SFC0		(1 << 17)
f513ac76530c276 Oscar Mateo                   2018-12-13    421  #define  GEN11_GRDOM_SFC1		(1 << 18)
f513ac76530c276 Oscar Mateo                   2018-12-13    422  
f513ac76530c276 Oscar Mateo                   2018-12-13    423  #define  GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << ((instance) >> 1))
f513ac76530c276 Oscar Mateo                   2018-12-13    424  #define  GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << (instance))
f513ac76530c276 Oscar Mateo                   2018-12-13    425  
f513ac76530c276 Oscar Mateo                   2018-12-13    426  #define GEN11_VCS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x88C)
f513ac76530c276 Oscar Mateo                   2018-12-13    427  #define   GEN11_VCS_SFC_FORCED_LOCK_BIT		(1 << 0)
f513ac76530c276 Oscar Mateo                   2018-12-13    428  #define GEN11_VCS_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x890)
f513ac76530c276 Oscar Mateo                   2018-12-13    429  #define   GEN11_VCS_SFC_USAGE_BIT		(1 << 0)
f513ac76530c276 Oscar Mateo                   2018-12-13    430  #define   GEN11_VCS_SFC_LOCK_ACK_BIT		(1 << 1)
f513ac76530c276 Oscar Mateo                   2018-12-13    431  
f513ac76530c276 Oscar Mateo                   2018-12-13    432  #define GEN11_VECS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x201C)
f513ac76530c276 Oscar Mateo                   2018-12-13    433  #define   GEN11_VECS_SFC_FORCED_LOCK_BIT	(1 << 0)
f513ac76530c276 Oscar Mateo                   2018-12-13    434  #define GEN11_VECS_SFC_LOCK_ACK(engine)		_MMIO((engine)->mmio_base + 0x2018)
f513ac76530c276 Oscar Mateo                   2018-12-13    435  #define   GEN11_VECS_SFC_LOCK_ACK_BIT		(1 << 0)
f513ac76530c276 Oscar Mateo                   2018-12-13    436  #define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)
f513ac76530c276 Oscar Mateo                   2018-12-13    437  #define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)
cff458c21063de9 Eric Anholt                   2010-11-18    438  
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25    439  #define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25    440  #define RING_PP_DIR_BASE_READ(base)	_MMIO((base) + 0x518)
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25    441  #define RING_PP_DIR_DCLV(base)		_MMIO((base) + 0x220)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    442  #define   PP_DIR_DCLV_2G		0xffffffff
5eb719cdbe47237 Daniel Vetter                 2012-02-09    443  
6d4257284a87ecb Chris Wilson                  2019-04-05    444  #define GEN8_RING_PDP_UDW(base, n)	_MMIO((base) + 0x270 + (n) * 8 + 4)
6d4257284a87ecb Chris Wilson                  2019-04-05    445  #define GEN8_RING_PDP_LDW(base, n)	_MMIO((base) + 0x270 + (n) * 8)
94e409c1449858b Ben Widawsky                  2013-11-04    446  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    447  #define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
0cea6502bf9c40c Jeff McGee                    2015-02-13    448  #define   GEN8_RPCS_ENABLE		(1 << 31)
0cea6502bf9c40c Jeff McGee                    2015-02-13    449  #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
0cea6502bf9c40c Jeff McGee                    2015-02-13    450  #define   GEN8_RPCS_S_CNT_SHIFT		15
0cea6502bf9c40c Jeff McGee                    2015-02-13    451  #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
b212f0a470eeb62 Tvrtko Ursulin                2018-09-03    452  #define   GEN11_RPCS_S_CNT_SHIFT	12
b212f0a470eeb62 Tvrtko Ursulin                2018-09-03    453  #define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)
0cea6502bf9c40c Jeff McGee                    2015-02-13    454  #define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
0cea6502bf9c40c Jeff McGee                    2015-02-13    455  #define   GEN8_RPCS_SS_CNT_SHIFT	8
0cea6502bf9c40c Jeff McGee                    2015-02-13    456  #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
0cea6502bf9c40c Jeff McGee                    2015-02-13    457  #define   GEN8_RPCS_EU_MAX_SHIFT	4
0cea6502bf9c40c Jeff McGee                    2015-02-13    458  #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
0cea6502bf9c40c Jeff McGee                    2015-02-13    459  #define   GEN8_RPCS_EU_MIN_SHIFT	0
0cea6502bf9c40c Jeff McGee                    2015-02-13    460  #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
0cea6502bf9c40c Jeff McGee                    2015-02-13    461  
f89823c212246d0 Lionel Landwerlin             2017-08-03    462  #define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
f89823c212246d0 Lionel Landwerlin             2017-08-03    463  /* HSW only */
f89823c212246d0 Lionel Landwerlin             2017-08-03    464  #define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT		2
f89823c212246d0 Lionel Landwerlin             2017-08-03    465  #define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
f89823c212246d0 Lionel Landwerlin             2017-08-03    466  #define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT		4
f89823c212246d0 Lionel Landwerlin             2017-08-03    467  #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
f89823c212246d0 Lionel Landwerlin             2017-08-03    468  /* HSW+ */
f89823c212246d0 Lionel Landwerlin             2017-08-03    469  #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
f89823c212246d0 Lionel Landwerlin             2017-08-03    470  #define   HSW_RCS_CONTEXT_ENABLE			(1 << 7)
f89823c212246d0 Lionel Landwerlin             2017-08-03    471  #define   HSW_RCS_INHIBIT				(1 << 8)
f89823c212246d0 Lionel Landwerlin             2017-08-03    472  /* Gen8 */
f89823c212246d0 Lionel Landwerlin             2017-08-03    473  #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
f89823c212246d0 Lionel Landwerlin             2017-08-03    474  #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
f89823c212246d0 Lionel Landwerlin             2017-08-03    475  #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
f89823c212246d0 Lionel Landwerlin             2017-08-03    476  #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
f89823c212246d0 Lionel Landwerlin             2017-08-03    477  #define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE	(1 << 6)
f89823c212246d0 Lionel Landwerlin             2017-08-03    478  #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT	9
f89823c212246d0 Lionel Landwerlin             2017-08-03    479  #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
f89823c212246d0 Lionel Landwerlin             2017-08-03    480  #define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT	11
f89823c212246d0 Lionel Landwerlin             2017-08-03    481  #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
f89823c212246d0 Lionel Landwerlin             2017-08-03    482  #define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)
f89823c212246d0 Lionel Landwerlin             2017-08-03    483  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    484  #define GAM_ECOCHK			_MMIO(0x4090)
81e231afe7478f1 Damien Lespiau                2015-02-09    485  #define   BDW_DISABLE_HDC_INVALIDATION	(1 << 25)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    486  #define   ECOCHK_SNB_BIT		(1 << 10)
6381b55016ec76f Nick Hoath                    2015-07-14    487  #define   ECOCHK_DIS_TLB		(1 << 8)
e3dff585508636c Ben Widawsky                  2013-03-20    488  #define   HSW_ECOCHK_ARB_PRIO_SOL	(1 << 6)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    489  #define   ECOCHK_PPGTT_CACHE64B		(0x3 << 3)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    490  #define   ECOCHK_PPGTT_CACHE4B		(0x0 << 3)
a6f429a5a2f6ae0 Ville Syrjälä                 2013-04-04    491  #define   ECOCHK_PPGTT_GFDT_IVB		(0x1 << 4)
a6f429a5a2f6ae0 Ville Syrjälä                 2013-04-04    492  #define   ECOCHK_PPGTT_LLC_IVB		(0x1 << 3)
a6f429a5a2f6ae0 Ville Syrjälä                 2013-04-04    493  #define   ECOCHK_PPGTT_UC_HSW		(0x1 << 3)
a6f429a5a2f6ae0 Ville Syrjälä                 2013-04-04    494  #define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)
a6f429a5a2f6ae0 Ville Syrjälä                 2013-04-04    495  #define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)
5eb719cdbe47237 Daniel Vetter                 2012-02-09    496  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    497  #define GAC_ECO_BITS			_MMIO(0x14090)
3b9d7888df1d1ee Ville Syrjälä                 2013-04-04    498  #define   ECOBITS_SNB_BIT		(1 << 13)
48ecfa1090b6539 Daniel Vetter                 2012-04-11    499  #define   ECOBITS_PPGTT_CACHE64B	(3 << 8)
48ecfa1090b6539 Daniel Vetter                 2012-04-11    500  #define   ECOBITS_PPGTT_CACHE4B		(0 << 8)
48ecfa1090b6539 Daniel Vetter                 2012-04-11    501  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    502  #define GAB_CTL				_MMIO(0x24000)
be901a5a1bdb13c Daniel Vetter                 2012-04-11    503  #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1 << 8)
be901a5a1bdb13c Daniel Vetter                 2012-04-11    504  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    505  #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    506  #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    507  #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    508  #define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    509  #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    510  #define GEN6_STOLEN_RESERVED_512K	(1 << 4)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    511  #define GEN6_STOLEN_RESERVED_256K	(2 << 4)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    512  #define GEN6_STOLEN_RESERVED_128K	(3 << 4)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    513  #define GEN7_STOLEN_RESERVED_SIZE_MASK	(1 << 5)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    514  #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    515  #define GEN7_STOLEN_RESERVED_256K	(1 << 5)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    516  #define GEN8_STOLEN_RESERVED_SIZE_MASK	(3 << 7)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    517  #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    518  #define GEN8_STOLEN_RESERVED_2M		(1 << 7)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    519  #define GEN8_STOLEN_RESERVED_4M		(2 << 7)
3774eb507e7b7df Paulo Zanoni                  2015-08-10    520  #define GEN8_STOLEN_RESERVED_8M		(3 << 7)
db7fb60593e4282 Ville Syrjälä                 2017-11-02    521  #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
185441e03aa9dde Paulo Zanoni                  2018-05-04    522  #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
40bae736116233a Daniel Vetter                 2014-09-11    523  
585fb111348f7cd Jesse Barnes                  2008-07-29    524  /* VGA stuff */
585fb111348f7cd Jesse Barnes                  2008-07-29    525  
585fb111348f7cd Jesse Barnes                  2008-07-29    526  #define VGA_ST01_MDA 0x3ba
585fb111348f7cd Jesse Barnes                  2008-07-29    527  #define VGA_ST01_CGA 0x3da
585fb111348f7cd Jesse Barnes                  2008-07-29    528  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    529  #define _VGA_MSR_WRITE _MMIO(0x3c2)
585fb111348f7cd Jesse Barnes                  2008-07-29    530  #define VGA_MSR_WRITE 0x3c2
585fb111348f7cd Jesse Barnes                  2008-07-29    531  #define VGA_MSR_READ 0x3cc
585fb111348f7cd Jesse Barnes                  2008-07-29    532  #define   VGA_MSR_MEM_EN (1 << 1)
585fb111348f7cd Jesse Barnes                  2008-07-29    533  #define   VGA_MSR_CGA_MODE (1 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29    534  
5434fd926d1e4de Ville Syrjälä                 2013-06-06    535  #define VGA_SR_INDEX 0x3c4
f930ddd0583c1a9 Daniel Vetter                 2012-11-21    536  #define SR01			1
5434fd926d1e4de Ville Syrjälä                 2013-06-06    537  #define VGA_SR_DATA 0x3c5
585fb111348f7cd Jesse Barnes                  2008-07-29    538  
585fb111348f7cd Jesse Barnes                  2008-07-29    539  #define VGA_AR_INDEX 0x3c0
585fb111348f7cd Jesse Barnes                  2008-07-29    540  #define   VGA_AR_VID_EN (1 << 5)
585fb111348f7cd Jesse Barnes                  2008-07-29    541  #define VGA_AR_DATA_WRITE 0x3c0
585fb111348f7cd Jesse Barnes                  2008-07-29    542  #define VGA_AR_DATA_READ 0x3c1
585fb111348f7cd Jesse Barnes                  2008-07-29    543  
585fb111348f7cd Jesse Barnes                  2008-07-29    544  #define VGA_GR_INDEX 0x3ce
585fb111348f7cd Jesse Barnes                  2008-07-29    545  #define VGA_GR_DATA 0x3cf
585fb111348f7cd Jesse Barnes                  2008-07-29    546  /* GR05 */
585fb111348f7cd Jesse Barnes                  2008-07-29    547  #define   VGA_GR_MEM_READ_MODE_SHIFT 3
585fb111348f7cd Jesse Barnes                  2008-07-29    548  #define     VGA_GR_MEM_READ_MODE_PLANE 1
585fb111348f7cd Jesse Barnes                  2008-07-29    549  /* GR06 */
585fb111348f7cd Jesse Barnes                  2008-07-29    550  #define   VGA_GR_MEM_MODE_MASK 0xc
585fb111348f7cd Jesse Barnes                  2008-07-29    551  #define   VGA_GR_MEM_MODE_SHIFT 2
585fb111348f7cd Jesse Barnes                  2008-07-29    552  #define   VGA_GR_MEM_A0000_AFFFF 0
585fb111348f7cd Jesse Barnes                  2008-07-29    553  #define   VGA_GR_MEM_A0000_BFFFF 1
585fb111348f7cd Jesse Barnes                  2008-07-29    554  #define   VGA_GR_MEM_B0000_B7FFF 2
585fb111348f7cd Jesse Barnes                  2008-07-29    555  #define   VGA_GR_MEM_B0000_BFFFF 3
585fb111348f7cd Jesse Barnes                  2008-07-29    556  
585fb111348f7cd Jesse Barnes                  2008-07-29    557  #define VGA_DACMASK 0x3c6
585fb111348f7cd Jesse Barnes                  2008-07-29    558  #define VGA_DACRX 0x3c7
585fb111348f7cd Jesse Barnes                  2008-07-29    559  #define VGA_DACWX 0x3c8
585fb111348f7cd Jesse Barnes                  2008-07-29    560  #define VGA_DACDATA 0x3c9
585fb111348f7cd Jesse Barnes                  2008-07-29    561  
585fb111348f7cd Jesse Barnes                  2008-07-29    562  #define VGA_CR_INDEX_MDA 0x3b4
585fb111348f7cd Jesse Barnes                  2008-07-29    563  #define VGA_CR_DATA_MDA 0x3b5
585fb111348f7cd Jesse Barnes                  2008-07-29    564  #define VGA_CR_INDEX_CGA 0x3d4
585fb111348f7cd Jesse Barnes                  2008-07-29    565  #define VGA_CR_DATA_CGA 0x3d5
585fb111348f7cd Jesse Barnes                  2008-07-29    566  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    567  #define MI_PREDICATE_SRC0	_MMIO(0x2400)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    568  #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    569  #define MI_PREDICATE_SRC1	_MMIO(0x2408)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    570  #define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
9435373ef8870e0 Rodrigo Vivi                  2013-08-28    571  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    572  #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
9435373ef8870e0 Rodrigo Vivi                  2013-08-28    573  #define  LOWER_SLICE_ENABLED	(1 << 0)
9435373ef8870e0 Rodrigo Vivi                  2013-08-28    574  #define  LOWER_SLICE_DISABLED	(0 << 0)
9435373ef8870e0 Rodrigo Vivi                  2013-08-28    575  
585fb111348f7cd Jesse Barnes                  2008-07-29    576  /*
5947de9b46d472f Brad Volkin                   2014-02-18    577   * Registers used only by the command parser
5947de9b46d472f Brad Volkin                   2014-02-18    578   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    579  #define BCS_SWCTRL _MMIO(0x22200)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    580  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    581  #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    582  #define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    583  #define HS_INVOCATION_COUNT             _MMIO(0x2300)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    584  #define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    585  #define DS_INVOCATION_COUNT             _MMIO(0x2308)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    586  #define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    587  #define IA_VERTICES_COUNT               _MMIO(0x2310)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    588  #define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    589  #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    590  #define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    591  #define VS_INVOCATION_COUNT             _MMIO(0x2320)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    592  #define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    593  #define GS_INVOCATION_COUNT             _MMIO(0x2328)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    594  #define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    595  #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    596  #define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    597  #define CL_INVOCATION_COUNT             _MMIO(0x2338)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    598  #define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    599  #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    600  #define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    601  #define PS_INVOCATION_COUNT             _MMIO(0x2348)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    602  #define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    603  #define PS_DEPTH_COUNT                  _MMIO(0x2350)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    604  #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
5947de9b46d472f Brad Volkin                   2014-02-18    605  
5947de9b46d472f Brad Volkin                   2014-02-18    606  /* There are the 4 64-bit counter registers, one for each stream output */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    607  #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    608  #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
5947de9b46d472f Brad Volkin                   2014-02-18    609  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    610  #define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    611  #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
113a047633eb7ee Brad Volkin                   2014-04-08    612  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    613  #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    614  #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    615  #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    616  #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    617  #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    618  #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
113a047633eb7ee Brad Volkin                   2014-04-08    619  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    620  #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    621  #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18    622  #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
7b9748cb513a6be Jordan Justen                 2015-10-01    623  
1b85066bb1332e4 Jordan Justen                 2016-03-06    624  /* There are the 16 64-bit CS General Purpose Registers */
1b85066bb1332e4 Jordan Justen                 2016-03-06    625  #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
1b85066bb1332e4 Jordan Justen                 2016-03-06    626  #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
1b85066bb1332e4 Jordan Justen                 2016-03-06    627  
a941795a3aead37 Robert Bragg                  2016-11-07    628  #define GEN7_OACONTROL _MMIO(0x2360)
d79651522e89c4f Robert Bragg                  2016-11-07    629  #define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
d79651522e89c4f Robert Bragg                  2016-11-07    630  #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
d79651522e89c4f Robert Bragg                  2016-11-07    631  #define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
d79651522e89c4f Robert Bragg                  2016-11-07    632  #define  GEN7_OACONTROL_TIMER_ENABLE	    (1 << 5)
d79651522e89c4f Robert Bragg                  2016-11-07    633  #define  GEN7_OACONTROL_FORMAT_A13	    (0 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    634  #define  GEN7_OACONTROL_FORMAT_A29	    (1 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    635  #define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    636  #define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    637  #define  GEN7_OACONTROL_FORMAT_B4_C8	    (4 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    638  #define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    639  #define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    640  #define  GEN7_OACONTROL_FORMAT_C4_B8	    (7 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    641  #define  GEN7_OACONTROL_FORMAT_SHIFT	    2
d79651522e89c4f Robert Bragg                  2016-11-07    642  #define  GEN7_OACONTROL_PER_CTX_ENABLE	    (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    643  #define  GEN7_OACONTROL_ENABLE		    (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    644  
d79651522e89c4f Robert Bragg                  2016-11-07    645  #define GEN8_OACTXID _MMIO(0x2364)
d79651522e89c4f Robert Bragg                  2016-11-07    646  
19f81df2859eb10 Robert Bragg                  2017-06-13    647  #define GEN8_OA_DEBUG _MMIO(0x2B04)
19f81df2859eb10 Robert Bragg                  2017-06-13    648  #define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1 << 5)
19f81df2859eb10 Robert Bragg                  2017-06-13    649  #define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO	    (1 << 6)
19f81df2859eb10 Robert Bragg                  2017-06-13    650  #define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS	    (1 << 2)
19f81df2859eb10 Robert Bragg                  2017-06-13    651  #define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
19f81df2859eb10 Robert Bragg                  2017-06-13    652  
d79651522e89c4f Robert Bragg                  2016-11-07    653  #define GEN8_OACONTROL _MMIO(0x2B00)
d79651522e89c4f Robert Bragg                  2016-11-07    654  #define  GEN8_OA_REPORT_FORMAT_A12	    (0 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    655  #define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    656  #define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    657  #define  GEN8_OA_REPORT_FORMAT_C4_B8	    (7 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    658  #define  GEN8_OA_REPORT_FORMAT_SHIFT	    2
d79651522e89c4f Robert Bragg                  2016-11-07    659  #define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    660  #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    661  
d79651522e89c4f Robert Bragg                  2016-11-07    662  #define GEN8_OACTXCONTROL _MMIO(0x2360)
d79651522e89c4f Robert Bragg                  2016-11-07    663  #define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
d79651522e89c4f Robert Bragg                  2016-11-07    664  #define  GEN8_OA_TIMER_PERIOD_SHIFT	    2
d79651522e89c4f Robert Bragg                  2016-11-07    665  #define  GEN8_OA_TIMER_ENABLE		    (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    666  #define  GEN8_OA_COUNTER_RESUME		    (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    667  
d79651522e89c4f Robert Bragg                  2016-11-07    668  #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
d79651522e89c4f Robert Bragg                  2016-11-07    669  #define  GEN7_OABUFFER_OVERRUN_DISABLE	    (1 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    670  #define  GEN7_OABUFFER_EDGE_TRIGGER	    (1 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    671  #define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    672  #define  GEN7_OABUFFER_RESUME		    (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    673  
19f81df2859eb10 Robert Bragg                  2017-06-13    674  #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
d79651522e89c4f Robert Bragg                  2016-11-07    675  #define GEN8_OABUFFER _MMIO(0x2b14)
b82ed43de5c01e4 Lionel Landwerlin             2018-03-26    676  #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
d79651522e89c4f Robert Bragg                  2016-11-07    677  
d79651522e89c4f Robert Bragg                  2016-11-07    678  #define GEN7_OASTATUS1 _MMIO(0x2364)
d79651522e89c4f Robert Bragg                  2016-11-07    679  #define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
d79651522e89c4f Robert Bragg                  2016-11-07    680  #define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    681  #define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    682  #define  GEN7_OASTATUS1_REPORT_LOST	    (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    683  
d79651522e89c4f Robert Bragg                  2016-11-07    684  #define GEN7_OASTATUS2 _MMIO(0x2368)
d79651522e89c4f Robert Bragg                  2016-11-07    685  #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
b82ed43de5c01e4 Lionel Landwerlin             2018-03-26    686  #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
d79651522e89c4f Robert Bragg                  2016-11-07    687  
d79651522e89c4f Robert Bragg                  2016-11-07    688  #define GEN8_OASTATUS _MMIO(0x2b08)
d79651522e89c4f Robert Bragg                  2016-11-07    689  #define  GEN8_OASTATUS_OVERRUN_STATUS	    (1 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    690  #define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    691  #define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    692  #define  GEN8_OASTATUS_REPORT_LOST	    (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    693  
d79651522e89c4f Robert Bragg                  2016-11-07    694  #define GEN8_OAHEADPTR _MMIO(0x2B0C)
19f81df2859eb10 Robert Bragg                  2017-06-13    695  #define GEN8_OAHEADPTR_MASK    0xffffffc0
d79651522e89c4f Robert Bragg                  2016-11-07    696  #define GEN8_OATAILPTR _MMIO(0x2B10)
19f81df2859eb10 Robert Bragg                  2017-06-13    697  #define GEN8_OATAILPTR_MASK    0xffffffc0
d79651522e89c4f Robert Bragg                  2016-11-07    698  
d79651522e89c4f Robert Bragg                  2016-11-07    699  #define OABUFFER_SIZE_128K  (0 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    700  #define OABUFFER_SIZE_256K  (1 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    701  #define OABUFFER_SIZE_512K  (2 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    702  #define OABUFFER_SIZE_1M    (3 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    703  #define OABUFFER_SIZE_2M    (4 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    704  #define OABUFFER_SIZE_4M    (5 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    705  #define OABUFFER_SIZE_8M    (6 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    706  #define OABUFFER_SIZE_16M   (7 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    707  
19f81df2859eb10 Robert Bragg                  2017-06-13    708  /*
19f81df2859eb10 Robert Bragg                  2017-06-13    709   * Flexible, Aggregate EU Counter Registers.
19f81df2859eb10 Robert Bragg                  2017-06-13    710   * Note: these aren't contiguous
19f81df2859eb10 Robert Bragg                  2017-06-13    711   */
d79651522e89c4f Robert Bragg                  2016-11-07    712  #define EU_PERF_CNTL0	    _MMIO(0xe458)
19f81df2859eb10 Robert Bragg                  2017-06-13    713  #define EU_PERF_CNTL1	    _MMIO(0xe558)
19f81df2859eb10 Robert Bragg                  2017-06-13    714  #define EU_PERF_CNTL2	    _MMIO(0xe658)
19f81df2859eb10 Robert Bragg                  2017-06-13    715  #define EU_PERF_CNTL3	    _MMIO(0xe758)
19f81df2859eb10 Robert Bragg                  2017-06-13    716  #define EU_PERF_CNTL4	    _MMIO(0xe45c)
19f81df2859eb10 Robert Bragg                  2017-06-13    717  #define EU_PERF_CNTL5	    _MMIO(0xe55c)
19f81df2859eb10 Robert Bragg                  2017-06-13    718  #define EU_PERF_CNTL6	    _MMIO(0xe65c)
d79651522e89c4f Robert Bragg                  2016-11-07    719  
d79651522e89c4f Robert Bragg                  2016-11-07    720  /*
d79651522e89c4f Robert Bragg                  2016-11-07    721   * OA Boolean state
d79651522e89c4f Robert Bragg                  2016-11-07    722   */
d79651522e89c4f Robert Bragg                  2016-11-07    723  
d79651522e89c4f Robert Bragg                  2016-11-07    724  #define OASTARTTRIG1 _MMIO(0x2710)
d79651522e89c4f Robert Bragg                  2016-11-07    725  #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
d79651522e89c4f Robert Bragg                  2016-11-07    726  #define OASTARTTRIG1_THRESHOLD_MASK	      0xffff
d79651522e89c4f Robert Bragg                  2016-11-07    727  
d79651522e89c4f Robert Bragg                  2016-11-07    728  #define OASTARTTRIG2 _MMIO(0x2714)
d79651522e89c4f Robert Bragg                  2016-11-07    729  #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    730  #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    731  #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    732  #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    733  #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
d79651522e89c4f Robert Bragg                  2016-11-07    734  #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
d79651522e89c4f Robert Bragg                  2016-11-07    735  #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
d79651522e89c4f Robert Bragg                  2016-11-07    736  #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
d79651522e89c4f Robert Bragg                  2016-11-07    737  #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
d79651522e89c4f Robert Bragg                  2016-11-07    738  #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
d79651522e89c4f Robert Bragg                  2016-11-07    739  #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
d79651522e89c4f Robert Bragg                  2016-11-07    740  #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
d79651522e89c4f Robert Bragg                  2016-11-07    741  #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
d79651522e89c4f Robert Bragg                  2016-11-07    742  #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
d79651522e89c4f Robert Bragg                  2016-11-07    743  #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
d79651522e89c4f Robert Bragg                  2016-11-07    744  #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
d79651522e89c4f Robert Bragg                  2016-11-07    745  #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
d79651522e89c4f Robert Bragg                  2016-11-07    746  #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
d79651522e89c4f Robert Bragg                  2016-11-07    747  #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
d79651522e89c4f Robert Bragg                  2016-11-07    748  #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
d79651522e89c4f Robert Bragg                  2016-11-07    749  #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
d79651522e89c4f Robert Bragg                  2016-11-07    750  #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
d79651522e89c4f Robert Bragg                  2016-11-07    751  #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
d79651522e89c4f Robert Bragg                  2016-11-07    752  #define OASTARTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
d79651522e89c4f Robert Bragg                  2016-11-07    753  #define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1 << 24)
d79651522e89c4f Robert Bragg                  2016-11-07    754  #define OASTARTTRIG2_EVENT_SELECT_0  (1 << 28)
d79651522e89c4f Robert Bragg                  2016-11-07    755  #define OASTARTTRIG2_EVENT_SELECT_1  (1 << 29)
d79651522e89c4f Robert Bragg                  2016-11-07    756  #define OASTARTTRIG2_EVENT_SELECT_2  (1 << 30)
d79651522e89c4f Robert Bragg                  2016-11-07    757  #define OASTARTTRIG2_EVENT_SELECT_3  (1 << 31)
d79651522e89c4f Robert Bragg                  2016-11-07    758  
d79651522e89c4f Robert Bragg                  2016-11-07    759  #define OASTARTTRIG3 _MMIO(0x2718)
d79651522e89c4f Robert Bragg                  2016-11-07    760  #define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
d79651522e89c4f Robert Bragg                  2016-11-07    761  #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
d79651522e89c4f Robert Bragg                  2016-11-07    762  #define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
d79651522e89c4f Robert Bragg                  2016-11-07    763  #define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
d79651522e89c4f Robert Bragg                  2016-11-07    764  #define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
d79651522e89c4f Robert Bragg                  2016-11-07    765  #define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
d79651522e89c4f Robert Bragg                  2016-11-07    766  #define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
d79651522e89c4f Robert Bragg                  2016-11-07    767  #define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
d79651522e89c4f Robert Bragg                  2016-11-07    768  #define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28
d79651522e89c4f Robert Bragg                  2016-11-07    769  
d79651522e89c4f Robert Bragg                  2016-11-07    770  #define OASTARTTRIG4 _MMIO(0x271c)
d79651522e89c4f Robert Bragg                  2016-11-07    771  #define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
d79651522e89c4f Robert Bragg                  2016-11-07    772  #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
d79651522e89c4f Robert Bragg                  2016-11-07    773  #define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
d79651522e89c4f Robert Bragg                  2016-11-07    774  #define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
d79651522e89c4f Robert Bragg                  2016-11-07    775  #define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
d79651522e89c4f Robert Bragg                  2016-11-07    776  #define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
d79651522e89c4f Robert Bragg                  2016-11-07    777  #define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
d79651522e89c4f Robert Bragg                  2016-11-07    778  #define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
d79651522e89c4f Robert Bragg                  2016-11-07    779  #define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28
d79651522e89c4f Robert Bragg                  2016-11-07    780  
d79651522e89c4f Robert Bragg                  2016-11-07    781  #define OASTARTTRIG5 _MMIO(0x2720)
d79651522e89c4f Robert Bragg                  2016-11-07    782  #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
d79651522e89c4f Robert Bragg                  2016-11-07    783  #define OASTARTTRIG5_THRESHOLD_MASK	      0xffff
d79651522e89c4f Robert Bragg                  2016-11-07    784  
d79651522e89c4f Robert Bragg                  2016-11-07    785  #define OASTARTTRIG6 _MMIO(0x2724)
d79651522e89c4f Robert Bragg                  2016-11-07    786  #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
d79651522e89c4f Robert Bragg                  2016-11-07    787  #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
d79651522e89c4f Robert Bragg                  2016-11-07    788  #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
d79651522e89c4f Robert Bragg                  2016-11-07    789  #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
d79651522e89c4f Robert Bragg                  2016-11-07    790  #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
d79651522e89c4f Robert Bragg                  2016-11-07    791  #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
d79651522e89c4f Robert Bragg                  2016-11-07    792  #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
d79651522e89c4f Robert Bragg                  2016-11-07    793  #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
d79651522e89c4f Robert Bragg                  2016-11-07    794  #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
d79651522e89c4f Robert Bragg                  2016-11-07    795  #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
d79651522e89c4f Robert Bragg                  2016-11-07    796  #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
d79651522e89c4f Robert Bragg                  2016-11-07    797  #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
d79651522e89c4f Robert Bragg                  2016-11-07    798  #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
d79651522e89c4f Robert Bragg                  2016-11-07    799  #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
d79651522e89c4f Robert Bragg                  2016-11-07    800  #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
d79651522e89c4f Robert Bragg                  2016-11-07    801  #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
d79651522e89c4f Robert Bragg                  2016-11-07    802  #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
d79651522e89c4f Robert Bragg                  2016-11-07    803  #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
d79651522e89c4f Robert Bragg                  2016-11-07    804  #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
d79651522e89c4f Robert Bragg                  2016-11-07    805  #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
d79651522e89c4f Robert Bragg                  2016-11-07    806  #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
d79651522e89c4f Robert Bragg                  2016-11-07    807  #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
d79651522e89c4f Robert Bragg                  2016-11-07    808  #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
d79651522e89c4f Robert Bragg                  2016-11-07    809  #define OASTARTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
d79651522e89c4f Robert Bragg                  2016-11-07    810  #define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1 << 24)
d79651522e89c4f Robert Bragg                  2016-11-07    811  #define OASTARTTRIG6_EVENT_SELECT_4  (1 << 28)
d79651522e89c4f Robert Bragg                  2016-11-07    812  #define OASTARTTRIG6_EVENT_SELECT_5  (1 << 29)
d79651522e89c4f Robert Bragg                  2016-11-07    813  #define OASTARTTRIG6_EVENT_SELECT_6  (1 << 30)
d79651522e89c4f Robert Bragg                  2016-11-07    814  #define OASTARTTRIG6_EVENT_SELECT_7  (1 << 31)
d79651522e89c4f Robert Bragg                  2016-11-07    815  
d79651522e89c4f Robert Bragg                  2016-11-07    816  #define OASTARTTRIG7 _MMIO(0x2728)
d79651522e89c4f Robert Bragg                  2016-11-07    817  #define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
d79651522e89c4f Robert Bragg                  2016-11-07    818  #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
d79651522e89c4f Robert Bragg                  2016-11-07    819  #define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
d79651522e89c4f Robert Bragg                  2016-11-07    820  #define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
d79651522e89c4f Robert Bragg                  2016-11-07    821  #define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
d79651522e89c4f Robert Bragg                  2016-11-07    822  #define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
d79651522e89c4f Robert Bragg                  2016-11-07    823  #define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
d79651522e89c4f Robert Bragg                  2016-11-07    824  #define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
d79651522e89c4f Robert Bragg                  2016-11-07    825  #define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28
d79651522e89c4f Robert Bragg                  2016-11-07    826  
d79651522e89c4f Robert Bragg                  2016-11-07    827  #define OASTARTTRIG8 _MMIO(0x272c)
d79651522e89c4f Robert Bragg                  2016-11-07    828  #define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
d79651522e89c4f Robert Bragg                  2016-11-07    829  #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
d79651522e89c4f Robert Bragg                  2016-11-07    830  #define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
d79651522e89c4f Robert Bragg                  2016-11-07    831  #define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
d79651522e89c4f Robert Bragg                  2016-11-07    832  #define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
d79651522e89c4f Robert Bragg                  2016-11-07    833  #define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
d79651522e89c4f Robert Bragg                  2016-11-07    834  #define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
d79651522e89c4f Robert Bragg                  2016-11-07    835  #define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
d79651522e89c4f Robert Bragg                  2016-11-07    836  #define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28
d79651522e89c4f Robert Bragg                  2016-11-07    837  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    838  #define OAREPORTTRIG1 _MMIO(0x2740)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    839  #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    840  #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    841  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    842  #define OAREPORTTRIG2 _MMIO(0x2744)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    843  #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    844  #define OAREPORTTRIG2_INVERT_A_1  (1 << 1)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    845  #define OAREPORTTRIG2_INVERT_A_2  (1 << 2)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    846  #define OAREPORTTRIG2_INVERT_A_3  (1 << 3)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    847  #define OAREPORTTRIG2_INVERT_A_4  (1 << 4)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    848  #define OAREPORTTRIG2_INVERT_A_5  (1 << 5)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    849  #define OAREPORTTRIG2_INVERT_A_6  (1 << 6)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    850  #define OAREPORTTRIG2_INVERT_A_7  (1 << 7)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    851  #define OAREPORTTRIG2_INVERT_A_8  (1 << 8)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    852  #define OAREPORTTRIG2_INVERT_A_9  (1 << 9)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    853  #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    854  #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    855  #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    856  #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    857  #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    858  #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    859  #define OAREPORTTRIG2_INVERT_B_0  (1 << 16)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    860  #define OAREPORTTRIG2_INVERT_B_1  (1 << 17)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    861  #define OAREPORTTRIG2_INVERT_B_2  (1 << 18)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    862  #define OAREPORTTRIG2_INVERT_B_3  (1 << 19)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    863  #define OAREPORTTRIG2_INVERT_C_0  (1 << 20)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    864  #define OAREPORTTRIG2_INVERT_C_1  (1 << 21)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    865  #define OAREPORTTRIG2_INVERT_D_0  (1 << 22)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    866  #define OAREPORTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    867  #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    868  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    869  #define OAREPORTTRIG3 _MMIO(0x2748)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    870  #define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    871  #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    872  #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    873  #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    874  #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    875  #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    876  #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    877  #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    878  #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    879  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    880  #define OAREPORTTRIG4 _MMIO(0x274c)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    881  #define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    882  #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    883  #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    884  #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    885  #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    886  #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    887  #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    888  #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    889  #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    890  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    891  #define OAREPORTTRIG5 _MMIO(0x2750)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    892  #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    893  #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    894  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    895  #define OAREPORTTRIG6 _MMIO(0x2754)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    896  #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    897  #define OAREPORTTRIG6_INVERT_A_1  (1 << 1)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    898  #define OAREPORTTRIG6_INVERT_A_2  (1 << 2)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    899  #define OAREPORTTRIG6_INVERT_A_3  (1 << 3)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    900  #define OAREPORTTRIG6_INVERT_A_4  (1 << 4)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    901  #define OAREPORTTRIG6_INVERT_A_5  (1 << 5)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    902  #define OAREPORTTRIG6_INVERT_A_6  (1 << 6)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    903  #define OAREPORTTRIG6_INVERT_A_7  (1 << 7)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    904  #define OAREPORTTRIG6_INVERT_A_8  (1 << 8)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    905  #define OAREPORTTRIG6_INVERT_A_9  (1 << 9)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    906  #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    907  #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    908  #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    909  #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    910  #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    911  #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    912  #define OAREPORTTRIG6_INVERT_B_0  (1 << 16)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    913  #define OAREPORTTRIG6_INVERT_B_1  (1 << 17)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    914  #define OAREPORTTRIG6_INVERT_B_2  (1 << 18)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    915  #define OAREPORTTRIG6_INVERT_B_3  (1 << 19)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    916  #define OAREPORTTRIG6_INVERT_C_0  (1 << 20)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    917  #define OAREPORTTRIG6_INVERT_C_1  (1 << 21)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    918  #define OAREPORTTRIG6_INVERT_D_0  (1 << 22)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    919  #define OAREPORTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    920  #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    921  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    922  #define OAREPORTTRIG7 _MMIO(0x2758)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    923  #define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    924  #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    925  #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    926  #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    927  #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    928  #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    929  #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    930  #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    931  #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    932  
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    933  #define OAREPORTTRIG8 _MMIO(0x275c)
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    934  #define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    935  #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    936  #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    937  #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    938  #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    939  #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    940  #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    941  #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    942  #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28
7853d92e8e95da5 Lionel Landwerlin             2017-08-03    943  
d79651522e89c4f Robert Bragg                  2016-11-07    944  /* CECX_0 */
d79651522e89c4f Robert Bragg                  2016-11-07    945  #define OACEC_COMPARE_LESS_OR_EQUAL	6
d79651522e89c4f Robert Bragg                  2016-11-07    946  #define OACEC_COMPARE_NOT_EQUAL		5
d79651522e89c4f Robert Bragg                  2016-11-07    947  #define OACEC_COMPARE_LESS_THAN		4
d79651522e89c4f Robert Bragg                  2016-11-07    948  #define OACEC_COMPARE_GREATER_OR_EQUAL	3
d79651522e89c4f Robert Bragg                  2016-11-07    949  #define OACEC_COMPARE_EQUAL		2
d79651522e89c4f Robert Bragg                  2016-11-07    950  #define OACEC_COMPARE_GREATER_THAN	1
d79651522e89c4f Robert Bragg                  2016-11-07    951  #define OACEC_COMPARE_ANY_EQUAL		0
d79651522e89c4f Robert Bragg                  2016-11-07    952  
d79651522e89c4f Robert Bragg                  2016-11-07    953  #define OACEC_COMPARE_VALUE_MASK    0xffff
d79651522e89c4f Robert Bragg                  2016-11-07    954  #define OACEC_COMPARE_VALUE_SHIFT   3
d79651522e89c4f Robert Bragg                  2016-11-07    955  
d79651522e89c4f Robert Bragg                  2016-11-07    956  #define OACEC_SELECT_NOA	(0 << 19)
d79651522e89c4f Robert Bragg                  2016-11-07    957  #define OACEC_SELECT_PREV	(1 << 19)
d79651522e89c4f Robert Bragg                  2016-11-07    958  #define OACEC_SELECT_BOOLEAN	(2 << 19)
d79651522e89c4f Robert Bragg                  2016-11-07    959  
d79651522e89c4f Robert Bragg                  2016-11-07    960  /* CECX_1 */
d79651522e89c4f Robert Bragg                  2016-11-07    961  #define OACEC_MASK_MASK		    0xffff
d79651522e89c4f Robert Bragg                  2016-11-07    962  #define OACEC_CONSIDERATIONS_MASK   0xffff
d79651522e89c4f Robert Bragg                  2016-11-07    963  #define OACEC_CONSIDERATIONS_SHIFT  16
d79651522e89c4f Robert Bragg                  2016-11-07    964  
d79651522e89c4f Robert Bragg                  2016-11-07    965  #define OACEC0_0 _MMIO(0x2770)
d79651522e89c4f Robert Bragg                  2016-11-07    966  #define OACEC0_1 _MMIO(0x2774)
d79651522e89c4f Robert Bragg                  2016-11-07    967  #define OACEC1_0 _MMIO(0x2778)
d79651522e89c4f Robert Bragg                  2016-11-07    968  #define OACEC1_1 _MMIO(0x277c)
d79651522e89c4f Robert Bragg                  2016-11-07    969  #define OACEC2_0 _MMIO(0x2780)
d79651522e89c4f Robert Bragg                  2016-11-07    970  #define OACEC2_1 _MMIO(0x2784)
d79651522e89c4f Robert Bragg                  2016-11-07    971  #define OACEC3_0 _MMIO(0x2788)
d79651522e89c4f Robert Bragg                  2016-11-07    972  #define OACEC3_1 _MMIO(0x278c)
d79651522e89c4f Robert Bragg                  2016-11-07    973  #define OACEC4_0 _MMIO(0x2790)
d79651522e89c4f Robert Bragg                  2016-11-07    974  #define OACEC4_1 _MMIO(0x2794)
d79651522e89c4f Robert Bragg                  2016-11-07    975  #define OACEC5_0 _MMIO(0x2798)
d79651522e89c4f Robert Bragg                  2016-11-07    976  #define OACEC5_1 _MMIO(0x279c)
d79651522e89c4f Robert Bragg                  2016-11-07    977  #define OACEC6_0 _MMIO(0x27a0)
d79651522e89c4f Robert Bragg                  2016-11-07    978  #define OACEC6_1 _MMIO(0x27a4)
d79651522e89c4f Robert Bragg                  2016-11-07    979  #define OACEC7_0 _MMIO(0x27a8)
d79651522e89c4f Robert Bragg                  2016-11-07    980  #define OACEC7_1 _MMIO(0x27ac)
d79651522e89c4f Robert Bragg                  2016-11-07    981  
f89823c212246d0 Lionel Landwerlin             2017-08-03    982  /* OA perf counters */
f89823c212246d0 Lionel Landwerlin             2017-08-03    983  #define OA_PERFCNT1_LO      _MMIO(0x91B8)
f89823c212246d0 Lionel Landwerlin             2017-08-03    984  #define OA_PERFCNT1_HI      _MMIO(0x91BC)
f89823c212246d0 Lionel Landwerlin             2017-08-03    985  #define OA_PERFCNT2_LO      _MMIO(0x91C0)
f89823c212246d0 Lionel Landwerlin             2017-08-03    986  #define OA_PERFCNT2_HI      _MMIO(0x91C4)
95690a02fb5d963 Lionel Landwerlin             2017-11-10    987  #define OA_PERFCNT3_LO      _MMIO(0x91C8)
95690a02fb5d963 Lionel Landwerlin             2017-11-10    988  #define OA_PERFCNT3_HI      _MMIO(0x91CC)
95690a02fb5d963 Lionel Landwerlin             2017-11-10    989  #define OA_PERFCNT4_LO      _MMIO(0x91D8)
95690a02fb5d963 Lionel Landwerlin             2017-11-10    990  #define OA_PERFCNT4_HI      _MMIO(0x91DC)
f89823c212246d0 Lionel Landwerlin             2017-08-03    991  
f89823c212246d0 Lionel Landwerlin             2017-08-03    992  #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
f89823c212246d0 Lionel Landwerlin             2017-08-03    993  #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
f89823c212246d0 Lionel Landwerlin             2017-08-03    994  
f89823c212246d0 Lionel Landwerlin             2017-08-03    995  /* RPM unit config (Gen8+) */
f89823c212246d0 Lionel Landwerlin             2017-08-03    996  #define RPM_CONFIG0	    _MMIO(0x0D00)
dab91783338bd3d Lionel Landwerlin             2017-11-10    997  #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
dab91783338bd3d Lionel Landwerlin             2017-11-10    998  #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
dab91783338bd3d Lionel Landwerlin             2017-11-10    999  #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
dab91783338bd3d Lionel Landwerlin             2017-11-10   1000  #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	1
d775a7b1840ddc9 Paulo Zanoni                  2018-01-09   1001  #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
d775a7b1840ddc9 Paulo Zanoni                  2018-01-09   1002  #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
d775a7b1840ddc9 Paulo Zanoni                  2018-01-09   1003  #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
d775a7b1840ddc9 Paulo Zanoni                  2018-01-09   1004  #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
d775a7b1840ddc9 Paulo Zanoni                  2018-01-09   1005  #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
d775a7b1840ddc9 Paulo Zanoni                  2018-01-09   1006  #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	3
dab91783338bd3d Lionel Landwerlin             2017-11-10   1007  #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT	1
dab91783338bd3d Lionel Landwerlin             2017-11-10   1008  #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
dab91783338bd3d Lionel Landwerlin             2017-11-10   1009  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1010  #define RPM_CONFIG1	    _MMIO(0x0D04)
95690a02fb5d963 Lionel Landwerlin             2017-11-10   1011  #define  GEN10_GT_NOA_ENABLE  (1 << 9)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1012  
dab91783338bd3d Lionel Landwerlin             2017-11-10   1013  /* GPM unit config (Gen9+) */
dab91783338bd3d Lionel Landwerlin             2017-11-10   1014  #define CTC_MODE			_MMIO(0xA26C)
dab91783338bd3d Lionel Landwerlin             2017-11-10   1015  #define  CTC_SOURCE_PARAMETER_MASK 1
dab91783338bd3d Lionel Landwerlin             2017-11-10   1016  #define  CTC_SOURCE_CRYSTAL_CLOCK	0
dab91783338bd3d Lionel Landwerlin             2017-11-10   1017  #define  CTC_SOURCE_DIVIDE_LOGIC	1
dab91783338bd3d Lionel Landwerlin             2017-11-10   1018  #define  CTC_SHIFT_PARAMETER_SHIFT	1
dab91783338bd3d Lionel Landwerlin             2017-11-10   1019  #define  CTC_SHIFT_PARAMETER_MASK	(0x3 << CTC_SHIFT_PARAMETER_SHIFT)
dab91783338bd3d Lionel Landwerlin             2017-11-10   1020  
5888576b0b5feda Lionel Landwerlin             2017-11-10   1021  /* RCP unit config (Gen8+) */
5888576b0b5feda Lionel Landwerlin             2017-11-10   1022  #define RCP_CONFIG	    _MMIO(0x0D08)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1023  
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1024  /* NOA (HSW) */
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1025  #define HSW_MBVID2_NOA0		_MMIO(0x9E80)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1026  #define HSW_MBVID2_NOA1		_MMIO(0x9E84)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1027  #define HSW_MBVID2_NOA2		_MMIO(0x9E88)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1028  #define HSW_MBVID2_NOA3		_MMIO(0x9E8C)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1029  #define HSW_MBVID2_NOA4		_MMIO(0x9E90)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1030  #define HSW_MBVID2_NOA5		_MMIO(0x9E94)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1031  #define HSW_MBVID2_NOA6		_MMIO(0x9E98)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1032  #define HSW_MBVID2_NOA7		_MMIO(0x9E9C)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1033  #define HSW_MBVID2_NOA8		_MMIO(0x9EA0)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1034  #define HSW_MBVID2_NOA9		_MMIO(0x9EA4)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1035  
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1036  #define HSW_MBVID2_MISR0	_MMIO(0x9EC0)
a54b19f17746b95 Lionel Landwerlin             2017-11-10   1037  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1038  /* NOA (Gen8+) */
f89823c212246d0 Lionel Landwerlin             2017-08-03   1039  #define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1040  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1041  #define MICRO_BP0_0	    _MMIO(0x9800)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1042  #define MICRO_BP0_2	    _MMIO(0x9804)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1043  #define MICRO_BP0_1	    _MMIO(0x9808)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1044  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1045  #define MICRO_BP1_0	    _MMIO(0x980C)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1046  #define MICRO_BP1_2	    _MMIO(0x9810)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1047  #define MICRO_BP1_1	    _MMIO(0x9814)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1048  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1049  #define MICRO_BP2_0	    _MMIO(0x9818)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1050  #define MICRO_BP2_2	    _MMIO(0x981C)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1051  #define MICRO_BP2_1	    _MMIO(0x9820)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1052  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1053  #define MICRO_BP3_0	    _MMIO(0x9824)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1054  #define MICRO_BP3_2	    _MMIO(0x9828)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1055  #define MICRO_BP3_1	    _MMIO(0x982C)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1056  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1057  #define MICRO_BP_TRIGGER		_MMIO(0x9830)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1058  #define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1059  #define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1060  #define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1061  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1062  #define GDT_CHICKEN_BITS    _MMIO(0x9840)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1063  #define   GT_NOA_ENABLE	    0x00000080
f89823c212246d0 Lionel Landwerlin             2017-08-03   1064  
f89823c212246d0 Lionel Landwerlin             2017-08-03   1065  #define NOA_DATA	    _MMIO(0x986C)
f89823c212246d0 Lionel Landwerlin             2017-08-03   1066  #define NOA_WRITE	    _MMIO(0x9888)
bf210f6c9e6fd8d Lionel Landwerlin             2019-06-02   1067  #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
180b813ced1d134 Kenneth Graunke               2014-03-25   1068  
220375aa12c9574 Brad Volkin                   2014-02-18   1069  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
220375aa12c9574 Brad Volkin                   2014-02-18   1070  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1071  #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
220375aa12c9574 Brad Volkin                   2014-02-18   1072  
5947de9b46d472f Brad Volkin                   2014-02-18   1073  /*
dc96e9b8e37641d Chris Wilson                  2010-10-01   1074   * Reset registers
dc96e9b8e37641d Chris Wilson                  2010-10-01   1075   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1076  #define DEBUG_RESET_I830		_MMIO(0x6070)
dc96e9b8e37641d Chris Wilson                  2010-10-01   1077  #define  DEBUG_RESET_FULL		(1 << 7)
dc96e9b8e37641d Chris Wilson                  2010-10-01   1078  #define  DEBUG_RESET_RENDER		(1 << 8)
dc96e9b8e37641d Chris Wilson                  2010-10-01   1079  #define  DEBUG_RESET_DISPLAY		(1 << 9)
dc96e9b8e37641d Chris Wilson                  2010-10-01   1080  
57f350b6722f956 Jesse Barnes                  2012-03-28   1081  /*
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1082   * IOSF sideband
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1083   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1084  #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1085  #define   IOSF_DEVFN_SHIFT			24
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1086  #define   IOSF_OPCODE_SHIFT			16
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1087  #define   IOSF_PORT_SHIFT			8
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1088  #define   IOSF_BYTE_ENABLES_SHIFT		4
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1089  #define   IOSF_BAR_SHIFT			1
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1090  #define   IOSF_SB_BUSY				(1 << 0)
4688d45f97f2154 Jani Nikula                   2016-02-04   1091  #define   IOSF_PORT_BUNIT			0x03
4688d45f97f2154 Jani Nikula                   2016-02-04   1092  #define   IOSF_PORT_PUNIT			0x04
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1093  #define   IOSF_PORT_NC				0x11
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1094  #define   IOSF_PORT_DPIO			0x12
e9f882a3f1e4ffa Jani Nikula                   2013-08-27   1095  #define   IOSF_PORT_GPIO_NC			0x13
e9f882a3f1e4ffa Jani Nikula                   2013-08-27   1096  #define   IOSF_PORT_CCK				0x14
4688d45f97f2154 Jani Nikula                   2016-02-04   1097  #define   IOSF_PORT_DPIO_2			0x1a
4688d45f97f2154 Jani Nikula                   2016-02-04   1098  #define   IOSF_PORT_FLISDSI			0x1b
dfb19ed20c32261 Deepak M                      2016-02-04   1099  #define   IOSF_PORT_GPIO_SC			0x48
dfb19ed20c32261 Deepak M                      2016-02-04   1100  #define   IOSF_PORT_GPIO_SUS			0xa8
4688d45f97f2154 Jani Nikula                   2016-02-04   1101  #define   IOSF_PORT_CCU				0xa9
7071af97c6316d2 Jani Nikula                   2016-03-18   1102  #define   CHV_IOSF_PORT_GPIO_N			0x13
7071af97c6316d2 Jani Nikula                   2016-03-18   1103  #define   CHV_IOSF_PORT_GPIO_SE			0x48
7071af97c6316d2 Jani Nikula                   2016-03-18   1104  #define   CHV_IOSF_PORT_GPIO_E			0xa8
7071af97c6316d2 Jani Nikula                   2016-03-18   1105  #define   CHV_IOSF_PORT_GPIO_SW			0xb2
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1106  #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1107  #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1108  
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1109  /* See configdb bunit SB addr map */
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1110  #define BUNIT_REG_BISOC				0x11
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1111  
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1112  /* PUNIT_REG_*SSPM0 */
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1113  #define   _SSPM0_SSC(val)			((val) << 0)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1114  #define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1115  #define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1116  #define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1117  #define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1118  #define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1119  #define   _SSPM0_SSS(val)			((val) << 24)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1120  #define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1121  #define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1122  #define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1123  #define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1124  #define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1125  
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1126  /* PUNIT_REG_*SSPM1 */
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1127  #define   SSPM1_FREQSTAT_SHIFT			24
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1128  #define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1129  #define   SSPM1_FREQGUAR_SHIFT			8
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1130  #define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1131  #define   SSPM1_FREQ_SHIFT			0
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1132  #define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1133  
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1134  #define PUNIT_REG_VEDSSPM0			0x32
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1135  #define PUNIT_REG_VEDSSPM1			0x33
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1136  
c11b813f53c98e3 Ville Syrjälä                 2018-11-29   1137  #define PUNIT_REG_DSPSSPM			0x36
383c5a6a4682f68 Ville Syrjälä                 2014-06-28   1138  #define   DSPFREQSTAT_SHIFT_CHV			24
383c5a6a4682f68 Ville Syrjälä                 2014-06-28   1139  #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
383c5a6a4682f68 Ville Syrjälä                 2014-06-28   1140  #define   DSPFREQGUAR_SHIFT_CHV			8
383c5a6a4682f68 Ville Syrjälä                 2014-06-28   1141  #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1142  #define   DSPFREQSTAT_SHIFT			30
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1143  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1144  #define   DSPFREQGUAR_SHIFT			14
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1145  #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
cfb41411fce52a8 Ville Syrjälä                 2015-03-05   1146  #define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
cfb41411fce52a8 Ville Syrjälä                 2015-03-05   1147  #define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
cfb41411fce52a8 Ville Syrjälä                 2015-03-05   1148  #define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
26972b0a80091cc Ville Syrjälä                 2014-06-28   1149  #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1150  #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1151  #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1152  #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1153  #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1154  #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1155  #define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1156  #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1157  #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1158  #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1159  #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
26972b0a80091cc Ville Syrjälä                 2014-06-28   1160  #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
a30180a5a349709 Imre Deak                     2014-03-04   1161  
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1162  #define PUNIT_REG_ISPSSPM0			0x39
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1163  #define PUNIT_REG_ISPSSPM1			0x3a
5e0b6697651b3e6 Ville Syrjälä                 2018-11-29   1164  
c3fdb9d8fc0a92a Jani Nikula                   2017-08-10   1165  /*
438b8dc457e7274 Imre Deak                     2017-07-11   1166   * i915_power_well_id:
438b8dc457e7274 Imre Deak                     2017-07-11   1167   *
4739a9d2438bbc8 Imre Deak                     2018-08-06   1168   * IDs used to look up power wells. Power wells accessed directly bypassing
4739a9d2438bbc8 Imre Deak                     2018-08-06   1169   * the power domains framework must be assigned a unique ID. The rest of power
4739a9d2438bbc8 Imre Deak                     2018-08-06   1170   * wells must be assigned DISP_PW_ID_NONE.
438b8dc457e7274 Imre Deak                     2017-07-11   1171   */
438b8dc457e7274 Imre Deak                     2017-07-11   1172  enum i915_power_well_id {
4739a9d2438bbc8 Imre Deak                     2018-08-06   1173  	DISP_PW_ID_NONE,
4739a9d2438bbc8 Imre Deak                     2018-08-06   1174  
2183b49933fce40 Imre Deak                     2018-08-06   1175  	VLV_DISP_PW_DISP2D,
2183b49933fce40 Imre Deak                     2018-08-06   1176  	BXT_DISP_PW_DPIO_CMN_A,
2183b49933fce40 Imre Deak                     2018-08-06   1177  	VLV_DISP_PW_DPIO_CMN_BC,
2183b49933fce40 Imre Deak                     2018-08-06   1178  	GLK_DISP_PW_DPIO_CMN_C,
2183b49933fce40 Imre Deak                     2018-08-06   1179  	CHV_DISP_PW_DPIO_CMN_D,
4739a9d2438bbc8 Imre Deak                     2018-08-06   1180  	HSW_DISP_PW_GLOBAL,
4739a9d2438bbc8 Imre Deak                     2018-08-06   1181  	SKL_DISP_PW_MISC_IO,
4739a9d2438bbc8 Imre Deak                     2018-08-06   1182  	SKL_DISP_PW_1,
94dd5138c5ed02d Satheeshakrishna M            2015-02-04   1183  	SKL_DISP_PW_2,
94dd5138c5ed02d Satheeshakrishna M            2015-02-04   1184  };
94dd5138c5ed02d Satheeshakrishna M            2015-02-04   1185  
02f4c9e02a021c5 Chon Ming Lee                 2013-10-03   1186  #define PUNIT_REG_PWRGT_CTRL			0x60
02f4c9e02a021c5 Chon Ming Lee                 2013-10-03   1187  #define PUNIT_REG_PWRGT_STATUS			0x61
d13dd05a1f20262 Imre Deak                     2018-08-06   1188  #define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
d13dd05a1f20262 Imre Deak                     2018-08-06   1189  #define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
d13dd05a1f20262 Imre Deak                     2018-08-06   1190  #define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
d13dd05a1f20262 Imre Deak                     2018-08-06   1191  #define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
d13dd05a1f20262 Imre Deak                     2018-08-06   1192  #define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
d13dd05a1f20262 Imre Deak                     2018-08-06   1193  
d13dd05a1f20262 Imre Deak                     2018-08-06   1194  #define PUNIT_PWGT_IDX_RENDER			0
d13dd05a1f20262 Imre Deak                     2018-08-06   1195  #define PUNIT_PWGT_IDX_MEDIA			1
d13dd05a1f20262 Imre Deak                     2018-08-06   1196  #define PUNIT_PWGT_IDX_DISP2D			3
d13dd05a1f20262 Imre Deak                     2018-08-06   1197  #define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
d13dd05a1f20262 Imre Deak                     2018-08-06   1198  #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
d13dd05a1f20262 Imre Deak                     2018-08-06   1199  #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
d13dd05a1f20262 Imre Deak                     2018-08-06   1200  #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
d13dd05a1f20262 Imre Deak                     2018-08-06   1201  #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
d13dd05a1f20262 Imre Deak                     2018-08-06   1202  #define PUNIT_PWGT_IDX_DPIO_RX0			10
d13dd05a1f20262 Imre Deak                     2018-08-06   1203  #define PUNIT_PWGT_IDX_DPIO_RX1			11
d13dd05a1f20262 Imre Deak                     2018-08-06   1204  #define PUNIT_PWGT_IDX_DPIO_CMN_D		12
02f4c9e02a021c5 Chon Ming Lee                 2013-10-03   1205  
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1206  #define PUNIT_REG_GPU_LFM			0xd3
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1207  #define PUNIT_REG_GPU_FREQ_REQ			0xd4
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1208  #define PUNIT_REG_GPU_FREQ_STS			0xd8
c8e9627d2ad9efe Ville Syrjälä                 2014-11-07   1209  #define   GPLLENABLE				(1 << 4)
e8474409d7ab6da Ville Syrjälä                 2013-06-26   1210  #define   GENFREQSTATUS				(1 << 0)
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1211  #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
31685c258e0b0ad Deepak S                      2014-07-03   1212  #define PUNIT_REG_CZ_TIMESTAMP			0xce
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1213  
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1214  #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1215  #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1216  
095acd5f8739aa8 Deepak S                      2015-01-17   1217  #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
095acd5f8739aa8 Deepak S                      2015-01-17   1218  #define FB_GFX_FREQ_FUSE_MASK			0xff
095acd5f8739aa8 Deepak S                      2015-01-17   1219  #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
095acd5f8739aa8 Deepak S                      2015-01-17   1220  #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
095acd5f8739aa8 Deepak S                      2015-01-17   1221  #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
095acd5f8739aa8 Deepak S                      2015-01-17   1222  
095acd5f8739aa8 Deepak S                      2015-01-17   1223  #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
095acd5f8739aa8 Deepak S                      2015-01-17   1224  #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
095acd5f8739aa8 Deepak S                      2015-01-17   1225  
fc1ac8dee1fe3d3 Ville Syrjälä                 2015-03-05   1226  #define PUNIT_REG_DDR_SETUP2			0x139
fc1ac8dee1fe3d3 Ville Syrjälä                 2015-03-05   1227  #define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
fc1ac8dee1fe3d3 Ville Syrjälä                 2015-03-05   1228  #define   FORCE_DDR_LOW_FREQ			(1 << 1)
fc1ac8dee1fe3d3 Ville Syrjälä                 2015-03-05   1229  #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
fc1ac8dee1fe3d3 Ville Syrjälä                 2015-03-05   1230  
2b6b3a09915f852 Deepak S                      2014-05-27   1231  #define PUNIT_GPU_STATUS_REG			0xdb
2b6b3a09915f852 Deepak S                      2014-05-27   1232  #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
2b6b3a09915f852 Deepak S                      2014-05-27   1233  #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
2b6b3a09915f852 Deepak S                      2014-05-27   1234  #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
2b6b3a09915f852 Deepak S                      2014-05-27   1235  #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
2b6b3a09915f852 Deepak S                      2014-05-27   1236  
2b6b3a09915f852 Deepak S                      2014-05-27   1237  #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
2b6b3a09915f852 Deepak S                      2014-05-27   1238  #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
2b6b3a09915f852 Deepak S                      2014-05-27   1239  #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
2b6b3a09915f852 Deepak S                      2014-05-27   1240  
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1241  #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1242  #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1243  #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1244  #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1245  #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1246  #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1247  #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1248  #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1249  #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1250  #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1251  
3ef62342bd854ff Deepak S                      2015-04-29   1252  #define VLV_TURBO_SOC_OVERRIDE		0x04
3ef62342bd854ff Deepak S                      2015-04-29   1253  #define   VLV_OVERRIDE_EN		1
3ef62342bd854ff Deepak S                      2015-04-29   1254  #define   VLV_SOC_TDP_EN		(1 << 1)
3ef62342bd854ff Deepak S                      2015-04-29   1255  #define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
3ef62342bd854ff Deepak S                      2015-04-29   1256  #define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
3ef62342bd854ff Deepak S                      2015-04-29   1257  
be4fc046bed35f7 ymohanma                      2013-08-27   1258  /* vlv2 north clock has */
24eb2d599b6a2bf Chon Ming Lee                 2013-09-27   1259  #define CCK_FUSE_REG				0x8
24eb2d599b6a2bf Chon Ming Lee                 2013-09-27   1260  #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
be4fc046bed35f7 ymohanma                      2013-08-27   1261  #define CCK_REG_DSI_PLL_FUSE			0x44
be4fc046bed35f7 ymohanma                      2013-08-27   1262  #define CCK_REG_DSI_PLL_CONTROL			0x48
be4fc046bed35f7 ymohanma                      2013-08-27   1263  #define  DSI_PLL_VCO_EN				(1 << 31)
be4fc046bed35f7 ymohanma                      2013-08-27   1264  #define  DSI_PLL_LDO_GATE			(1 << 30)
be4fc046bed35f7 ymohanma                      2013-08-27   1265  #define  DSI_PLL_P1_POST_DIV_SHIFT		17
be4fc046bed35f7 ymohanma                      2013-08-27   1266  #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
be4fc046bed35f7 ymohanma                      2013-08-27   1267  #define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
be4fc046bed35f7 ymohanma                      2013-08-27   1268  #define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
be4fc046bed35f7 ymohanma                      2013-08-27   1269  #define  DSI_PLL_MUX_MASK			(3 << 9)
be4fc046bed35f7 ymohanma                      2013-08-27   1270  #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
be4fc046bed35f7 ymohanma                      2013-08-27   1271  #define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
be4fc046bed35f7 ymohanma                      2013-08-27   1272  #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
be4fc046bed35f7 ymohanma                      2013-08-27   1273  #define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
be4fc046bed35f7 ymohanma                      2013-08-27   1274  #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
be4fc046bed35f7 ymohanma                      2013-08-27   1275  #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
be4fc046bed35f7 ymohanma                      2013-08-27   1276  #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
be4fc046bed35f7 ymohanma                      2013-08-27   1277  #define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
be4fc046bed35f7 ymohanma                      2013-08-27   1278  #define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
be4fc046bed35f7 ymohanma                      2013-08-27   1279  #define  DSI_PLL_LOCK				(1 << 0)
be4fc046bed35f7 ymohanma                      2013-08-27   1280  #define CCK_REG_DSI_PLL_DIVIDER			0x4c
be4fc046bed35f7 ymohanma                      2013-08-27   1281  #define  DSI_PLL_LFSR				(1 << 31)
be4fc046bed35f7 ymohanma                      2013-08-27   1282  #define  DSI_PLL_FRACTION_EN			(1 << 30)
be4fc046bed35f7 ymohanma                      2013-08-27   1283  #define  DSI_PLL_FRAC_COUNTER_SHIFT		27
be4fc046bed35f7 ymohanma                      2013-08-27   1284  #define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
be4fc046bed35f7 ymohanma                      2013-08-27   1285  #define  DSI_PLL_USYNC_CNT_SHIFT		18
be4fc046bed35f7 ymohanma                      2013-08-27   1286  #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
be4fc046bed35f7 ymohanma                      2013-08-27   1287  #define  DSI_PLL_N1_DIV_SHIFT			16
be4fc046bed35f7 ymohanma                      2013-08-27   1288  #define  DSI_PLL_N1_DIV_MASK			(3 << 16)
be4fc046bed35f7 ymohanma                      2013-08-27   1289  #define  DSI_PLL_M1_DIV_SHIFT			0
be4fc046bed35f7 ymohanma                      2013-08-27   1290  #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
bfa7df01a092e92 Ville Syrjälä                 2015-09-24   1291  #define CCK_CZ_CLOCK_CONTROL			0x62
c30fec656d1336a Ville Syrjälä                 2016-03-04   1292  #define CCK_GPLL_CLOCK_CONTROL			0x67
30a970c6a6ff734 Jesse Barnes                  2013-11-04   1293  #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
35d38d1f17b853a Ville Syrjälä                 2016-03-02   1294  #define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
87d5d2593299cb8 Vandana Kannan                2015-09-24   1295  #define  CCK_TRUNK_FORCE_ON			(1 << 17)
87d5d2593299cb8 Vandana Kannan                2015-09-24   1296  #define  CCK_TRUNK_FORCE_OFF			(1 << 16)
87d5d2593299cb8 Vandana Kannan                2015-09-24   1297  #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
87d5d2593299cb8 Vandana Kannan                2015-09-24   1298  #define  CCK_FREQUENCY_STATUS_SHIFT		8
87d5d2593299cb8 Vandana Kannan                2015-09-24   1299  #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
be4fc046bed35f7 ymohanma                      2013-08-27   1300  
f38861b814b530f Ander Conselvan de Oliveira   2016-10-06   1301  /* DPIO registers */
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1302  #define DPIO_DEVFN			0
5a09ae9fd509d7d Jani Nikula                   2013-05-22   1303  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1304  #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
57f350b6722f956 Jesse Barnes                  2012-03-28   1305  #define  DPIO_MODSEL1			(1 << 3) /* if ref clk b == 27 */
57f350b6722f956 Jesse Barnes                  2012-03-28   1306  #define  DPIO_MODSEL0			(1 << 2) /* if ref clk a == 27 */
57f350b6722f956 Jesse Barnes                  2012-03-28   1307  #define  DPIO_SFR_BYPASS		(1 << 1)
40e9cf649a88abe Jesse Barnes                  2013-10-03   1308  #define  DPIO_CMNRST			(1 << 0)
57f350b6722f956 Jesse Barnes                  2012-03-28   1309  
e4607fcfb1cd5d8 Chon Ming Lee                 2013-11-06   1310  #define DPIO_PHY(pipe)			((pipe) >> 1)
e4607fcfb1cd5d8 Chon Ming Lee                 2013-11-06   1311  #define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])
e4607fcfb1cd5d8 Chon Ming Lee                 2013-11-06   1312  
598fac6bf8299ed Daniel Vetter                 2013-04-18   1313  /*
598fac6bf8299ed Daniel Vetter                 2013-04-18   1314   * Per pipe/PLL DPIO regs
598fac6bf8299ed Daniel Vetter                 2013-04-18   1315   */
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1316  #define _VLV_PLL_DW3_CH0		0x800c
57f350b6722f956 Jesse Barnes                  2012-03-28   1317  #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
598fac6bf8299ed Daniel Vetter                 2013-04-18   1318  #define   DPIO_POST_DIV_DAC		0
598fac6bf8299ed Daniel Vetter                 2013-04-18   1319  #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
598fac6bf8299ed Daniel Vetter                 2013-04-18   1320  #define   DPIO_POST_DIV_LVDS1		2
598fac6bf8299ed Daniel Vetter                 2013-04-18   1321  #define   DPIO_POST_DIV_LVDS2		3
57f350b6722f956 Jesse Barnes                  2012-03-28   1322  #define   DPIO_K_SHIFT			(24) /* 4 bits */
57f350b6722f956 Jesse Barnes                  2012-03-28   1323  #define   DPIO_P1_SHIFT			(21) /* 3 bits */
57f350b6722f956 Jesse Barnes                  2012-03-28   1324  #define   DPIO_P2_SHIFT			(16) /* 5 bits */
57f350b6722f956 Jesse Barnes                  2012-03-28   1325  #define   DPIO_N_SHIFT			(12) /* 4 bits */
57f350b6722f956 Jesse Barnes                  2012-03-28   1326  #define   DPIO_ENABLE_CALIBRATION	(1 << 11)
57f350b6722f956 Jesse Barnes                  2012-03-28   1327  #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
57f350b6722f956 Jesse Barnes                  2012-03-28   1328  #define   DPIO_M2DIV_MASK		0xff
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1329  #define _VLV_PLL_DW3_CH1		0x802c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1330  #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
57f350b6722f956 Jesse Barnes                  2012-03-28   1331  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1332  #define _VLV_PLL_DW5_CH0		0x8014
57f350b6722f956 Jesse Barnes                  2012-03-28   1333  #define   DPIO_REFSEL_OVERRIDE		27
57f350b6722f956 Jesse Barnes                  2012-03-28   1334  #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
57f350b6722f956 Jesse Barnes                  2012-03-28   1335  #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
57f350b6722f956 Jesse Barnes                  2012-03-28   1336  #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
b56747aace48a26 Vijay Purushothaman           2012-09-27   1337  #define   DPIO_PLL_REFCLK_SEL_MASK	3
57f350b6722f956 Jesse Barnes                  2012-03-28   1338  #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
57f350b6722f956 Jesse Barnes                  2012-03-28   1339  #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1340  #define _VLV_PLL_DW5_CH1		0x8034
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1341  #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
57f350b6722f956 Jesse Barnes                  2012-03-28   1342  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1343  #define _VLV_PLL_DW7_CH0		0x801c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1344  #define _VLV_PLL_DW7_CH1		0x803c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1345  #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
57f350b6722f956 Jesse Barnes                  2012-03-28   1346  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1347  #define _VLV_PLL_DW8_CH0		0x8040
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1348  #define _VLV_PLL_DW8_CH1		0x8060
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1349  #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1350  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1351  #define VLV_PLL_DW9_BCAST		0xc044
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1352  #define _VLV_PLL_DW9_CH0		0x8044
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1353  #define _VLV_PLL_DW9_CH1		0x8064
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1354  #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1355  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1356  #define _VLV_PLL_DW10_CH0		0x8048
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1357  #define _VLV_PLL_DW10_CH1		0x8068
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1358  #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1359  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1360  #define _VLV_PLL_DW11_CH0		0x804c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1361  #define _VLV_PLL_DW11_CH1		0x806c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1362  #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
57f350b6722f956 Jesse Barnes                  2012-03-28   1363  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1364  /* Spec for ref block start counts at DW10 */
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1365  #define VLV_REF_DW13			0x80ac
598fac6bf8299ed Daniel Vetter                 2013-04-18   1366  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1367  #define VLV_CMN_DW0			0x8100
dc96e9b8e37641d Chris Wilson                  2010-10-01   1368  
598fac6bf8299ed Daniel Vetter                 2013-04-18   1369  /*
598fac6bf8299ed Daniel Vetter                 2013-04-18   1370   * Per DDI channel DPIO regs
598fac6bf8299ed Daniel Vetter                 2013-04-18   1371   */
598fac6bf8299ed Daniel Vetter                 2013-04-18   1372  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1373  #define _VLV_PCS_DW0_CH0		0x8200
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1374  #define _VLV_PCS_DW0_CH1		0x8400
598fac6bf8299ed Daniel Vetter                 2013-04-18   1375  #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1376  #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1377  #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1378  #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1379  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1380  
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1381  #define _VLV_PCS01_DW0_CH0		0x200
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1382  #define _VLV_PCS23_DW0_CH0		0x400
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1383  #define _VLV_PCS01_DW0_CH1		0x2600
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1384  #define _VLV_PCS23_DW0_CH1		0x2800
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1385  #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1386  #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1387  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1388  #define _VLV_PCS_DW1_CH0		0x8204
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1389  #define _VLV_PCS_DW1_CH1		0x8404
d2152b2524a96e6 Ville Syrjälä                 2014-04-28   1390  #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1391  #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1392  #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1393  #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
598fac6bf8299ed Daniel Vetter                 2013-04-18   1394  #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1395  #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1396  
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1397  #define _VLV_PCS01_DW1_CH0		0x204
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1398  #define _VLV_PCS23_DW1_CH0		0x404
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1399  #define _VLV_PCS01_DW1_CH1		0x2604
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1400  #define _VLV_PCS23_DW1_CH1		0x2804
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1401  #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1402  #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
97fd4d5c81af797 Ville Syrjälä                 2014-04-09   1403  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1404  #define _VLV_PCS_DW8_CH0		0x8220
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1405  #define _VLV_PCS_DW8_CH1		0x8420
9197c88bf946cf7 Ville Syrjälä                 2014-04-09   1406  #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
9197c88bf946cf7 Ville Syrjälä                 2014-04-09   1407  #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1408  #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1409  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1410  #define _VLV_PCS01_DW8_CH0		0x0220
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1411  #define _VLV_PCS23_DW8_CH0		0x0420
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1412  #define _VLV_PCS01_DW8_CH1		0x2620
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1413  #define _VLV_PCS23_DW8_CH1		0x2820
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1414  #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1415  #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1416  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1417  #define _VLV_PCS_DW9_CH0		0x8224
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1418  #define _VLV_PCS_DW9_CH1		0x8424
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1419  #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1420  #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1421  #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1422  #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1423  #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1424  #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1425  #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1426  
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1427  #define _VLV_PCS01_DW9_CH0		0x224
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1428  #define _VLV_PCS23_DW9_CH0		0x424
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1429  #define _VLV_PCS01_DW9_CH1		0x2624
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1430  #define _VLV_PCS23_DW9_CH1		0x2824
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1431  #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1432  #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1433  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1434  #define _CHV_PCS_DW10_CH0		0x8228
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1435  #define _CHV_PCS_DW10_CH1		0x8428
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1436  #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1437  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1438  #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1439  #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1440  #define   DPIO_PCS_TX2DEEMP_6P0		(2 << 24)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1441  #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1442  #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
a02ef3c7193c942 Ville Syrjälä                 2014-08-18   1443  #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1444  #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1445  
1966e59ec107559 Ville Syrjälä                 2014-04-09   1446  #define _VLV_PCS01_DW10_CH0		0x0228
1966e59ec107559 Ville Syrjälä                 2014-04-09   1447  #define _VLV_PCS23_DW10_CH0		0x0428
1966e59ec107559 Ville Syrjälä                 2014-04-09   1448  #define _VLV_PCS01_DW10_CH1		0x2628
1966e59ec107559 Ville Syrjälä                 2014-04-09   1449  #define _VLV_PCS23_DW10_CH1		0x2828
1966e59ec107559 Ville Syrjälä                 2014-04-09   1450  #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1966e59ec107559 Ville Syrjälä                 2014-04-09   1451  #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1966e59ec107559 Ville Syrjälä                 2014-04-09   1452  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1453  #define _VLV_PCS_DW11_CH0		0x822c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1454  #define _VLV_PCS_DW11_CH1		0x842c
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1455  #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1456  #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1457  #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1458  #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1459  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1460  
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1461  #define _VLV_PCS01_DW11_CH0		0x022c
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1462  #define _VLV_PCS23_DW11_CH0		0x042c
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1463  #define _VLV_PCS01_DW11_CH1		0x262c
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1464  #define _VLV_PCS23_DW11_CH1		0x282c
142d2eca356af67 Ville Syrjälä                 2014-10-16   1465  #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
142d2eca356af67 Ville Syrjälä                 2014-10-16   1466  #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
570e2a747bc06cd Ville Syrjälä                 2014-08-18   1467  
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1468  #define _VLV_PCS01_DW12_CH0		0x0230
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1469  #define _VLV_PCS23_DW12_CH0		0x0430
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1470  #define _VLV_PCS01_DW12_CH1		0x2630
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1471  #define _VLV_PCS23_DW12_CH1		0x2830
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1472  #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1473  #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1474  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1475  #define _VLV_PCS_DW12_CH0		0x8230
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1476  #define _VLV_PCS_DW12_CH1		0x8430
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1477  #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1478  #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1479  #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1480  #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
2e523e98bb59395 Ville Syrjälä                 2015-04-10   1481  #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1482  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1483  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1484  #define _VLV_PCS_DW14_CH0		0x8238
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1485  #define _VLV_PCS_DW14_CH1		0x8438
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1486  #define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1487  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1488  #define _VLV_PCS_DW23_CH0		0x825c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1489  #define _VLV_PCS_DW23_CH1		0x845c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1490  #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1491  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1492  #define _VLV_TX_DW2_CH0			0x8288
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1493  #define _VLV_TX_DW2_CH1			0x8488
1fb44505f6c5477 Ville Syrjälä                 2014-06-28   1494  #define   DPIO_SWING_MARGIN000_SHIFT	16
1fb44505f6c5477 Ville Syrjälä                 2014-06-28   1495  #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1496  #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1497  #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1498  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1499  #define _VLV_TX_DW3_CH0			0x828c
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1500  #define _VLV_TX_DW3_CH1			0x848c
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1501  /* The following bit for CHV phy */
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1502  #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
1fb44505f6c5477 Ville Syrjälä                 2014-06-28   1503  #define   DPIO_SWING_MARGIN101_SHIFT	16
1fb44505f6c5477 Ville Syrjälä                 2014-06-28   1504  #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1505  #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1506  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1507  #define _VLV_TX_DW4_CH0			0x8290
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1508  #define _VLV_TX_DW4_CH1			0x8490
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1509  #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1510  #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1fb44505f6c5477 Ville Syrjälä                 2014-06-28   1511  #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
1fb44505f6c5477 Ville Syrjälä                 2014-06-28   1512  #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1513  #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1514  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1515  #define _VLV_TX3_DW4_CH0		0x690
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1516  #define _VLV_TX3_DW4_CH1		0x2a90
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1517  #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1518  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1519  #define _VLV_TX_DW5_CH0			0x8294
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1520  #define _VLV_TX_DW5_CH1			0x8494
598fac6bf8299ed Daniel Vetter                 2013-04-18   1521  #define   DPIO_TX_OCALINIT_EN		(1 << 31)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1522  #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1523  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1524  #define _VLV_TX_DW11_CH0		0x82ac
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1525  #define _VLV_TX_DW11_CH1		0x84ac
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1526  #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1527  
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1528  #define _VLV_TX_DW14_CH0		0x82b8
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1529  #define _VLV_TX_DW14_CH1		0x84b8
ab3c759a0461528 Chon Ming Lee                 2013-11-07   1530  #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
b56747aace48a26 Vijay Purushothaman           2012-09-27   1531  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1532  /* CHV dpPhy registers */
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1533  #define _CHV_PLL_DW0_CH0		0x8000
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1534  #define _CHV_PLL_DW0_CH1		0x8180
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1535  #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1536  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1537  #define _CHV_PLL_DW1_CH0		0x8004
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1538  #define _CHV_PLL_DW1_CH1		0x8184
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1539  #define   DPIO_CHV_N_DIV_SHIFT		8
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1540  #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1541  #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1542  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1543  #define _CHV_PLL_DW2_CH0		0x8008
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1544  #define _CHV_PLL_DW2_CH1		0x8188
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1545  #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1546  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1547  #define _CHV_PLL_DW3_CH0		0x800c
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1548  #define _CHV_PLL_DW3_CH1		0x818c
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1549  #define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1550  #define  DPIO_CHV_FIRST_MOD		(0 << 8)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1551  #define  DPIO_CHV_SECOND_MOD		(1 << 8)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1552  #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
a945ce7e4eeb9c6 Vijay Purushothaman           2015-03-05   1553  #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1554  #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1555  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1556  #define _CHV_PLL_DW6_CH0		0x8018
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1557  #define _CHV_PLL_DW6_CH1		0x8198
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1558  #define   DPIO_CHV_GAIN_CTRL_SHIFT	16
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1559  #define	  DPIO_CHV_INT_COEFF_SHIFT	8
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1560  #define   DPIO_CHV_PROP_COEFF_SHIFT	0
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1561  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1562  
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1563  #define _CHV_PLL_DW8_CH0		0x8020
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1564  #define _CHV_PLL_DW8_CH1		0x81A0
9cbe40c15a753e0 Vijay Purushothaman           2015-03-05   1565  #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
9cbe40c15a753e0 Vijay Purushothaman           2015-03-05   1566  #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1567  #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1568  
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1569  #define _CHV_PLL_DW9_CH0		0x8024
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1570  #define _CHV_PLL_DW9_CH1		0x81A4
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1571  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
de3a0fde9afe551 Vijay Purushothaman           2015-03-05   1572  #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1573  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1574  #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
d3eee4baa0cb34e Vijay Purushothaman           2015-02-16   1575  
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1576  #define _CHV_CMN_DW0_CH0               0x8100
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1577  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1578  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1579  #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1580  #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1581  
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1582  #define _CHV_CMN_DW5_CH0               0x8114
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1583  #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1584  #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1585  #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1586  #define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1587  #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1588  #define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1589  #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1590  #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1591  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1592  #define _CHV_CMN_DW13_CH0		0x8134
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1593  #define _CHV_CMN_DW0_CH1		0x8080
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1594  #define   DPIO_CHV_S1_DIV_SHIFT		21
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1595  #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1596  #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1597  #define   DPIO_CHV_K_DIV_SHIFT		4
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1598  #define   DPIO_PLL_FREQLOCK		(1 << 1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1599  #define   DPIO_PLL_LOCK			(1 << 0)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1600  #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1601  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1602  #define _CHV_CMN_DW14_CH0		0x8138
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1603  #define _CHV_CMN_DW1_CH1		0x8084
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1604  #define   DPIO_AFC_RECAL		(1 << 14)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1605  #define   DPIO_DCLKP_EN			(1 << 13)
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1606  #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1607  #define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1608  #define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1609  #define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1610  #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1611  #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1612  #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
b9e5ac3c181e470 Ville Syrjälä                 2014-05-27   1613  #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1614  #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1615  
9197c88bf946cf7 Ville Syrjälä                 2014-04-09   1616  #define _CHV_CMN_DW19_CH0		0x814c
9197c88bf946cf7 Ville Syrjälä                 2014-04-09   1617  #define _CHV_CMN_DW6_CH1		0x8098
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1618  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
6669e39f95b5530 Ville Syrjälä                 2015-07-08   1619  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
e0fce78f0410148 Ville Syrjälä                 2015-07-08   1620  #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
9197c88bf946cf7 Ville Syrjälä                 2014-04-09   1621  #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
e0fce78f0410148 Ville Syrjälä                 2015-07-08   1622  
9197c88bf946cf7 Ville Syrjälä                 2014-04-09   1623  #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
9197c88bf946cf7 Ville Syrjälä                 2014-04-09   1624  
e0fce78f0410148 Ville Syrjälä                 2015-07-08   1625  #define CHV_CMN_DW28			0x8170
e0fce78f0410148 Ville Syrjälä                 2015-07-08   1626  #define   DPIO_CL1POWERDOWNEN		(1 << 23)
e0fce78f0410148 Ville Syrjälä                 2015-07-08   1627  #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
ee27921824e6ad0 Ville Syrjälä                 2015-07-08   1628  #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
ee27921824e6ad0 Ville Syrjälä                 2015-07-08   1629  #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
ee27921824e6ad0 Ville Syrjälä                 2015-07-08   1630  #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
ee27921824e6ad0 Ville Syrjälä                 2015-07-08   1631  #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
e0fce78f0410148 Ville Syrjälä                 2015-07-08   1632  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1633  #define CHV_CMN_DW30			0x8178
3e28878635cc3bb Ville Syrjälä                 2015-07-08   1634  #define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1635  #define   DPIO_LRC_BYPASS		(1 << 3)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1636  
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1637  #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1638  					(lane) * 0x200 + (offset))
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1639  
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1640  #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1641  #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1642  #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1643  #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1644  #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1645  #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1646  #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1647  #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1648  #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1649  #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
f72df8dbe2211cf Ville Syrjälä                 2014-04-09   1650  #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1651  #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1652  #define   DPIO_FRC_LATENCY_SHFIT	8
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1653  #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
9d556c99ed48ae9 Chon Ming Lee                 2014-05-02   1654  #define   DPIO_UPAR_SHIFT		30
5c6706e5644b608 Vandana Kannan                2014-11-24   1655  
5c6706e5644b608 Vandana Kannan                2014-11-24   1656  /* BXT PHY registers */
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1657  #define _BXT_PHY0_BASE			0x6C000
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1658  #define _BXT_PHY1_BASE			0x162000
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1659  #define _BXT_PHY2_BASE			0x163000
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1660  #define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1661  						     _BXT_PHY1_BASE, \
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1662  						     _BXT_PHY2_BASE)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1663  
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1664  #define _BXT_PHY(phy, reg)						\
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1665  	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1666  
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1667  #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1668  	(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,	\
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1669  					 (reg_ch1) - _BXT_PHY0_BASE))
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1670  #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1671  	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
5c6706e5644b608 Vandana Kannan                2014-11-24   1672  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1673  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
1881a4234ef0375 Uma Shankar                   2017-01-25   1674  #define  MIPIO_RST_CTRL				(1 << 2)
5c6706e5644b608 Vandana Kannan                2014-11-24   1675  
e93da0a0137b14f Imre Deak                     2016-06-13   1676  #define _BXT_PHY_CTL_DDI_A		0x64C00
e93da0a0137b14f Imre Deak                     2016-06-13   1677  #define _BXT_PHY_CTL_DDI_B		0x64C10
e93da0a0137b14f Imre Deak                     2016-06-13   1678  #define _BXT_PHY_CTL_DDI_C		0x64C20
e93da0a0137b14f Imre Deak                     2016-06-13   1679  #define   BXT_PHY_CMNLANE_POWERDOWN_ACK	(1 << 10)
e93da0a0137b14f Imre Deak                     2016-06-13   1680  #define   BXT_PHY_LANE_POWERDOWN_ACK	(1 << 9)
e93da0a0137b14f Imre Deak                     2016-06-13   1681  #define   BXT_PHY_LANE_ENABLED		(1 << 8)
e93da0a0137b14f Imre Deak                     2016-06-13   1682  #define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
e93da0a0137b14f Imre Deak                     2016-06-13   1683  							 _BXT_PHY_CTL_DDI_B)
e93da0a0137b14f Imre Deak                     2016-06-13   1684  
5c6706e5644b608 Vandana Kannan                2014-11-24   1685  #define _PHY_CTL_FAMILY_EDP		0x64C80
5c6706e5644b608 Vandana Kannan                2014-11-24   1686  #define _PHY_CTL_FAMILY_DDI		0x64C90
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1687  #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
5c6706e5644b608 Vandana Kannan                2014-11-24   1688  #define   COMMON_RESET_DIS		(1 << 31)
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1689  #define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1690  							  _PHY_CTL_FAMILY_EDP, \
0a116ce895e7ee2 Ander Conselvan de Oliveira   2016-12-02   1691  							  _PHY_CTL_FAMILY_DDI_C)
5c6706e5644b608 Vandana Kannan                2014-11-24   1692  
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1693  /* BXT PHY PLL registers */
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1694  #define _PORT_PLL_A			0x46074
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1695  #define _PORT_PLL_B			0x46078
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1696  #define _PORT_PLL_C			0x4607c
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1697  #define   PORT_PLL_ENABLE		(1 << 31)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1698  #define   PORT_PLL_LOCK			(1 << 30)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1699  #define   PORT_PLL_REF_SEL		(1 << 27)
f7044dd904d7a97 Madhav Chauhan                2016-12-02   1700  #define   PORT_PLL_POWER_ENABLE		(1 << 26)
f7044dd904d7a97 Madhav Chauhan                2016-12-02   1701  #define   PORT_PLL_POWER_STATE		(1 << 25)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   1702  #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1703  
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1704  #define _PORT_PLL_EBB_0_A		0x162034
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1705  #define _PORT_PLL_EBB_0_B		0x6C034
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1706  #define _PORT_PLL_EBB_0_C		0x6C340
aa610dcb7c1999f Imre Deak                     2015-06-22   1707  #define   PORT_PLL_P1_SHIFT		13
aa610dcb7c1999f Imre Deak                     2015-06-22   1708  #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
aa610dcb7c1999f Imre Deak                     2015-06-22   1709  #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
aa610dcb7c1999f Imre Deak                     2015-06-22   1710  #define   PORT_PLL_P2_SHIFT		8
aa610dcb7c1999f Imre Deak                     2015-06-22   1711  #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
aa610dcb7c1999f Imre Deak                     2015-06-22   1712  #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1713  #define BXT_PORT_PLL_EBB_0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1714  							 _PORT_PLL_EBB_0_B, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1715  							 _PORT_PLL_EBB_0_C)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1716  
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1717  #define _PORT_PLL_EBB_4_A		0x162038
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1718  #define _PORT_PLL_EBB_4_B		0x6C038
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1719  #define _PORT_PLL_EBB_4_C		0x6C344
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1720  #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1721  #define   PORT_PLL_RECALIBRATE		(1 << 14)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1722  #define BXT_PORT_PLL_EBB_4(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1723  							 _PORT_PLL_EBB_4_B, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1724  							 _PORT_PLL_EBB_4_C)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1725  
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1726  #define _PORT_PLL_0_A			0x162100
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1727  #define _PORT_PLL_0_B			0x6C100
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1728  #define _PORT_PLL_0_C			0x6C380
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1729  /* PORT_PLL_0_A */
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1730  #define   PORT_PLL_M2_MASK		0xFF
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1731  /* PORT_PLL_1_A */
aa610dcb7c1999f Imre Deak                     2015-06-22   1732  #define   PORT_PLL_N_SHIFT		8
aa610dcb7c1999f Imre Deak                     2015-06-22   1733  #define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
aa610dcb7c1999f Imre Deak                     2015-06-22   1734  #define   PORT_PLL_N(x)			((x) << PORT_PLL_N_SHIFT)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1735  /* PORT_PLL_2_A */
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1736  #define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1737  /* PORT_PLL_3_A */
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1738  #define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1739  /* PORT_PLL_6_A */
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1740  #define   PORT_PLL_PROP_COEFF_MASK	0xF
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1741  #define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1742  #define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1743  #define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1744  #define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1745  /* PORT_PLL_8_A */
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1746  #define   PORT_PLL_TARGET_CNT_MASK	0x3FF
b6dc71f38a84e36 Vandana Kannan                2015-05-13   1747  /* PORT_PLL_9_A */
05712c1561041d1 Imre Deak                     2015-06-18   1748  #define  PORT_PLL_LOCK_THRESHOLD_SHIFT	1
05712c1561041d1 Imre Deak                     2015-06-18   1749  #define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
b6dc71f38a84e36 Vandana Kannan                2015-05-13   1750  /* PORT_PLL_10_A */
b6dc71f38a84e36 Vandana Kannan                2015-05-13   1751  #define  PORT_PLL_DCO_AMP_OVR_EN_H	(1 << 27)
e62925567c7926e Vandana Kannan                2015-07-01   1752  #define  PORT_PLL_DCO_AMP_DEFAULT	15
b6dc71f38a84e36 Vandana Kannan                2015-05-13   1753  #define  PORT_PLL_DCO_AMP_MASK		0x3c00
68d9753837db0e4 Ville Syrjälä                 2015-09-18   1754  #define  PORT_PLL_DCO_AMP(x)		((x) << 10)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1755  #define _PORT_PLL_BASE(phy, ch)		_BXT_PHY_CH(phy, ch, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1756  						    _PORT_PLL_0_B, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1757  						    _PORT_PLL_0_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1758  #define BXT_PORT_PLL(phy, ch, idx)	_MMIO(_PORT_PLL_BASE(phy, ch) + \
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1759  					      (idx) * 4)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   1760  
5c6706e5644b608 Vandana Kannan                2014-11-24   1761  /* BXT PHY common lane registers */
5c6706e5644b608 Vandana Kannan                2014-11-24   1762  #define _PORT_CL1CM_DW0_A		0x162000
5c6706e5644b608 Vandana Kannan                2014-11-24   1763  #define _PORT_CL1CM_DW0_BC		0x6C000
5c6706e5644b608 Vandana Kannan                2014-11-24   1764  #define   PHY_POWER_GOOD		(1 << 16)
b61e79967a6f350 Vandana Kannan                2016-03-31   1765  #define   PHY_RESERVED			(1 << 7)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   1766  #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
5c6706e5644b608 Vandana Kannan                2014-11-24   1767  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1768  #define _PORT_CL1CM_DW9_A		0x162024
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1769  #define _PORT_CL1CM_DW9_BC		0x6C024
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1770  #define   IREF0RC_OFFSET_SHIFT		8
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1771  #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1772  #define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
d8d4a512a6ffa97 Ville Syrjälä                 2017-06-09   1773  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1774  #define _PORT_CL1CM_DW10_A		0x162028
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1775  #define _PORT_CL1CM_DW10_BC		0x6C028
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1776  #define   IREF1RC_OFFSET_SHIFT		8
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1777  #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1778  #define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1779  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1780  #define _PORT_CL1CM_DW28_A		0x162070
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1781  #define _PORT_CL1CM_DW28_BC		0x6C070
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1782  #define   OCL1_POWER_DOWN_EN		(1 << 23)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1783  #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1784  #define   SUS_CLK_CONFIG		0x3
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1785  #define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1786  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1787  #define _PORT_CL1CM_DW30_A		0x162078
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1788  #define _PORT_CL1CM_DW30_BC		0x6C078
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1789  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1790  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1791  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1792  /*
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1793   * CNL/ICL Port/COMBO-PHY Registers
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1794   */
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1795  #define _ICL_COMBOPHY_A			0x162000
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1796  #define _ICL_COMBOPHY_B			0x6C000
0e933162b0420b5 Matt Roper                    2019-06-25   1797  #define _EHL_COMBOPHY_C			0x160000
dc867bc7d887699 Matt Roper                    2019-07-09   1798  #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
0e933162b0420b5 Matt Roper                    2019-06-25   1799  					      _ICL_COMBOPHY_B, \
0e933162b0420b5 Matt Roper                    2019-06-25   1800  					      _EHL_COMBOPHY_C)
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1801  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1802  /* CNL/ICL Port CL_DW registers */
dc867bc7d887699 Matt Roper                    2019-07-09   1803  #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1804  					 4 * (dw))
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1805  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1806  #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
dc867bc7d887699 Matt Roper                    2019-07-09   1807  #define ICL_PORT_CL_DW5(phy)		_MMIO(_ICL_PORT_CL_DW(5, phy))
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1808  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1809  #define   SUS_CLOCK_CONFIG		(3 << 0)
ad186f3fd98a958 Paulo Zanoni                  2018-02-05   1810  
dc867bc7d887699 Matt Roper                    2019-07-09   1811  #define ICL_PORT_CL_DW10(phy)		_MMIO(_ICL_PORT_CL_DW(10, phy))
166869b390b6fe7 Madhav Chauhan                2018-07-05   1812  #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1813  #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
166869b390b6fe7 Madhav Chauhan                2018-07-05   1814  #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1815  #define  PWR_UP_ALL_LANES		(0x0 << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1816  #define  PWR_DOWN_LN_3_2_1		(0xe << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1817  #define  PWR_DOWN_LN_3_2		(0xc << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1818  #define  PWR_DOWN_LN_3			(0x8 << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1819  #define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1820  #define  PWR_DOWN_LN_1_0		(0x3 << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1821  #define  PWR_DOWN_LN_3_1		(0xa << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1822  #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1823  #define  PWR_DOWN_LN_MASK		(0xf << 4)
166869b390b6fe7 Madhav Chauhan                2018-07-05   1824  #define  PWR_DOWN_LN_SHIFT		4
166869b390b6fe7 Madhav Chauhan                2018-07-05   1825  
dc867bc7d887699 Matt Roper                    2019-07-09   1826  #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
67ca07e7ac10d7c Imre Deak                     2018-06-26   1827  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
67ca07e7ac10d7c Imre Deak                     2018-06-26   1828  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1829  /* CNL/ICL Port COMP_DW registers */
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1830  #define _ICL_PORT_COMP			0x100
dc867bc7d887699 Matt Roper                    2019-07-09   1831  #define _ICL_PORT_COMP_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1832  					 _ICL_PORT_COMP + 4 * (dw))
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1833  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1834  #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
dc867bc7d887699 Matt Roper                    2019-07-09   1835  #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1836  #define   COMP_INIT			(1 << 31)
5c6706e5644b608 Vandana Kannan                2014-11-24   1837  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1838  #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
dc867bc7d887699 Matt Roper                    2019-07-09   1839  #define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1840  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1841  #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
dc867bc7d887699 Matt Roper                    2019-07-09   1842  #define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1843  #define   PROCESS_INFO_DOT_0		(0 << 26)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1844  #define   PROCESS_INFO_DOT_1		(1 << 26)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1845  #define   PROCESS_INFO_DOT_4		(2 << 26)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1846  #define   PROCESS_INFO_MASK		(7 << 26)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1847  #define   PROCESS_INFO_SHIFT		26
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1848  #define   VOLTAGE_INFO_0_85V		(0 << 24)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1849  #define   VOLTAGE_INFO_0_95V		(1 << 24)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1850  #define   VOLTAGE_INFO_1_05V		(2 << 24)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1851  #define   VOLTAGE_INFO_MASK		(3 << 24)
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1852  #define   VOLTAGE_INFO_SHIFT		24
5c6706e5644b608 Vandana Kannan                2014-11-24   1853  
dc867bc7d887699 Matt Roper                    2019-07-09   1854  #define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
4361ccac2810553 Imre Deak                     2019-05-24   1855  #define   IREFGEN			(1 << 24)
4361ccac2810553 Imre Deak                     2019-05-24   1856  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1857  #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
dc867bc7d887699 Matt Roper                    2019-07-09   1858  #define ICL_PORT_COMP_DW9(phy)		_MMIO(_ICL_PORT_COMP_DW(9, phy))
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1859  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1860  #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
dc867bc7d887699 Matt Roper                    2019-07-09   1861  #define ICL_PORT_COMP_DW10(phy)		_MMIO(_ICL_PORT_COMP_DW(10, phy))
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1862  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1863  /* CNL/ICL Port PCS registers */
04416108ccea55f Rodrigo Vivi                  2017-06-09   1864  #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
04416108ccea55f Rodrigo Vivi                  2017-06-09   1865  #define _CNL_PORT_PCS_DW1_GRP_B		0x162384
04416108ccea55f Rodrigo Vivi                  2017-06-09   1866  #define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
04416108ccea55f Rodrigo Vivi                  2017-06-09   1867  #define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
04416108ccea55f Rodrigo Vivi                  2017-06-09   1868  #define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
04416108ccea55f Rodrigo Vivi                  2017-06-09   1869  #define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
04416108ccea55f Rodrigo Vivi                  2017-06-09   1870  #define _CNL_PORT_PCS_DW1_LN0_B		0x162604
04416108ccea55f Rodrigo Vivi                  2017-06-09   1871  #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
04416108ccea55f Rodrigo Vivi                  2017-06-09   1872  #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
04416108ccea55f Rodrigo Vivi                  2017-06-09   1873  #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
dc867bc7d887699 Matt Roper                    2019-07-09   1874  #define CNL_PORT_PCS_DW1_GRP(phy)	_MMIO(_PICK(phy, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1875  						    _CNL_PORT_PCS_DW1_GRP_AE, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1876  						    _CNL_PORT_PCS_DW1_GRP_B, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1877  						    _CNL_PORT_PCS_DW1_GRP_C, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1878  						    _CNL_PORT_PCS_DW1_GRP_D, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1879  						    _CNL_PORT_PCS_DW1_GRP_AE, \
da9cb11f76623b9 Mahesh Kumar                  2018-03-14   1880  						    _CNL_PORT_PCS_DW1_GRP_F))
dc867bc7d887699 Matt Roper                    2019-07-09   1881  #define CNL_PORT_PCS_DW1_LN0(phy)	_MMIO(_PICK(phy, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1882  						    _CNL_PORT_PCS_DW1_LN0_AE, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1883  						    _CNL_PORT_PCS_DW1_LN0_B, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1884  						    _CNL_PORT_PCS_DW1_LN0_C, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1885  						    _CNL_PORT_PCS_DW1_LN0_D, \
04416108ccea55f Rodrigo Vivi                  2017-06-09   1886  						    _CNL_PORT_PCS_DW1_LN0_AE, \
da9cb11f76623b9 Mahesh Kumar                  2018-03-14   1887  						    _CNL_PORT_PCS_DW1_LN0_F))
d61d1b3bbba1054 Madhav Chauhan                2018-07-05   1888  
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1889  #define _ICL_PORT_PCS_AUX		0x300
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1890  #define _ICL_PORT_PCS_GRP		0x600
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1891  #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
dc867bc7d887699 Matt Roper                    2019-07-09   1892  #define _ICL_PORT_PCS_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1893  					 _ICL_PORT_PCS_AUX + 4 * (dw))
dc867bc7d887699 Matt Roper                    2019-07-09   1894  #define _ICL_PORT_PCS_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1895  					 _ICL_PORT_PCS_GRP + 4 * (dw))
dc867bc7d887699 Matt Roper                    2019-07-09   1896  #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1897  					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
dc867bc7d887699 Matt Roper                    2019-07-09   1898  #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1899  #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1900  #define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
04416108ccea55f Rodrigo Vivi                  2017-06-09   1901  #define   COMMON_KEEPER_EN		(1 << 26)
6a7bafe8fdb6019 Vandita Kulkarni              2019-06-19   1902  #define   LATENCY_OPTIM_MASK		(0x3 << 2)
6a7bafe8fdb6019 Vandita Kulkarni              2019-06-19   1903  #define   LATENCY_OPTIM_VAL(x)		((x) << 2)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1904  
d72e84ccba20686 Mahesh Kumar                  2018-10-12   1905  /* CNL/ICL Port TX registers */
4635b573634c702 Mahesh Kumar                  2018-03-14   1906  #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
4635b573634c702 Mahesh Kumar                  2018-03-14   1907  #define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
4635b573634c702 Mahesh Kumar                  2018-03-14   1908  #define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
4635b573634c702 Mahesh Kumar                  2018-03-14   1909  #define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
4635b573634c702 Mahesh Kumar                  2018-03-14   1910  #define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
4635b573634c702 Mahesh Kumar                  2018-03-14   1911  #define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
4635b573634c702 Mahesh Kumar                  2018-03-14   1912  #define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
4635b573634c702 Mahesh Kumar                  2018-03-14   1913  #define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
4635b573634c702 Mahesh Kumar                  2018-03-14   1914  #define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
4635b573634c702 Mahesh Kumar                  2018-03-14   1915  #define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
b14c06ec024947e Aditya Swarup                 2019-01-10   1916  #define _CNL_PORT_TX_DW_GRP(dw, port)	(_PICK((port), \
4635b573634c702 Mahesh Kumar                  2018-03-14   1917  					       _CNL_PORT_TX_AE_GRP_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1918  					       _CNL_PORT_TX_B_GRP_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1919  					       _CNL_PORT_TX_B_GRP_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1920  					       _CNL_PORT_TX_D_GRP_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1921  					       _CNL_PORT_TX_AE_GRP_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1922  					       _CNL_PORT_TX_F_GRP_OFFSET) + \
4635b573634c702 Mahesh Kumar                  2018-03-14   1923  					       4 * (dw))
b14c06ec024947e Aditya Swarup                 2019-01-10   1924  #define _CNL_PORT_TX_DW_LN0(dw, port)	(_PICK((port), \
4635b573634c702 Mahesh Kumar                  2018-03-14   1925  					       _CNL_PORT_TX_AE_LN0_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1926  					       _CNL_PORT_TX_B_LN0_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1927  					       _CNL_PORT_TX_B_LN0_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1928  					       _CNL_PORT_TX_D_LN0_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1929  					       _CNL_PORT_TX_AE_LN0_OFFSET, \
4635b573634c702 Mahesh Kumar                  2018-03-14   1930  					       _CNL_PORT_TX_F_LN0_OFFSET) + \
4635b573634c702 Mahesh Kumar                  2018-03-14   1931  					       4 * (dw))
4635b573634c702 Mahesh Kumar                  2018-03-14   1932  
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1933  #define _ICL_PORT_TX_AUX		0x380
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1934  #define _ICL_PORT_TX_GRP		0x680
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1935  #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1936  
dc867bc7d887699 Matt Roper                    2019-07-09   1937  #define _ICL_PORT_TX_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1938  					 _ICL_PORT_TX_AUX + 4 * (dw))
dc867bc7d887699 Matt Roper                    2019-07-09   1939  #define _ICL_PORT_TX_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1940  					 _ICL_PORT_TX_GRP + 4 * (dw))
dc867bc7d887699 Matt Roper                    2019-07-09   1941  #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1942  					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1943  
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1944  #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1945  #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
dc867bc7d887699 Matt Roper                    2019-07-09   1946  #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1947  #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1948  #define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
7487508eff1fe78 Paulo Zanoni                  2018-03-23   1949  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1950  #define   SWING_SEL_UPPER_MASK		(1 << 15)
7487508eff1fe78 Paulo Zanoni                  2018-03-23   1951  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1952  #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
d61d1b3bbba1054 Madhav Chauhan                2018-07-05   1953  #define   FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
d61d1b3bbba1054 Madhav Chauhan                2018-07-05   1954  #define   FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1955  #define   RCOMP_SCALAR(x)		((x) << 0)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1956  #define   RCOMP_SCALAR_MASK		(0xFF << 0)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1957  
04416108ccea55f Rodrigo Vivi                  2017-06-09   1958  #define _CNL_PORT_TX_DW4_LN0_AE		0x162450
04416108ccea55f Rodrigo Vivi                  2017-06-09   1959  #define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
b14c06ec024947e Aditya Swarup                 2019-01-10   1960  #define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
b14c06ec024947e Aditya Swarup                 2019-01-10   1961  #define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
9194e42a1837b2c Aditya Swarup                 2019-01-28   1962  #define CNL_PORT_TX_DW4_LN(ln, port)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   1963  					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
4635b573634c702 Mahesh Kumar                  2018-03-14   1964  						    _CNL_PORT_TX_DW4_LN0_AE)))
dc867bc7d887699 Matt Roper                    2019-07-09   1965  #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1966  #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1967  #define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1968  #define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
04416108ccea55f Rodrigo Vivi                  2017-06-09   1969  #define   LOADGEN_SELECT		(1 << 31)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1970  #define   POST_CURSOR_1(x)		((x) << 12)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1971  #define   POST_CURSOR_1_MASK		(0x3F << 12)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1972  #define   POST_CURSOR_2(x)		((x) << 6)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1973  #define   POST_CURSOR_2_MASK		(0x3F << 6)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1974  #define   CURSOR_COEFF(x)		((x) << 0)
fcace3b9b727e25 Navare, Manasi D              2017-06-29   1975  #define   CURSOR_COEFF_MASK		(0x3F << 0)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1976  
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1977  #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
4e53840fdfdd054 Lucas De Marchi               2018-10-15   1978  #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
dc867bc7d887699 Matt Roper                    2019-07-09   1979  #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1980  #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1981  #define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
04416108ccea55f Rodrigo Vivi                  2017-06-09   1982  #define   TX_TRAINING_EN		(1 << 31)
5bb975de3f279c6 Manasi Navare                 2018-03-23   1983  #define   TAP2_DISABLE			(1 << 30)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1984  #define   TAP3_DISABLE			(1 << 29)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1985  #define   SCALING_MODE_SEL(x)		((x) << 18)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1986  #define   SCALING_MODE_SEL_MASK		(0x7 << 18)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1987  #define   RTERM_SELECT(x)		((x) << 3)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1988  #define   RTERM_SELECT_MASK		(0x7 << 3)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1989  
b14c06ec024947e Aditya Swarup                 2019-01-10   1990  #define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
b14c06ec024947e Aditya Swarup                 2019-01-10   1991  #define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
dc867bc7d887699 Matt Roper                    2019-07-09   1992  #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1993  #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1994  #define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
dc867bc7d887699 Matt Roper                    2019-07-09   1995  #define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
04416108ccea55f Rodrigo Vivi                  2017-06-09   1996  #define   N_SCALAR(x)			((x) << 24)
1f588aeb60b4412 Rodrigo Vivi                  2017-06-19   1997  #define   N_SCALAR_MASK			(0x7F << 24)
04416108ccea55f Rodrigo Vivi                  2017-06-09   1998  
683d672c425aa29 José Roberto de Souza         2019-06-19   1999  #define _ICL_DPHY_CHKN_REG			0x194
683d672c425aa29 José Roberto de Souza         2019-06-19   2000  #define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
683d672c425aa29 José Roberto de Souza         2019-06-19   2001  #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)
683d672c425aa29 José Roberto de Souza         2019-06-19   2002  
58106b7d816e1dd Aditya Swarup                 2019-01-28   2003  #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2004  	_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2005  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2006  #define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2007  #define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2008  #define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2009  #define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2010  #define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2011  #define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2012  #define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2013  #define MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
58106b7d816e1dd Aditya Swarup                 2019-01-28   2014  #define MG_TX1_LINK_PARAMS(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2015  	MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2016  				 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2017  				 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2018  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2019  #define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2020  #define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2021  #define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2022  #define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2023  #define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2024  #define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2025  #define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2026  #define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
58106b7d816e1dd Aditya Swarup                 2019-01-28   2027  #define MG_TX2_LINK_PARAMS(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2028  	MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2029  				 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2030  				 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2031  #define   CRI_USE_FS32			(1 << 5)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2032  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2033  #define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2034  #define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2035  #define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2036  #define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2037  #define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2038  #define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2039  #define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2040  #define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
58106b7d816e1dd Aditya Swarup                 2019-01-28   2041  #define MG_TX1_PISO_READLOAD(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2042  	MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2043  				 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2044  				 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2045  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2046  #define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2047  #define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2048  #define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2049  #define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2050  #define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2051  #define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2052  #define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
a38bb309c2ce25a Manasi Navare                 2018-07-13   2053  #define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
58106b7d816e1dd Aditya Swarup                 2019-01-28   2054  #define MG_TX2_PISO_READLOAD(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2055  	MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2056  				 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2057  				 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2058  #define   CRI_CALCINIT					(1 << 1)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2059  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2060  #define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
a38bb309c2ce25a Manasi Navare                 2018-07-13   2061  #define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
a38bb309c2ce25a Manasi Navare                 2018-07-13   2062  #define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
a38bb309c2ce25a Manasi Navare                 2018-07-13   2063  #define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
a38bb309c2ce25a Manasi Navare                 2018-07-13   2064  #define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
a38bb309c2ce25a Manasi Navare                 2018-07-13   2065  #define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
a38bb309c2ce25a Manasi Navare                 2018-07-13   2066  #define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
a38bb309c2ce25a Manasi Navare                 2018-07-13   2067  #define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
58106b7d816e1dd Aditya Swarup                 2019-01-28   2068  #define MG_TX1_SWINGCTRL(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2069  	MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2070  				 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2071  				 MG_TX_SWINGCTRL_TX1LN1_PORT1)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2072  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2073  #define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
a38bb309c2ce25a Manasi Navare                 2018-07-13   2074  #define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
a38bb309c2ce25a Manasi Navare                 2018-07-13   2075  #define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
a38bb309c2ce25a Manasi Navare                 2018-07-13   2076  #define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
a38bb309c2ce25a Manasi Navare                 2018-07-13   2077  #define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
a38bb309c2ce25a Manasi Navare                 2018-07-13   2078  #define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
a38bb309c2ce25a Manasi Navare                 2018-07-13   2079  #define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
a38bb309c2ce25a Manasi Navare                 2018-07-13   2080  #define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
58106b7d816e1dd Aditya Swarup                 2019-01-28   2081  #define MG_TX2_SWINGCTRL(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2082  	MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2083  				 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2084  				 MG_TX_SWINGCTRL_TX2LN1_PORT1)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2085  #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2086  #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2087  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2088  #define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
a38bb309c2ce25a Manasi Navare                 2018-07-13   2089  #define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
a38bb309c2ce25a Manasi Navare                 2018-07-13   2090  #define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
a38bb309c2ce25a Manasi Navare                 2018-07-13   2091  #define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
a38bb309c2ce25a Manasi Navare                 2018-07-13   2092  #define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
a38bb309c2ce25a Manasi Navare                 2018-07-13   2093  #define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
a38bb309c2ce25a Manasi Navare                 2018-07-13   2094  #define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
a38bb309c2ce25a Manasi Navare                 2018-07-13   2095  #define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
58106b7d816e1dd Aditya Swarup                 2019-01-28   2096  #define MG_TX1_DRVCTRL(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2097  	MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2098  				 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2099  				 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2100  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2101  #define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
a38bb309c2ce25a Manasi Navare                 2018-07-13   2102  #define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
a38bb309c2ce25a Manasi Navare                 2018-07-13   2103  #define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
a38bb309c2ce25a Manasi Navare                 2018-07-13   2104  #define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
a38bb309c2ce25a Manasi Navare                 2018-07-13   2105  #define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
a38bb309c2ce25a Manasi Navare                 2018-07-13   2106  #define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
a38bb309c2ce25a Manasi Navare                 2018-07-13   2107  #define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
a38bb309c2ce25a Manasi Navare                 2018-07-13   2108  #define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
58106b7d816e1dd Aditya Swarup                 2019-01-28   2109  #define MG_TX2_DRVCTRL(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2110  	MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2111  				 MG_TX_DRVCTRL_TX2LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2112  				 MG_TX_DRVCTRL_TX2LN1_PORT1)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2113  #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)			((x) << 24)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2114  #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2115  #define   CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2116  #define   CRI_TXDEEMPH_OVERRIDE_5_0(x)			((x) << 16)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2117  #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK		(0x3F << 16)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2118  #define   CRI_LOADGEN_SEL(x)				((x) << 12)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2119  #define   CRI_LOADGEN_SEL_MASK				(0x3 << 12)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2120  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2121  #define MG_CLKHUB_LN0_PORT1			0x16839C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2122  #define MG_CLKHUB_LN1_PORT1			0x16879C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2123  #define MG_CLKHUB_LN0_PORT2			0x16939C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2124  #define MG_CLKHUB_LN1_PORT2			0x16979C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2125  #define MG_CLKHUB_LN0_PORT3			0x16A39C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2126  #define MG_CLKHUB_LN1_PORT3			0x16A79C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2127  #define MG_CLKHUB_LN0_PORT4			0x16B39C
a38bb309c2ce25a Manasi Navare                 2018-07-13   2128  #define MG_CLKHUB_LN1_PORT4			0x16B79C
58106b7d816e1dd Aditya Swarup                 2019-01-28   2129  #define MG_CLKHUB(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2130  	MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2131  				 MG_CLKHUB_LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2132  				 MG_CLKHUB_LN1_PORT1)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2133  #define   CFG_LOW_RATE_LKREN_EN				(1 << 11)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2134  
a38bb309c2ce25a Manasi Navare                 2018-07-13   2135  #define MG_TX_DCC_TX1LN0_PORT1			0x168110
a38bb309c2ce25a Manasi Navare                 2018-07-13   2136  #define MG_TX_DCC_TX1LN1_PORT1			0x168510
a38bb309c2ce25a Manasi Navare                 2018-07-13   2137  #define MG_TX_DCC_TX1LN0_PORT2			0x169110
a38bb309c2ce25a Manasi Navare                 2018-07-13   2138  #define MG_TX_DCC_TX1LN1_PORT2			0x169510
a38bb309c2ce25a Manasi Navare                 2018-07-13   2139  #define MG_TX_DCC_TX1LN0_PORT3			0x16A110
a38bb309c2ce25a Manasi Navare                 2018-07-13   2140  #define MG_TX_DCC_TX1LN1_PORT3			0x16A510
a38bb309c2ce25a Manasi Navare                 2018-07-13   2141  #define MG_TX_DCC_TX1LN0_PORT4			0x16B110
a38bb309c2ce25a Manasi Navare                 2018-07-13   2142  #define MG_TX_DCC_TX1LN1_PORT4			0x16B510
58106b7d816e1dd Aditya Swarup                 2019-01-28   2143  #define MG_TX1_DCC(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2144  	MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2145  				 MG_TX_DCC_TX1LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2146  				 MG_TX_DCC_TX1LN1_PORT1)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2147  #define MG_TX_DCC_TX2LN0_PORT1			0x168090
a38bb309c2ce25a Manasi Navare                 2018-07-13   2148  #define MG_TX_DCC_TX2LN1_PORT1			0x168490
a38bb309c2ce25a Manasi Navare                 2018-07-13   2149  #define MG_TX_DCC_TX2LN0_PORT2			0x169090
a38bb309c2ce25a Manasi Navare                 2018-07-13   2150  #define MG_TX_DCC_TX2LN1_PORT2			0x169490
a38bb309c2ce25a Manasi Navare                 2018-07-13   2151  #define MG_TX_DCC_TX2LN0_PORT3			0x16A090
a38bb309c2ce25a Manasi Navare                 2018-07-13   2152  #define MG_TX_DCC_TX2LN1_PORT3			0x16A490
a38bb309c2ce25a Manasi Navare                 2018-07-13   2153  #define MG_TX_DCC_TX2LN0_PORT4			0x16B090
a38bb309c2ce25a Manasi Navare                 2018-07-13   2154  #define MG_TX_DCC_TX2LN1_PORT4			0x16B490
58106b7d816e1dd Aditya Swarup                 2019-01-28   2155  #define MG_TX2_DCC(ln, port) \
58106b7d816e1dd Aditya Swarup                 2019-01-28   2156  	MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2157  				 MG_TX_DCC_TX2LN0_PORT2, \
a38bb309c2ce25a Manasi Navare                 2018-07-13   2158  				 MG_TX_DCC_TX2LN1_PORT1)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2159  #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)	((x) << 25)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2160  #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK	(0x3 << 25)
a38bb309c2ce25a Manasi Navare                 2018-07-13   2161  #define   CFG_AMI_CK_DIV_OVERRIDE_EN		(1 << 24)
c92f47b5ec977a3 Manasi Navare                 2018-03-23   2162  
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2163  #define MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2164  #define MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2165  #define MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2166  #define MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2167  #define MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2168  #define MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2169  #define MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2170  #define MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
58106b7d816e1dd Aditya Swarup                 2019-01-28   2171  #define MG_DP_MODE(ln, port)	\
58106b7d816e1dd Aditya Swarup                 2019-01-28   2172  	MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2173  				 MG_DP_MODE_LN0_ACU_PORT2, \
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2174  				 MG_DP_MODE_LN1_ACU_PORT1)
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2175  #define   MG_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2176  #define   MG_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2177  #define   MG_DP_MODE_CFG_TR2PWR_GATING			(1 << 5)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2178  #define   MG_DP_MODE_CFG_TRPWR_GATING			(1 << 4)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2179  #define   MG_DP_MODE_CFG_CLNPWR_GATING			(1 << 3)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2180  #define   MG_DP_MODE_CFG_DIGPWR_GATING			(1 << 2)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2181  #define   MG_DP_MODE_CFG_GAONPWR_GATING			(1 << 1)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2182  
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2183  #define MG_MISC_SUS0_PORT1				0x168814
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2184  #define MG_MISC_SUS0_PORT2				0x169814
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2185  #define MG_MISC_SUS0_PORT3				0x16A814
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2186  #define MG_MISC_SUS0_PORT4				0x16B814
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2187  #define MG_MISC_SUS0(tc_port) \
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2188  	_MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2189  #define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK	(3 << 14)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2190  #define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x)	((x) << 14)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2191  #define   MG_MISC_SUS0_CFG_TR2PWR_GATING		(1 << 12)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2192  #define   MG_MISC_SUS0_CFG_CL2PWR_GATING		(1 << 11)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2193  #define   MG_MISC_SUS0_CFG_GAONPWR_GATING		(1 << 10)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2194  #define   MG_MISC_SUS0_CFG_TRPWR_GATING			(1 << 7)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2195  #define   MG_MISC_SUS0_CFG_CL1PWR_GATING		(1 << 6)
bc334d914eeee02 Paulo Zanoni                  2018-07-24   2196  #define   MG_MISC_SUS0_CFG_DGPWR_GATING			(1 << 5)
340a44bef2342b0 Paulo Zanoni                  2018-07-24   2197  
842d416654ebbca Ander Conselvan de Oliveira   2016-10-06   2198  /* The spec defines this only for BXT PHY0, but lets assume that this
842d416654ebbca Ander Conselvan de Oliveira   2016-10-06   2199   * would exist for PHY1 too if it had a second channel.
842d416654ebbca Ander Conselvan de Oliveira   2016-10-06   2200   */
842d416654ebbca Ander Conselvan de Oliveira   2016-10-06   2201  #define _PORT_CL2CM_DW6_A		0x162358
842d416654ebbca Ander Conselvan de Oliveira   2016-10-06   2202  #define _PORT_CL2CM_DW6_BC		0x6C358
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2203  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
5c6706e5644b608 Vandana Kannan                2014-11-24   2204  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
5c6706e5644b608 Vandana Kannan                2014-11-24   2205  
a6576a8d715ae73 Anusha Srivatsa               2018-11-01   2206  #define FIA1_BASE			0x163000
0caf625777300d3 Anusha Srivatsa               2019-07-11   2207  #define FIA2_BASE			0x16E000
0caf625777300d3 Anusha Srivatsa               2019-07-11   2208  #define FIA3_BASE			0x16F000
0caf625777300d3 Anusha Srivatsa               2019-07-11   2209  #define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
0caf625777300d3 Anusha Srivatsa               2019-07-11   2210  #define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
a6576a8d715ae73 Anusha Srivatsa               2018-11-01   2211  
a2bc69a1a9d6820 Manasi Navare                 2018-05-25   2212  /* ICL PHY DFLEX registers */
0caf625777300d3 Anusha Srivatsa               2019-07-11   2213  #define PORT_TX_DFLEXDPMLE1(fia)	_MMIO_FIA((fia),  0x008C0)
b4335ec0a3ee622 Manasi Navare                 2018-10-23   2214  #define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)	(0xf << (4 * (tc_port)))
b4335ec0a3ee622 Manasi Navare                 2018-10-23   2215  #define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)	(1 << (4 * (tc_port)))
b4335ec0a3ee622 Manasi Navare                 2018-10-23   2216  #define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)	(3 << (4 * (tc_port)))
b4335ec0a3ee622 Manasi Navare                 2018-10-23   2217  #define   DFLEXDPMLE1_DPMLETC_ML3(tc_port)	(8 << (4 * (tc_port)))
b4335ec0a3ee622 Manasi Navare                 2018-10-23   2218  #define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port)	(12 << (4 * (tc_port)))
b4335ec0a3ee622 Manasi Navare                 2018-10-23   2219  #define   DFLEXDPMLE1_DPMLETC_ML3_0(tc_port)	(15 << (4 * (tc_port)))
a2bc69a1a9d6820 Manasi Navare                 2018-05-25   2220  
5c6706e5644b608 Vandana Kannan                2014-11-24   2221  /* BXT PHY Ref registers */
5c6706e5644b608 Vandana Kannan                2014-11-24   2222  #define _PORT_REF_DW3_A			0x16218C
5c6706e5644b608 Vandana Kannan                2014-11-24   2223  #define _PORT_REF_DW3_BC		0x6C18C
5c6706e5644b608 Vandana Kannan                2014-11-24   2224  #define   GRC_DONE			(1 << 22)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2225  #define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC)
5c6706e5644b608 Vandana Kannan                2014-11-24   2226  
5c6706e5644b608 Vandana Kannan                2014-11-24   2227  #define _PORT_REF_DW6_A			0x162198
5c6706e5644b608 Vandana Kannan                2014-11-24   2228  #define _PORT_REF_DW6_BC		0x6C198
d1e082ffb898bd9 Imre Deak                     2016-04-01   2229  #define   GRC_CODE_SHIFT		24
d1e082ffb898bd9 Imre Deak                     2016-04-01   2230  #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
5c6706e5644b608 Vandana Kannan                2014-11-24   2231  #define   GRC_CODE_FAST_SHIFT		16
d1e082ffb898bd9 Imre Deak                     2016-04-01   2232  #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
5c6706e5644b608 Vandana Kannan                2014-11-24   2233  #define   GRC_CODE_SLOW_SHIFT		8
5c6706e5644b608 Vandana Kannan                2014-11-24   2234  #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
5c6706e5644b608 Vandana Kannan                2014-11-24   2235  #define   GRC_CODE_NOM_MASK		0xFF
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2236  #define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC)
5c6706e5644b608 Vandana Kannan                2014-11-24   2237  
5c6706e5644b608 Vandana Kannan                2014-11-24   2238  #define _PORT_REF_DW8_A			0x1621A0
5c6706e5644b608 Vandana Kannan                2014-11-24   2239  #define _PORT_REF_DW8_BC		0x6C1A0
5c6706e5644b608 Vandana Kannan                2014-11-24   2240  #define   GRC_DIS			(1 << 15)
5c6706e5644b608 Vandana Kannan                2014-11-24   2241  #define   GRC_RDY_OVRD			(1 << 1)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2242  #define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC)
5c6706e5644b608 Vandana Kannan                2014-11-24   2243  
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2244  /* BXT PHY PCS registers */
96fb9f9b154a8db Vandana Kannan                2014-11-18   2245  #define _PORT_PCS_DW10_LN01_A		0x162428
96fb9f9b154a8db Vandana Kannan                2014-11-18   2246  #define _PORT_PCS_DW10_LN01_B		0x6C428
96fb9f9b154a8db Vandana Kannan                2014-11-18   2247  #define _PORT_PCS_DW10_LN01_C		0x6C828
96fb9f9b154a8db Vandana Kannan                2014-11-18   2248  #define _PORT_PCS_DW10_GRP_A		0x162C28
96fb9f9b154a8db Vandana Kannan                2014-11-18   2249  #define _PORT_PCS_DW10_GRP_B		0x6CC28
96fb9f9b154a8db Vandana Kannan                2014-11-18   2250  #define _PORT_PCS_DW10_GRP_C		0x6CE28
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2251  #define BXT_PORT_PCS_DW10_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2252  							 _PORT_PCS_DW10_LN01_B, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2253  							 _PORT_PCS_DW10_LN01_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2254  #define BXT_PORT_PCS_DW10_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2255  							 _PORT_PCS_DW10_GRP_B, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2256  							 _PORT_PCS_DW10_GRP_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2257  
96fb9f9b154a8db Vandana Kannan                2014-11-18   2258  #define   TX2_SWING_CALC_INIT		(1 << 31)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2259  #define   TX1_SWING_CALC_INIT		(1 << 30)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2260  
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2261  #define _PORT_PCS_DW12_LN01_A		0x162430
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2262  #define _PORT_PCS_DW12_LN01_B		0x6C430
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2263  #define _PORT_PCS_DW12_LN01_C		0x6C830
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2264  #define _PORT_PCS_DW12_LN23_A		0x162630
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2265  #define _PORT_PCS_DW12_LN23_B		0x6C630
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2266  #define _PORT_PCS_DW12_LN23_C		0x6CA30
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2267  #define _PORT_PCS_DW12_GRP_A		0x162c30
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2268  #define _PORT_PCS_DW12_GRP_B		0x6CC30
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2269  #define _PORT_PCS_DW12_GRP_C		0x6CE30
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2270  #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2271  #define   LANE_STAGGER_MASK		0x1F
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2272  #define BXT_PORT_PCS_DW12_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2273  							 _PORT_PCS_DW12_LN01_B, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2274  							 _PORT_PCS_DW12_LN01_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2275  #define BXT_PORT_PCS_DW12_LN23(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2276  							 _PORT_PCS_DW12_LN23_B, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2277  							 _PORT_PCS_DW12_LN23_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2278  #define BXT_PORT_PCS_DW12_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2279  							 _PORT_PCS_DW12_GRP_B, \
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2280  							 _PORT_PCS_DW12_GRP_C)
dfb82408471ee2e Satheeshakrishna M            2014-08-22   2281  
5c6706e5644b608 Vandana Kannan                2014-11-24   2282  /* BXT PHY TX registers */
5c6706e5644b608 Vandana Kannan                2014-11-24   2283  #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
5c6706e5644b608 Vandana Kannan                2014-11-24   2284  					  ((lane) & 1) * 0x80)
5c6706e5644b608 Vandana Kannan                2014-11-24   2285  
96fb9f9b154a8db Vandana Kannan                2014-11-18   2286  #define _PORT_TX_DW2_LN0_A		0x162508
96fb9f9b154a8db Vandana Kannan                2014-11-18   2287  #define _PORT_TX_DW2_LN0_B		0x6C508
96fb9f9b154a8db Vandana Kannan                2014-11-18   2288  #define _PORT_TX_DW2_LN0_C		0x6C908
96fb9f9b154a8db Vandana Kannan                2014-11-18   2289  #define _PORT_TX_DW2_GRP_A		0x162D08
96fb9f9b154a8db Vandana Kannan                2014-11-18   2290  #define _PORT_TX_DW2_GRP_B		0x6CD08
96fb9f9b154a8db Vandana Kannan                2014-11-18   2291  #define _PORT_TX_DW2_GRP_C		0x6CF08
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2292  #define BXT_PORT_TX_DW2_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2293  							 _PORT_TX_DW2_LN0_B, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2294  							 _PORT_TX_DW2_LN0_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2295  #define BXT_PORT_TX_DW2_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2296  							 _PORT_TX_DW2_GRP_B, \
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2297  							 _PORT_TX_DW2_GRP_C)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2298  #define   MARGIN_000_SHIFT		16
96fb9f9b154a8db Vandana Kannan                2014-11-18   2299  #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2300  #define   UNIQ_TRANS_SCALE_SHIFT	8
96fb9f9b154a8db Vandana Kannan                2014-11-18   2301  #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2302  
96fb9f9b154a8db Vandana Kannan                2014-11-18   2303  #define _PORT_TX_DW3_LN0_A		0x16250C
96fb9f9b154a8db Vandana Kannan                2014-11-18   2304  #define _PORT_TX_DW3_LN0_B		0x6C50C
96fb9f9b154a8db Vandana Kannan                2014-11-18   2305  #define _PORT_TX_DW3_LN0_C		0x6C90C
96fb9f9b154a8db Vandana Kannan                2014-11-18   2306  #define _PORT_TX_DW3_GRP_A		0x162D0C
96fb9f9b154a8db Vandana Kannan                2014-11-18   2307  #define _PORT_TX_DW3_GRP_B		0x6CD0C
96fb9f9b154a8db Vandana Kannan                2014-11-18   2308  #define _PORT_TX_DW3_GRP_C		0x6CF0C
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2309  #define BXT_PORT_TX_DW3_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2310  							 _PORT_TX_DW3_LN0_B, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2311  							 _PORT_TX_DW3_LN0_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2312  #define BXT_PORT_TX_DW3_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2313  							 _PORT_TX_DW3_GRP_B, \
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2314  							 _PORT_TX_DW3_GRP_C)
9c58a049566566a Sonika Jindal                 2015-09-24   2315  #define   SCALE_DCOMP_METHOD		(1 << 26)
9c58a049566566a Sonika Jindal                 2015-09-24   2316  #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2317  
96fb9f9b154a8db Vandana Kannan                2014-11-18   2318  #define _PORT_TX_DW4_LN0_A		0x162510
96fb9f9b154a8db Vandana Kannan                2014-11-18   2319  #define _PORT_TX_DW4_LN0_B		0x6C510
96fb9f9b154a8db Vandana Kannan                2014-11-18   2320  #define _PORT_TX_DW4_LN0_C		0x6C910
96fb9f9b154a8db Vandana Kannan                2014-11-18   2321  #define _PORT_TX_DW4_GRP_A		0x162D10
96fb9f9b154a8db Vandana Kannan                2014-11-18   2322  #define _PORT_TX_DW4_GRP_B		0x6CD10
96fb9f9b154a8db Vandana Kannan                2014-11-18   2323  #define _PORT_TX_DW4_GRP_C		0x6CF10
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2324  #define BXT_PORT_TX_DW4_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2325  							 _PORT_TX_DW4_LN0_B, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2326  							 _PORT_TX_DW4_LN0_C)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2327  #define BXT_PORT_TX_DW4_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2328  							 _PORT_TX_DW4_GRP_B, \
96fb9f9b154a8db Vandana Kannan                2014-11-18   2329  							 _PORT_TX_DW4_GRP_C)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2330  #define   DEEMPH_SHIFT			24
96fb9f9b154a8db Vandana Kannan                2014-11-18   2331  #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
96fb9f9b154a8db Vandana Kannan                2014-11-18   2332  
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2333  #define _PORT_TX_DW5_LN0_A		0x162514
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2334  #define _PORT_TX_DW5_LN0_B		0x6C514
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2335  #define _PORT_TX_DW5_LN0_C		0x6C914
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2336  #define _PORT_TX_DW5_GRP_A		0x162D14
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2337  #define _PORT_TX_DW5_GRP_B		0x6CD14
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2338  #define _PORT_TX_DW5_GRP_C		0x6CF14
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2339  #define BXT_PORT_TX_DW5_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2340  							 _PORT_TX_DW5_LN0_B, \
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2341  							 _PORT_TX_DW5_LN0_C)
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2342  #define BXT_PORT_TX_DW5_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2343  							 _PORT_TX_DW5_GRP_B, \
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2344  							 _PORT_TX_DW5_GRP_C)
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2345  #define   DCC_DELAY_RANGE_1		(1 << 9)
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2346  #define   DCC_DELAY_RANGE_2		(1 << 8)
51b3ee35affa369 Ander Conselvan de Oliveira   2016-12-02   2347  
5c6706e5644b608 Vandana Kannan                2014-11-24   2348  #define _PORT_TX_DW14_LN0_A		0x162538
5c6706e5644b608 Vandana Kannan                2014-11-24   2349  #define _PORT_TX_DW14_LN0_B		0x6C538
5c6706e5644b608 Vandana Kannan                2014-11-24   2350  #define _PORT_TX_DW14_LN0_C		0x6C938
5c6706e5644b608 Vandana Kannan                2014-11-24   2351  #define   LATENCY_OPTIM_SHIFT		30
5c6706e5644b608 Vandana Kannan                2014-11-24   2352  #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2353  #define BXT_PORT_TX_DW14_LN(phy, ch, lane)				\
ed37892e6df2a3c Ander Conselvan de Oliveira   2016-10-19   2354  	_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,			\
5c6706e5644b608 Vandana Kannan                2014-11-24   2355  				   _PORT_TX_DW14_LN0_C) +		\
5c6706e5644b608 Vandana Kannan                2014-11-24   2356  	      _BXT_LANE_OFFSET(lane))
5c6706e5644b608 Vandana Kannan                2014-11-24   2357  
f8896f5d58e64bf David Weinehall               2015-06-25   2358  /* UAIMI scratch pad register 1 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2359  #define UAIMI_SPR1			_MMIO(0x4F074)
f8896f5d58e64bf David Weinehall               2015-06-25   2360  /* SKL VccIO mask */
f8896f5d58e64bf David Weinehall               2015-06-25   2361  #define SKL_VCCIO_MASK			0x1
f8896f5d58e64bf David Weinehall               2015-06-25   2362  /* SKL balance leg register */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2363  #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
f8896f5d58e64bf David Weinehall               2015-06-25   2364  /* I_boost values */
f8896f5d58e64bf David Weinehall               2015-06-25   2365  #define BALANCE_LEG_SHIFT(port)		(8 + 3 * (port))
f8896f5d58e64bf David Weinehall               2015-06-25   2366  #define BALANCE_LEG_MASK(port)		(7 << (8 + 3 * (port)))
f8896f5d58e64bf David Weinehall               2015-06-25   2367  /* Balance leg disable bits */
f8896f5d58e64bf David Weinehall               2015-06-25   2368  #define BALANCE_LEG_DISABLE_SHIFT	23
a7d8dbc07c8f0fa Ville Syrjälä                 2016-07-12   2369  #define BALANCE_LEG_DISABLE(port)	(1 << (23 + (port)))
f8896f5d58e64bf David Weinehall               2015-06-25   2370  
585fb111348f7cd Jesse Barnes                  2008-07-29   2371  /*
de151cf67ce52ed Jesse Barnes                  2008-11-12   2372   * Fence registers
eecf613a432c663 Ville Syrjälä                 2015-09-21   2373   * [0-7]  @ 0x2000 gen2,gen3
eecf613a432c663 Ville Syrjälä                 2015-09-21   2374   * [8-15] @ 0x3000 945,g33,pnv
eecf613a432c663 Ville Syrjälä                 2015-09-21   2375   *
eecf613a432c663 Ville Syrjälä                 2015-09-21   2376   * [0-15] @ 0x3000 gen4,gen5
eecf613a432c663 Ville Syrjälä                 2015-09-21   2377   *
eecf613a432c663 Ville Syrjälä                 2015-09-21   2378   * [0-15] @ 0x100000 gen6,vlv,chv
eecf613a432c663 Ville Syrjälä                 2015-09-21   2379   * [0-31] @ 0x100000 gen7+
585fb111348f7cd Jesse Barnes                  2008-07-29   2380   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2381  #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
de151cf67ce52ed Jesse Barnes                  2008-11-12   2382  #define   I830_FENCE_START_MASK		0x07f80000
de151cf67ce52ed Jesse Barnes                  2008-11-12   2383  #define   I830_FENCE_TILING_Y_SHIFT	12
0f973f27888e466 Jesse Barnes                  2009-01-26   2384  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
de151cf67ce52ed Jesse Barnes                  2008-11-12   2385  #define   I830_FENCE_PITCH_SHIFT	4
de151cf67ce52ed Jesse Barnes                  2008-11-12   2386  #define   I830_FENCE_REG_VALID		(1 << 0)
c36a2a6de59e4a1 Daniel Vetter                 2010-04-17   2387  #define   I915_FENCE_MAX_PITCH_VAL	4
e76a16deb878531 Eric Anholt                   2009-05-26   2388  #define   I830_FENCE_MAX_PITCH_VAL	6
8d7773a32d8aa72 Daniel Vetter                 2009-03-29   2389  #define   I830_FENCE_MAX_SIZE_VAL	(1 << 8)
de151cf67ce52ed Jesse Barnes                  2008-11-12   2390  
de151cf67ce52ed Jesse Barnes                  2008-11-12   2391  #define   I915_FENCE_START_MASK		0x0ff00000
0f973f27888e466 Jesse Barnes                  2009-01-26   2392  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   2393  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2394  #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2395  #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
de151cf67ce52ed Jesse Barnes                  2008-11-12   2396  #define   I965_FENCE_PITCH_SHIFT	2
de151cf67ce52ed Jesse Barnes                  2008-11-12   2397  #define   I965_FENCE_TILING_Y_SHIFT	1
de151cf67ce52ed Jesse Barnes                  2008-11-12   2398  #define   I965_FENCE_REG_VALID		(1 << 0)
8d7773a32d8aa72 Daniel Vetter                 2009-03-29   2399  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
de151cf67ce52ed Jesse Barnes                  2008-11-12   2400  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2401  #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2402  #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
eecf613a432c663 Ville Syrjälä                 2015-09-21   2403  #define   GEN6_FENCE_PITCH_SHIFT	32
3a062478308187d Ville Syrjälä                 2013-04-09   2404  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
4e901fdc263d32d Eric Anholt                   2009-10-26   2405  
2b6b3a09915f852 Deepak S                      2014-05-27   2406  
f691e2f4cec334e Daniel Vetter                 2012-02-02   2407  /* control register for cpu gtt access */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2408  #define TILECTL				_MMIO(0x101000)
f691e2f4cec334e Daniel Vetter                 2012-02-02   2409  #define   TILECTL_SWZCTL			(1 << 0)
e3a290553f3b09b Robert Beckett                2015-03-11   2410  #define   TILECTL_TLBPF			(1 << 1)
f691e2f4cec334e Daniel Vetter                 2012-02-02   2411  #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
f691e2f4cec334e Daniel Vetter                 2012-02-02   2412  #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
f691e2f4cec334e Daniel Vetter                 2012-02-02   2413  
de151cf67ce52ed Jesse Barnes                  2008-11-12   2414  /*
de151cf67ce52ed Jesse Barnes                  2008-11-12   2415   * Instruction and interrupt control regs
de151cf67ce52ed Jesse Barnes                  2008-11-12   2416   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2417  #define PGTBL_CTL	_MMIO(0x02020)
f1e1c2129b79cfd Ville Syrjälä                 2014-06-05   2418  #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
f1e1c2129b79cfd Ville Syrjälä                 2014-06-05   2419  #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2420  #define PGTBL_ER	_MMIO(0x02024)
81e7f2002b7db26 Ville Syrjälä                 2014-08-15   2421  #define PRB0_BASE	(0x2030 - 0x30)
81e7f2002b7db26 Ville Syrjälä                 2014-08-15   2422  #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
81e7f2002b7db26 Ville Syrjälä                 2014-08-15   2423  #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
81e7f2002b7db26 Ville Syrjälä                 2014-08-15   2424  #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
81e7f2002b7db26 Ville Syrjälä                 2014-08-15   2425  #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
81e7f2002b7db26 Ville Syrjälä                 2014-08-15   2426  #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
81e7f2002b7db26 Ville Syrjälä                 2014-08-15   2427  #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
333e9fe94d00ce8 Daniel Vetter                 2010-08-02   2428  #define RENDER_RING_BASE	0x02000
333e9fe94d00ce8 Daniel Vetter                 2010-08-02   2429  #define BSD_RING_BASE		0x04000
333e9fe94d00ce8 Daniel Vetter                 2010-08-02   2430  #define GEN6_BSD_RING_BASE	0x12000
845f74a70154166 Zhao Yakui                    2014-04-17   2431  #define GEN8_BSD2_RING_BASE	0x1c000
5f79e7c6754249d Oscar Mateo                   2018-03-02   2432  #define GEN11_BSD_RING_BASE	0x1c0000
5f79e7c6754249d Oscar Mateo                   2018-03-02   2433  #define GEN11_BSD2_RING_BASE	0x1c4000
5f79e7c6754249d Oscar Mateo                   2018-03-02   2434  #define GEN11_BSD3_RING_BASE	0x1d0000
5f79e7c6754249d Oscar Mateo                   2018-03-02   2435  #define GEN11_BSD4_RING_BASE	0x1d4000
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2436  #define VEBOX_RING_BASE		0x1a000
5f79e7c6754249d Oscar Mateo                   2018-03-02   2437  #define GEN11_VEBOX_RING_BASE		0x1c8000
5f79e7c6754249d Oscar Mateo                   2018-03-02   2438  #define GEN11_VEBOX2_RING_BASE		0x1d8000
549f7365820a212 Chris Wilson                  2010-10-19   2439  #define BLT_RING_BASE		0x22000
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2440  #define RING_TAIL(base)		_MMIO((base) + 0x30)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2441  #define RING_HEAD(base)		_MMIO((base) + 0x34)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2442  #define RING_START(base)	_MMIO((base) + 0x38)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2443  #define RING_CTL(base)		_MMIO((base) + 0x3c)
62ae14b1edca0aa Chris Wilson                  2016-10-04   2444  #define   RING_CTL_SIZE(size)	((size) - PAGE_SIZE) /* in bytes -> pages */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2445  #define RING_SYNC_0(base)	_MMIO((base) + 0x40)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2446  #define RING_SYNC_1(base)	_MMIO((base) + 0x44)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2447  #define RING_SYNC_2(base)	_MMIO((base) + 0x48)
c8c99b0f0dea1ce Ben Widawsky                  2011-09-14   2448  #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
c8c99b0f0dea1ce Ben Widawsky                  2011-09-14   2449  #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2450  #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
c8c99b0f0dea1ce Ben Widawsky                  2011-09-14   2451  #define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2452  #define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2453  #define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
c8c99b0f0dea1ce Ben Widawsky                  2011-09-14   2454  #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
c8c99b0f0dea1ce Ben Widawsky                  2011-09-14   2455  #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2456  #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2457  #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2458  #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
1950de14fd1b8ea Ben Widawsky                  2013-05-28   2459  #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2460  #define GEN6_NOSYNC	INVALID_MMIO_REG
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2461  #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2462  #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2463  #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2464  #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2465  #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
5ce5f61b70f97bd Mika Kuoppala                 2019-04-12   2466  #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
5ce5f61b70f97bd Mika Kuoppala                 2019-04-12   2467  #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
5ce5f61b70f97bd Mika Kuoppala                 2019-04-12   2468  #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
5ce5f61b70f97bd Mika Kuoppala                 2019-04-12   2469  
39e78234b0be7ae Mika Kuoppala                 2018-06-07   2470  #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
9e72b46c0d92735 Imre Deak                     2014-05-05   2471  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2472  #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
6d50b0650fb4605 Ville Syrjälä                 2015-05-19   2473  #define   GTT_CACHE_EN_ALL	0xF0007FFF
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2474  #define GEN7_WR_WATERMARK	_MMIO(0x4028)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2475  #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2476  #define ARB_MODE		_MMIO(0x4030)
f691e2f4cec334e Daniel Vetter                 2012-02-02   2477  #define   ARB_MODE_SWIZZLE_SNB	(1 << 4)
f691e2f4cec334e Daniel Vetter                 2012-02-02   2478  #define   ARB_MODE_SWIZZLE_IVB	(1 << 5)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2479  #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2480  #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
9e72b46c0d92735 Imre Deak                     2014-05-05   2481  /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2482  #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
9e72b46c0d92735 Imre Deak                     2014-05-05   2483  #define GEN7_LRA_LIMITS_REG_NUM	13
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2484  #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2485  #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
9e72b46c0d92735 Imre Deak                     2014-05-05   2486  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2487  #define GAMTARBMODE		_MMIO(0x04a08)
4afe8d3347d69af Ben Widawsky                  2013-11-02   2488  #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
31a5336e1c8e7cf Ben Widawsky                  2013-11-02   2489  #define   ARB_MODE_SWIZZLE_BDW	(1 << 1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2490  #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
5ac9793bf9f43cb Chris Wilson                  2016-07-27   2491  #define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100 * (engine)->hw_id)
b03ec3d67ab840f Michel Thierry                2017-11-13   2492  #define GEN8_RING_FAULT_REG	_MMIO(0x4094)
b03ec3d67ab840f Michel Thierry                2017-11-13   2493  #define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
828c79087cec61e Ben Widawsky                  2013-10-16   2494  #define   RING_FAULT_GTTSEL_MASK (1 << 11)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   2495  #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   2496  #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
828c79087cec61e Ben Widawsky                  2013-10-16   2497  #define   RING_FAULT_VALID	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2498  #define DONE_REG		_MMIO(0x40b0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2499  #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2500  #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
1790625b1deaafb Michal Wajdeczko              2017-09-08   2501  #define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index) * 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2502  #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2503  #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2504  #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2505  #define RING_ACTHD(base)	_MMIO((base) + 0x74)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2506  #define RING_ACTHD_UDW(base)	_MMIO((base) + 0x5c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2507  #define RING_NOPID(base)	_MMIO((base) + 0x94)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2508  #define RING_IMR(base)		_MMIO((base) + 0xa8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2509  #define RING_HWSTAM(base)	_MMIO((base) + 0x98)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2510  #define RING_TIMESTAMP(base)		_MMIO((base) + 0x358)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2511  #define RING_TIMESTAMP_UDW(base)	_MMIO((base) + 0x358 + 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   2512  #define   TAIL_ADDR		0x001FFFF8
585fb111348f7cd Jesse Barnes                  2008-07-29   2513  #define   HEAD_WRAP_COUNT	0xFFE00000
585fb111348f7cd Jesse Barnes                  2008-07-29   2514  #define   HEAD_WRAP_ONE		0x00200000
585fb111348f7cd Jesse Barnes                  2008-07-29   2515  #define   HEAD_ADDR		0x001FFFFC
585fb111348f7cd Jesse Barnes                  2008-07-29   2516  #define   RING_NR_PAGES		0x001FF000
585fb111348f7cd Jesse Barnes                  2008-07-29   2517  #define   RING_REPORT_MASK	0x00000006
585fb111348f7cd Jesse Barnes                  2008-07-29   2518  #define   RING_REPORT_64K	0x00000002
585fb111348f7cd Jesse Barnes                  2008-07-29   2519  #define   RING_REPORT_128K	0x00000004
585fb111348f7cd Jesse Barnes                  2008-07-29   2520  #define   RING_NO_REPORT	0x00000000
585fb111348f7cd Jesse Barnes                  2008-07-29   2521  #define   RING_VALID_MASK	0x00000001
585fb111348f7cd Jesse Barnes                  2008-07-29   2522  #define   RING_VALID		0x00000001
585fb111348f7cd Jesse Barnes                  2008-07-29   2523  #define   RING_INVALID		0x00000000
4b60e5cb707aa1d Chris Wilson                  2010-08-08   2524  #define   RING_WAIT_I8XX	(1 << 0) /* gen2, PRBx_HEAD */
4b60e5cb707aa1d Chris Wilson                  2010-08-08   2525  #define   RING_WAIT		(1 << 11) /* gen3+, PRBx_CTL */
1ec14ad31327026 Chris Wilson                  2010-12-04   2526  #define   RING_WAIT_SEMAPHORE	(1 << 10) /* gen6+ */
9e72b46c0d92735 Imre Deak                     2014-05-05   2527  
33136b06d549156 Arun Siluvery                 2016-01-21   2528  #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
1e2b7f497c28a47 John Harrison                 2019-07-12   2529  #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
1e2b7f497c28a47 John Harrison                 2019-07-12   2530  #define   RING_FORCE_TO_NONPRIV_ACCESS_RD	(1 << 28)
1e2b7f497c28a47 John Harrison                 2019-07-12   2531  #define   RING_FORCE_TO_NONPRIV_ACCESS_WR	(2 << 28)
1e2b7f497c28a47 John Harrison                 2019-07-12   2532  #define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID	(3 << 28)
1e2b7f497c28a47 John Harrison                 2019-07-12   2533  #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK	(3 << 28)
5380d0b781c491d John Harrison                 2019-06-17   2534  #define   RING_FORCE_TO_NONPRIV_RANGE_1		(0 << 0)     /* CFL+ & Gen11+ */
5380d0b781c491d John Harrison                 2019-06-17   2535  #define   RING_FORCE_TO_NONPRIV_RANGE_4		(1 << 0)
5380d0b781c491d John Harrison                 2019-06-17   2536  #define   RING_FORCE_TO_NONPRIV_RANGE_16	(2 << 0)
5380d0b781c491d John Harrison                 2019-06-17   2537  #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
1e2b7f497c28a47 John Harrison                 2019-07-12   2538  #define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
1e2b7f497c28a47 John Harrison                 2019-07-12   2539  #define   RING_FORCE_TO_NONPRIV_MASK_VALID	\
1e2b7f497c28a47 John Harrison                 2019-07-12   2540  					(RING_FORCE_TO_NONPRIV_RANGE_MASK \
1e2b7f497c28a47 John Harrison                 2019-07-12   2541  					| RING_FORCE_TO_NONPRIV_ACCESS_MASK)
33136b06d549156 Arun Siluvery                 2016-01-21   2542  #define   RING_MAX_NONPRIV_SLOTS  12
33136b06d549156 Arun Siluvery                 2016-01-21   2543  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2544  #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
9e72b46c0d92735 Imre Deak                     2014-05-05   2545  
4ba9c1f7c7b8ca8 Mika Kuoppala                 2016-07-20   2546  #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
4ba9c1f7c7b8ca8 Mika Kuoppala                 2016-07-20   2547  #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1 << 18)
4ba9c1f7c7b8ca8 Mika Kuoppala                 2016-07-20   2548  
9a6330cff9b4b06 Matthew Auld                  2017-10-06   2549  #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
9a6330cff9b4b06 Matthew Auld                  2017-10-06   2550  #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
85f04aa569addbd Mika Kuoppala                 2018-11-09   2551  #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
9a6330cff9b4b06 Matthew Auld                  2017-10-06   2552  
c0b730d572ea00d Mika Kuoppala                 2016-06-07   2553  #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
4ece66b149a38c7 Oscar Mateo                   2018-05-25   2554  #define   GAMT_CHKN_DISABLE_L3_COH_PIPE			(1 << 31)
c0b730d572ea00d Mika Kuoppala                 2016-06-07   2555  #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1 << 28)
86ebb015fa744dd Rodrigo Vivi                  2017-08-29   2556  #define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1 << 24)
c0b730d572ea00d Mika Kuoppala                 2016-06-07   2557  
8168bd48bb863c0 Chris Wilson                  2010-11-11   2558  #if 0
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2559  #define PRB0_TAIL	_MMIO(0x2030)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2560  #define PRB0_HEAD	_MMIO(0x2034)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2561  #define PRB0_START	_MMIO(0x2038)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2562  #define PRB0_CTL	_MMIO(0x203c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2563  #define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2564  #define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2565  #define PRB1_START	_MMIO(0x2048) /* 915+ only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2566  #define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
8168bd48bb863c0 Chris Wilson                  2010-11-11   2567  #endif
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2568  #define IPEIR_I965	_MMIO(0x2064)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2569  #define IPEHR_I965	_MMIO(0x2068)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2570  #define GEN7_SC_INSTDONE	_MMIO(0x7100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2571  #define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2572  #define GEN7_ROW_INSTDONE	_MMIO(0xe164)
f9e613728090e7f Ben Widawsky                  2016-09-20   2573  #define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
f9e613728090e7f Ben Widawsky                  2016-09-20   2574  #define   GEN8_MCR_SLICE(slice)		(((slice) & 3) << 26)
f9e613728090e7f Ben Widawsky                  2016-09-20   2575  #define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
f9e613728090e7f Ben Widawsky                  2016-09-20   2576  #define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
f9e613728090e7f Ben Widawsky                  2016-09-20   2577  #define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
d3d57927995f872 Kelvin Gardiner               2018-03-16   2578  #define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
d3d57927995f872 Kelvin Gardiner               2018-03-16   2579  #define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
d3d57927995f872 Kelvin Gardiner               2018-03-16   2580  #define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
d3d57927995f872 Kelvin Gardiner               2018-03-16   2581  #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2582  #define RING_IPEIR(base)	_MMIO((base) + 0x64)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2583  #define RING_IPEHR(base)	_MMIO((base) + 0x68)
f1d543485344f11 Imre Deak                     2015-09-30   2584  /*
f1d543485344f11 Imre Deak                     2015-09-30   2585   * On GEN4, only the render ring INSTDONE exists and has a different
f1d543485344f11 Imre Deak                     2015-09-30   2586   * layout than the GEN7+ version.
bd93a50e4dbae10 Imre Deak                     2015-09-30   2587   * The GEN2 counterpart of this register is GEN2_INSTDONE.
f1d543485344f11 Imre Deak                     2015-09-30   2588   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2589  #define RING_INSTDONE(base)	_MMIO((base) + 0x6c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2590  #define RING_INSTPS(base)	_MMIO((base) + 0x70)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2591  #define RING_DMA_FADD(base)	_MMIO((base) + 0x78)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2592  #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2593  #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2594  #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2595  #define INSTPS		_MMIO(0x2070) /* 965+ only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2596  #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2597  #define ACTHD_I965	_MMIO(0x2074)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2598  #define HWS_PGA		_MMIO(0x2080)
585fb111348f7cd Jesse Barnes                  2008-07-29   2599  #define HWS_ADDRESS_MASK	0xfffff000
585fb111348f7cd Jesse Barnes                  2008-07-29   2600  #define HWS_START_ADDRESS_SHIFT	4
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2601  #define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
97f5ab6651a996e Jesse Barnes                  2009-10-08   2602  #define   PWRCTX_EN	(1 << 0)
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25   2603  #define IPEIR(base)	_MMIO((base) + 0x88)
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25   2604  #define IPEHR(base)	_MMIO((base) + 0x8c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2605  #define GEN2_INSTDONE	_MMIO(0x2090)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2606  #define NOPID		_MMIO(0x2094)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2607  #define HWSTAM		_MMIO(0x2098)
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25   2608  #define DMA_FADD_I8XX(base)	_MMIO((base) + 0xd0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2609  #define RING_BBSTATE(base)	_MMIO((base) + 0x110)
35dc3f97a69bb34 Ville Syrjälä                 2015-11-04   2610  #define   RING_BB_PPGTT		(1 << 5)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2611  #define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2612  #define RING_SBBSTATE(base)	_MMIO((base) + 0x118) /* hsw+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2613  #define RING_SBBADDR_UDW(base)	_MMIO((base) + 0x11c) /* gen8+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2614  #define RING_BBADDR(base)	_MMIO((base) + 0x140)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2615  #define RING_BBADDR_UDW(base)	_MMIO((base) + 0x168) /* gen8+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2616  #define RING_BB_PER_CTX_PTR(base)	_MMIO((base) + 0x1c0) /* gen8+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2617  #define RING_INDIRECT_CTX(base)		_MMIO((base) + 0x1c4) /* gen8+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2618  #define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base) + 0x1c8) /* gen8+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2619  #define RING_CTX_TIMESTAMP(base)	_MMIO((base) + 0x3a8) /* gen8+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2620  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2621  #define ERROR_GEN6	_MMIO(0x40a0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2622  #define GEN7_ERR_INT	_MMIO(0x44040)
de032bf40a52dbb Paulo Zanoni                  2013-04-12   2623  #define   ERR_INT_POISON		(1 << 31)
b4c145c1d245c2c Ben Widawsky                  2012-08-20   2624  #define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   2625  #define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
8664281b64c4577 Paulo Zanoni                  2013-04-12   2626  #define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   2627  #define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
8664281b64c4577 Paulo Zanoni                  2013-04-12   2628  #define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   2629  #define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   2630  #define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
8664281b64c4577 Paulo Zanoni                  2013-04-12   2631  #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   2632  #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
f406839f094ef24 Chris Wilson                  2010-10-27   2633  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2634  #define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2635  #define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
5a3f58dfd142034 Oscar Mateo                   2017-12-22   2636  #define   FAULT_VA_HIGH_BITS		(0xf << 0)
5a3f58dfd142034 Oscar Mateo                   2017-12-22   2637  #define   FAULT_GTT_SEL			(1 << 4)
6c826f349587f6c Mika Kuoppala                 2015-03-24   2638  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2639  #define FPGA_DBG		_MMIO(0x42300)
3f1e109a8be5670 Paulo Zanoni                  2013-02-18   2640  #define   FPGA_DBG_RM_NOCLAIM	(1 << 31)
3f1e109a8be5670 Paulo Zanoni                  2013-02-18   2641  
8ac3e1bb76cc2e1 Mika Kuoppala                 2015-12-15   2642  #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
8ac3e1bb76cc2e1 Mika Kuoppala                 2015-12-15   2643  #define   CLAIM_ER_CLR		(1 << 31)
8ac3e1bb76cc2e1 Mika Kuoppala                 2015-12-15   2644  #define   CLAIM_ER_OVERFLOW	(1 << 16)
8ac3e1bb76cc2e1 Mika Kuoppala                 2015-12-15   2645  #define   CLAIM_ER_CTR_MASK	0xffff
8ac3e1bb76cc2e1 Mika Kuoppala                 2015-12-15   2646  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2647  #define DERRMR		_MMIO(0x44050)
4e0bbc316ef2a7d Ben Widawsky                  2013-11-02   2648  /* Note that HBLANK events are reserved on bdw+ */
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2649  #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2650  #define   DERRMR_PIPEA_PRI_FLIP_DONE	(1 << 1)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2651  #define   DERRMR_PIPEA_SPR_FLIP_DONE	(1 << 2)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2652  #define   DERRMR_PIPEA_VBLANK		(1 << 3)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2653  #define   DERRMR_PIPEA_HBLANK		(1 << 5)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2654  #define   DERRMR_PIPEB_SCANLINE		(1 << 8)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2655  #define   DERRMR_PIPEB_PRI_FLIP_DONE	(1 << 9)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2656  #define   DERRMR_PIPEB_SPR_FLIP_DONE	(1 << 10)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2657  #define   DERRMR_PIPEB_VBLANK		(1 << 11)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2658  #define   DERRMR_PIPEB_HBLANK		(1 << 13)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2659  /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2660  #define   DERRMR_PIPEC_SCANLINE		(1 << 14)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2661  #define   DERRMR_PIPEC_PRI_FLIP_DONE	(1 << 15)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2662  #define   DERRMR_PIPEC_SPR_FLIP_DONE	(1 << 20)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2663  #define   DERRMR_PIPEC_VBLANK		(1 << 21)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2664  #define   DERRMR_PIPEC_HBLANK		(1 << 22)
ffe74d75502e3a9 Chris Wilson                  2013-08-26   2665  
0f3b6849dd55943 Chris Wilson                  2013-01-15   2666  
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2667  /* GM45+ chicken bits -- debug workaround bits that may be required
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2668   * for various sorts of correct behavior.  The top 16 bits of each are
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2669   * the enables for writing to the corresponding low bit.
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2670   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2671  #define _3D_CHICKEN	_MMIO(0x2084)
4283908ef7f11a7 Daniel Vetter                 2012-12-14   2672  #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2673  #define _3D_CHICKEN2	_MMIO(0x208c)
b77422f80337d36 Kenneth Graunke               2018-06-15   2674  
b77422f80337d36 Kenneth Graunke               2018-06-15   2675  #define FF_SLICE_CHICKEN	_MMIO(0x2088)
b77422f80337d36 Kenneth Graunke               2018-06-15   2676  #define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX	(1 << 1)
b77422f80337d36 Kenneth Graunke               2018-06-15   2677  
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2678  /* Disables pipelining of read flushes past the SF-WIZ interface.
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2679   * Required on all Ironlake steppings according to the B-Spec, but the
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2680   * particular danger of not doing so is not specified.
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2681   */
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2682  # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2683  #define _3D_CHICKEN3	_MMIO(0x2090)
b77422f80337d36 Kenneth Graunke               2018-06-15   2684  #define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX		(1 << 12)
87f8020ec9e3069 Jesse Barnes                  2012-10-02   2685  #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
1a25db65d39cc6c Rodrigo Vivi                  2017-08-15   2686  #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE	(1 << 5)
26b6e44afb58432 Kenneth Graunke               2012-10-07   2687  #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
e927ecde591702f Ville Syrjälä                 2014-02-04   2688  #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x) << 1) /* gen8+ */
e927ecde591702f Ville Syrjälä                 2014-02-04   2689  #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
de6e2eaf2c420bb Eric Anholt                   2010-11-06   2690  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2691  #define MI_MODE		_MMIO(0x209c)
71cf39b117d5aa8 Eric Anholt                   2010-03-08   2692  # define VS_TIMER_DISPATCH				(1 << 6)
fc74d8e01165b56 Eric Anholt                   2012-01-19   2693  # define MI_FLUSH_ENABLE				(1 << 12)
1c8c38c588ea91f Chris Wilson                  2013-01-20   2694  # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
e9fea5747d2b3db Naresh Kumar Kachhi           2014-03-12   2695  # define MODE_IDLE					(1 << 9)
9991ae787a0c87f Chris Wilson                  2014-04-02   2696  # define STOP_RING					(1 << 8)
71cf39b117d5aa8 Eric Anholt                   2010-03-08   2697  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2698  #define GEN6_GT_MODE	_MMIO(0x20d0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2699  #define GEN7_GT_MODE	_MMIO(0x7008)
8d85d27281095e4 Ville Syrjälä                 2014-02-04   2700  #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
8d85d27281095e4 Ville Syrjälä                 2014-02-04   2701  #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
8d85d27281095e4 Ville Syrjälä                 2014-02-04   2702  #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
8d85d27281095e4 Ville Syrjälä                 2014-02-04   2703  #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
98533251b0bbfa5 Damien Lespiau                2014-12-08   2704  #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
6547fbdbfff62c9 Daniel Vetter                 2012-12-14   2705  #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   2706  #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
68d9753837db0e4 Ville Syrjälä                 2015-09-18   2707  #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
f8f2ac9a76b0f80 Ben Widawsky                  2012-10-03   2708  
a8ab5ed5e1bf856 Tim Gore                      2016-06-13   2709  /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
a8ab5ed5e1bf856 Tim Gore                      2016-06-13   2710  #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
a8ab5ed5e1bf856 Tim Gore                      2016-06-13   2711  #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
622b3f68139e932 Radhakrishna Sripada          2018-10-30   2712  #define   GEN11_ENABLE_32_PLANE_MODE (1 << 7)
a8ab5ed5e1bf856 Tim Gore                      2016-06-13   2713  
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2714  /* WaClearTdlStateAckDirtyBits */
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2715  #define GEN8_STATE_ACK		_MMIO(0x20F0)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2716  #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2717  #define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2718  #define   GEN9_STATE_ACK_TDL0 (1 << 12)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2719  #define   GEN9_STATE_ACK_TDL1 (1 << 13)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2720  #define   GEN9_STATE_ACK_TDL2 (1 << 14)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2721  #define   GEN9_STATE_ACK_TDL3 (1 << 15)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2722  #define   GEN9_SUBSLICE_TDL_ACK_BITS \
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2723  	(GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2724  	 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
b1e429fe3ba7b10 Tim Gore                      2016-03-21   2725  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2726  #define GFX_MODE	_MMIO(0x2520)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2727  #define GFX_MODE_GEN7	_MMIO(0x229c)
dbc651836372a7b Tvrtko Ursulin                2019-06-07   2728  #define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
1ec14ad31327026 Chris Wilson                  2010-12-04   2729  #define   GFX_RUN_LIST_ENABLE		(1 << 15)
4df001d3989ed31 Dave Gordon                   2015-08-12   2730  #define   GFX_INTERRUPT_STEERING	(1 << 14)
aa83e30d8f71c96 Chris Wilson                  2014-03-21   2731  #define   GFX_TLB_INVALIDATE_EXPLICIT	(1 << 13)
1ec14ad31327026 Chris Wilson                  2010-12-04   2732  #define   GFX_SURFACE_FAULT_ENABLE	(1 << 12)
1ec14ad31327026 Chris Wilson                  2010-12-04   2733  #define   GFX_REPLAY_MODE		(1 << 11)
1ec14ad31327026 Chris Wilson                  2010-12-04   2734  #define   GFX_PSMI_GRANULARITY		(1 << 10)
1ec14ad31327026 Chris Wilson                  2010-12-04   2735  #define   GFX_PPGTT_ENABLE		(1 << 9)
2dba3239f5c7511 Michel Thierry                2015-07-30   2736  #define   GEN8_GFX_PPGTT_48B		(1 << 7)
1ec14ad31327026 Chris Wilson                  2010-12-04   2737  
4df001d3989ed31 Dave Gordon                   2015-08-12   2738  #define   GFX_FORWARD_VBLANK_MASK	(3 << 5)
4df001d3989ed31 Dave Gordon                   2015-08-12   2739  #define   GFX_FORWARD_VBLANK_NEVER	(0 << 5)
4df001d3989ed31 Dave Gordon                   2015-08-12   2740  #define   GFX_FORWARD_VBLANK_ALWAYS	(1 << 5)
4df001d3989ed31 Dave Gordon                   2015-08-12   2741  #define   GFX_FORWARD_VBLANK_COND	(2 << 5)
4df001d3989ed31 Dave Gordon                   2015-08-12   2742  
225701fc20ef9c0 Kelvin Gardiner               2018-01-30   2743  #define   GEN11_GFX_DISABLE_LEGACY_MODE	(1 << 3)
225701fc20ef9c0 Kelvin Gardiner               2018-01-30   2744  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2745  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2746  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2747  #define SCPD0		_MMIO(0x209c) /* 915+ only */
9d9523d8c12295d Paulo Zanoni                  2019-04-10   2748  #define GEN2_IER	_MMIO(0x20a0)
9d9523d8c12295d Paulo Zanoni                  2019-04-10   2749  #define GEN2_IIR	_MMIO(0x20a4)
9d9523d8c12295d Paulo Zanoni                  2019-04-10   2750  #define GEN2_IMR	_MMIO(0x20a8)
9d9523d8c12295d Paulo Zanoni                  2019-04-10   2751  #define GEN2_ISR	_MMIO(0x20ac)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2752  #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
e4443e459ccf43f Ville Syrjälä                 2014-04-09   2753  #define   GINT_DIS		(1 << 22)
2d809570c8d72b9 Jesse Barnes                  2012-10-25   2754  #define   GCFG_DIS		(1 << 8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2755  #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2756  #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2757  #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2758  #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2759  #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2760  #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2761  #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
38807746fa2ce44 Deepak S                      2014-05-23   2762  #define VLV_PCBR_ADDR_SHIFT	12
38807746fa2ce44 Deepak S                      2014-05-23   2763  
90a72f8774b6060 Ville Syrjälä                 2013-02-19   2764  #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2765  #define EIR		_MMIO(0x20b0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2766  #define EMR		_MMIO(0x20b4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2767  #define ESR		_MMIO(0x20b8)
63eeaf38251183e Jesse Barnes                  2009-06-18   2768  #define   GM45_ERROR_PAGE_TABLE				(1 << 5)
63eeaf38251183e Jesse Barnes                  2009-06-18   2769  #define   GM45_ERROR_MEM_PRIV				(1 << 4)
63eeaf38251183e Jesse Barnes                  2009-06-18   2770  #define   I915_ERROR_PAGE_TABLE				(1 << 4)
63eeaf38251183e Jesse Barnes                  2009-06-18   2771  #define   GM45_ERROR_CP_PRIV				(1 << 3)
63eeaf38251183e Jesse Barnes                  2009-06-18   2772  #define   I915_ERROR_MEMORY_REFRESH			(1 << 1)
63eeaf38251183e Jesse Barnes                  2009-06-18   2773  #define   I915_ERROR_INSTRUCTION			(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2774  #define INSTPM	        _MMIO(0x20c0)
ee980b8003a25fb Li Peng                       2010-01-27   2775  #define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
3299254ffc42082 Ville Syrjälä                 2014-02-25   2776  #define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
8692d00e996ed2a Chris Wilson                  2011-02-05   2777  					will not assert AGPBUSY# and will only
8692d00e996ed2a Chris Wilson                  2011-02-05   2778  					be delivered when out of C3. */
84f9f938be4156e Ben Widawsky                  2011-12-12   2779  #define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
884020bf3d2a378 Chris Wilson                  2013-08-06   2780  #define   INSTPM_TLB_INVALIDATE	(1 << 9)
884020bf3d2a378 Chris Wilson                  2013-08-06   2781  #define   INSTPM_SYNC_FLUSH	(1 << 5)
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25   2782  #define ACTHD(base)	_MMIO((base) + 0xc8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2783  #define MEM_MODE	_MMIO(0x20cc)
1038392b4dd02a4 Ville Syrjälä                 2014-08-15   2784  #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
1038392b4dd02a4 Ville Syrjälä                 2014-08-15   2785  #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
1038392b4dd02a4 Ville Syrjälä                 2014-08-15   2786  #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2787  #define FW_BLC		_MMIO(0x20d8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2788  #define FW_BLC2		_MMIO(0x20dc)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2789  #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
ee980b8003a25fb Li Peng                       2010-01-27   2790  #define   FW_BLC_SELF_EN_MASK      (1 << 31)
ee980b8003a25fb Li Peng                       2010-01-27   2791  #define   FW_BLC_SELF_FIFO_MASK    (1 << 16) /* 945 only */
ee980b8003a25fb Li Peng                       2010-01-27   2792  #define   FW_BLC_SELF_EN           (1 << 15) /* 945 only */
7662c8bd6545c12 Shaohua Li                    2009-06-26   2793  #define MM_BURST_LENGTH     0x00700000
7662c8bd6545c12 Shaohua Li                    2009-06-26   2794  #define MM_FIFO_WATERMARK   0x0001F000
7662c8bd6545c12 Shaohua Li                    2009-06-26   2795  #define LM_BURST_LENGTH     0x00000700
7662c8bd6545c12 Shaohua Li                    2009-06-26   2796  #define LM_FIFO_WATERMARK   0x0000001F
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2797  #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
45503ded966c98e Keith Packard                 2010-07-19   2798  
7800549716f48ea Mahesh Kumar                  2018-01-30   2799  #define MBUS_ABOX_CTL			_MMIO(0x45038)
7800549716f48ea Mahesh Kumar                  2018-01-30   2800  #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
7800549716f48ea Mahesh Kumar                  2018-01-30   2801  #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
7800549716f48ea Mahesh Kumar                  2018-01-30   2802  #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
7800549716f48ea Mahesh Kumar                  2018-01-30   2803  #define MBUS_ABOX_B_CREDIT(x)		((x) << 16)
7800549716f48ea Mahesh Kumar                  2018-01-30   2804  #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
7800549716f48ea Mahesh Kumar                  2018-01-30   2805  #define MBUS_ABOX_BT_CREDIT_POOL2(x)	((x) << 8)
7800549716f48ea Mahesh Kumar                  2018-01-30   2806  #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
7800549716f48ea Mahesh Kumar                  2018-01-30   2807  #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
7800549716f48ea Mahesh Kumar                  2018-01-30   2808  
7800549716f48ea Mahesh Kumar                  2018-01-30   2809  #define _PIPEA_MBUS_DBOX_CTL		0x7003C
7800549716f48ea Mahesh Kumar                  2018-01-30   2810  #define _PIPEB_MBUS_DBOX_CTL		0x7103C
7800549716f48ea Mahesh Kumar                  2018-01-30   2811  #define PIPE_MBUS_DBOX_CTL(pipe)	_MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
7800549716f48ea Mahesh Kumar                  2018-01-30   2812  						   _PIPEB_MBUS_DBOX_CTL)
7800549716f48ea Mahesh Kumar                  2018-01-30   2813  #define MBUS_DBOX_BW_CREDIT_MASK	(3 << 14)
7800549716f48ea Mahesh Kumar                  2018-01-30   2814  #define MBUS_DBOX_BW_CREDIT(x)		((x) << 14)
7800549716f48ea Mahesh Kumar                  2018-01-30   2815  #define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)
7800549716f48ea Mahesh Kumar                  2018-01-30   2816  #define MBUS_DBOX_B_CREDIT(x)		((x) << 8)
7800549716f48ea Mahesh Kumar                  2018-01-30   2817  #define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)
7800549716f48ea Mahesh Kumar                  2018-01-30   2818  #define MBUS_DBOX_A_CREDIT(x)		((x) << 0)
7800549716f48ea Mahesh Kumar                  2018-01-30   2819  
7800549716f48ea Mahesh Kumar                  2018-01-30   2820  #define MBUS_UBOX_CTL			_MMIO(0x4503C)
7800549716f48ea Mahesh Kumar                  2018-01-30   2821  #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
7800549716f48ea Mahesh Kumar                  2018-01-30   2822  #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
7800549716f48ea Mahesh Kumar                  2018-01-30   2823  
45503ded966c98e Keith Packard                 2010-07-19   2824  /* Make render/texture TLB fetches lower priorty than associated data
45503ded966c98e Keith Packard                 2010-07-19   2825   *   fetches. This is not turned on by default
45503ded966c98e Keith Packard                 2010-07-19   2826   */
45503ded966c98e Keith Packard                 2010-07-19   2827  #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
45503ded966c98e Keith Packard                 2010-07-19   2828  
45503ded966c98e Keith Packard                 2010-07-19   2829  /* Isoch request wait on GTT enable (Display A/B/C streams).
45503ded966c98e Keith Packard                 2010-07-19   2830   * Make isoch requests stall on the TLB update. May cause
45503ded966c98e Keith Packard                 2010-07-19   2831   * display underruns (test mode only)
45503ded966c98e Keith Packard                 2010-07-19   2832   */
45503ded966c98e Keith Packard                 2010-07-19   2833  #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
45503ded966c98e Keith Packard                 2010-07-19   2834  
45503ded966c98e Keith Packard                 2010-07-19   2835  /* Block grant count for isoch requests when block count is
45503ded966c98e Keith Packard                 2010-07-19   2836   * set to a finite value.
45503ded966c98e Keith Packard                 2010-07-19   2837   */
45503ded966c98e Keith Packard                 2010-07-19   2838  #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
45503ded966c98e Keith Packard                 2010-07-19   2839  #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
45503ded966c98e Keith Packard                 2010-07-19   2840  #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
45503ded966c98e Keith Packard                 2010-07-19   2841  #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
45503ded966c98e Keith Packard                 2010-07-19   2842  #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
45503ded966c98e Keith Packard                 2010-07-19   2843  
45503ded966c98e Keith Packard                 2010-07-19   2844  /* Enable render writes to complete in C2/C3/C4 power states.
45503ded966c98e Keith Packard                 2010-07-19   2845   * If this isn't enabled, render writes are prevented in low
45503ded966c98e Keith Packard                 2010-07-19   2846   * power states. That seems bad to me.
45503ded966c98e Keith Packard                 2010-07-19   2847   */
45503ded966c98e Keith Packard                 2010-07-19   2848  #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
45503ded966c98e Keith Packard                 2010-07-19   2849  
45503ded966c98e Keith Packard                 2010-07-19   2850  /* This acknowledges an async flip immediately instead
45503ded966c98e Keith Packard                 2010-07-19   2851   * of waiting for 2TLB fetches.
45503ded966c98e Keith Packard                 2010-07-19   2852   */
45503ded966c98e Keith Packard                 2010-07-19   2853  #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
45503ded966c98e Keith Packard                 2010-07-19   2854  
45503ded966c98e Keith Packard                 2010-07-19   2855  /* Enables non-sequential data reads through arbiter
45503ded966c98e Keith Packard                 2010-07-19   2856   */
45503ded966c98e Keith Packard                 2010-07-19   2857  #define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
45503ded966c98e Keith Packard                 2010-07-19   2858  
45503ded966c98e Keith Packard                 2010-07-19   2859  /* Disable FSB snooping of cacheable write cycles from binner/render
45503ded966c98e Keith Packard                 2010-07-19   2860   * command stream
45503ded966c98e Keith Packard                 2010-07-19   2861   */
45503ded966c98e Keith Packard                 2010-07-19   2862  #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
45503ded966c98e Keith Packard                 2010-07-19   2863  
45503ded966c98e Keith Packard                 2010-07-19   2864  /* Arbiter time slice for non-isoch streams */
45503ded966c98e Keith Packard                 2010-07-19   2865  #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2866  #define   MI_ARB_TIME_SLICE_1			(0 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2867  #define   MI_ARB_TIME_SLICE_2			(1 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2868  #define   MI_ARB_TIME_SLICE_4			(2 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2869  #define   MI_ARB_TIME_SLICE_6			(3 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2870  #define   MI_ARB_TIME_SLICE_8			(4 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2871  #define   MI_ARB_TIME_SLICE_10			(5 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2872  #define   MI_ARB_TIME_SLICE_14			(6 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2873  #define   MI_ARB_TIME_SLICE_16			(7 << 5)
45503ded966c98e Keith Packard                 2010-07-19   2874  
45503ded966c98e Keith Packard                 2010-07-19   2875  /* Low priority grace period page size */
45503ded966c98e Keith Packard                 2010-07-19   2876  #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
45503ded966c98e Keith Packard                 2010-07-19   2877  #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
45503ded966c98e Keith Packard                 2010-07-19   2878  
45503ded966c98e Keith Packard                 2010-07-19   2879  /* Disable display A/B trickle feed */
45503ded966c98e Keith Packard                 2010-07-19   2880  #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
45503ded966c98e Keith Packard                 2010-07-19   2881  
45503ded966c98e Keith Packard                 2010-07-19   2882  /* Set display plane priority */
45503ded966c98e Keith Packard                 2010-07-19   2883  #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
45503ded966c98e Keith Packard                 2010-07-19   2884  #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
45503ded966c98e Keith Packard                 2010-07-19   2885  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2886  #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
54e472ae9632992 Ville Syrjälä                 2014-02-25   2887  #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
54e472ae9632992 Ville Syrjälä                 2014-02-25   2888  #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
54e472ae9632992 Ville Syrjälä                 2014-02-25   2889  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2890  #define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
4358a3748c39de3 Daniel Vetter                 2012-10-18   2891  #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   2892  #define   CM0_IZ_OPT_DISABLE      (1 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   2893  #define   CM0_ZR_OPT_DISABLE      (1 << 5)
009be664ecc77d5 Daniel Vetter                 2012-04-11   2894  #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1 << 5)
585fb111348f7cd Jesse Barnes                  2008-07-29   2895  #define   CM0_DEPTH_EVICT_DISABLE (1 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   2896  #define   CM0_COLOR_EVICT_DISABLE (1 << 3)
585fb111348f7cd Jesse Barnes                  2008-07-29   2897  #define   CM0_DEPTH_WRITE_DISABLE (1 << 1)
585fb111348f7cd Jesse Barnes                  2008-07-29   2898  #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2899  #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2900  #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
0f9b91c754b7244 Ben Widawsky                  2012-11-04   2901  #define   GFX_FLSH_CNTL_EN	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2902  #define ECOSKPD		_MMIO(0x21d0)
9ce9bdb00dfc7e5 Chris Wilson                  2019-04-19   2903  #define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
1afe3e9d4335bf3 Jesse Barnes                  2010-03-26   2904  #define   ECO_GATING_CX_ONLY	(1 << 3)
1afe3e9d4335bf3 Jesse Barnes                  2010-03-26   2905  #define   ECO_FLIP_DONE		(1 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   2906  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2907  #define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
4e04632e882719e Akash Goel                    2014-04-04   2908  #define RC_OP_FLUSH_ENABLE (1 << 0)
fe27c606625299e Chia-I Wu                     2014-01-28   2909  #define   HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2910  #define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
fb046853ad66e64 Jesse Barnes                  2012-03-28   2911  #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1 << 6)
5d708680eac2a8e Damien Lespiau                2014-03-26   2912  #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)
9370cd987e91d6d Damien Lespiau                2015-02-09   2913  #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)
fb046853ad66e64 Jesse Barnes                  2012-03-28   2914  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2915  #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
4efe070896e1f73 Jesse Barnes                  2011-01-18   2916  #define   GEN6_BLITTER_LOCK_SHIFT			16
4efe070896e1f73 Jesse Barnes                  2011-01-18   2917  #define   GEN6_BLITTER_FBC_NOTIFY			(1 << 3)
4efe070896e1f73 Jesse Barnes                  2011-01-18   2918  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2919  #define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
2c550183476dfa2 Chris Wilson                  2014-12-16   2920  #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
295e8bb73a4785b Ville Syrjälä                 2014-02-27   2921  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
e4443e459ccf43f Ville Syrjälä                 2014-04-09   2922  #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1 << 10)
295e8bb73a4785b Ville Syrjälä                 2014-02-27   2923  
19f81df2859eb10 Robert Bragg                  2017-06-13   2924  #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
19f81df2859eb10 Robert Bragg                  2017-06-13   2925  #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
19f81df2859eb10 Robert Bragg                  2017-06-13   2926  
0b904c890ac2d99 Talha Nassar                  2019-01-31   2927  #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
0b904c890ac2d99 Talha Nassar                  2019-01-31   2928  #define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
0b904c890ac2d99 Talha Nassar                  2019-01-31   2929  
693d11c34053450 Deepak S                      2015-01-16   2930  /* Fuse readout registers for GT */
b8ec759e6f1c6da Lionel Landwerlin             2018-02-21   2931  #define HSW_PAVP_FUSE1			_MMIO(0x911C)
b8ec759e6f1c6da Lionel Landwerlin             2018-02-21   2932  #define   HSW_F1_EU_DIS_SHIFT		16
b8ec759e6f1c6da Lionel Landwerlin             2018-02-21   2933  #define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
b8ec759e6f1c6da Lionel Landwerlin             2018-02-21   2934  #define   HSW_F1_EU_DIS_10EUS		0
b8ec759e6f1c6da Lionel Landwerlin             2018-02-21   2935  #define   HSW_F1_EU_DIS_8EUS		1
b8ec759e6f1c6da Lionel Landwerlin             2018-02-21   2936  #define   HSW_F1_EU_DIS_6EUS		2
b8ec759e6f1c6da Lionel Landwerlin             2018-02-21   2937  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2938  #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
c93043ae1deaa0f Jeff McGee                    2015-02-27   2939  #define   CHV_FGT_DISABLE_SS0		(1 << 10)
c93043ae1deaa0f Jeff McGee                    2015-02-27   2940  #define   CHV_FGT_DISABLE_SS1		(1 << 11)
693d11c34053450 Deepak S                      2015-01-16   2941  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
693d11c34053450 Deepak S                      2015-01-16   2942  #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
693d11c34053450 Deepak S                      2015-01-16   2943  #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
693d11c34053450 Deepak S                      2015-01-16   2944  #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
693d11c34053450 Deepak S                      2015-01-16   2945  #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
693d11c34053450 Deepak S                      2015-01-16   2946  #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
693d11c34053450 Deepak S                      2015-01-16   2947  #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
693d11c34053450 Deepak S                      2015-01-16   2948  #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
693d11c34053450 Deepak S                      2015-01-16   2949  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2950  #define GEN8_FUSE2			_MMIO(0x9120)
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2951  #define   GEN8_F2_SS_DIS_SHIFT		21
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2952  #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
3873218f359a411 Jeff McGee                    2015-02-13   2953  #define   GEN8_F2_S_ENA_SHIFT		25
3873218f359a411 Jeff McGee                    2015-02-13   2954  #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
3873218f359a411 Jeff McGee                    2015-02-13   2955  
3873218f359a411 Jeff McGee                    2015-02-13   2956  #define   GEN9_F2_SS_DIS_SHIFT		20
3873218f359a411 Jeff McGee                    2015-02-13   2957  #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
3873218f359a411 Jeff McGee                    2015-02-13   2958  
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2959  #define   GEN10_F2_S_ENA_SHIFT		22
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2960  #define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2961  #define   GEN10_F2_SS_DIS_SHIFT		18
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2962  #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2963  
fe864b76c2ab950 Yunwei Zhang                  2018-05-18   2964  #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
fe864b76c2ab950 Yunwei Zhang                  2018-05-18   2965  #define GEN10_L3BANK_PAIR_COUNT     4
fe864b76c2ab950 Yunwei Zhang                  2018-05-18   2966  #define GEN10_L3BANK_MASK   0x0F
fe864b76c2ab950 Yunwei Zhang                  2018-05-18   2967  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2968  #define GEN8_EU_DISABLE0		_MMIO(0x9134)
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2969  #define   GEN8_EU_DIS0_S0_MASK		0xffffff
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2970  #define   GEN8_EU_DIS0_S1_SHIFT		24
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2971  #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2972  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2973  #define GEN8_EU_DISABLE1		_MMIO(0x9138)
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2974  #define   GEN8_EU_DIS1_S1_MASK		0xffff
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2975  #define   GEN8_EU_DIS1_S2_SHIFT		16
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2976  #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2977  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2978  #define GEN8_EU_DISABLE2		_MMIO(0x913c)
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2979  #define   GEN8_EU_DIS2_S2_MASK		0xff
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   2980  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2981  #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice) * 0x4)
3873218f359a411 Jeff McGee                    2015-02-13   2982  
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2983  #define GEN10_EU_DISABLE3		_MMIO(0x9140)
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2984  #define   GEN10_EU_DIS_SS_MASK		0xff
4e9767bc28e9313 Ben Widawsky                  2017-09-20   2985  
26376a7e74d2def Oscar Mateo                   2018-03-16   2986  #define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
26376a7e74d2def Oscar Mateo                   2018-03-16   2987  #define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
26376a7e74d2def Oscar Mateo                   2018-03-16   2988  #define   GEN11_GT_VEBOX_DISABLE_SHIFT	16
547fcf9b1c608cf José Roberto de Souza         2019-03-26   2989  #define   GEN11_GT_VEBOX_DISABLE_MASK	(0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
26376a7e74d2def Oscar Mateo                   2018-03-16   2990  
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2991  #define GEN11_EU_DISABLE _MMIO(0x9134)
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2992  #define GEN11_EU_DIS_MASK 0xFF
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2993  
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2994  #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2995  #define GEN11_GT_S_ENA_MASK 0xFF
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2996  
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2997  #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
8b5eb5e2b5d2ddf Kelvin Gardiner               2018-03-20   2998  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   2999  #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
12f55818bac7b89 Chris Wilson                  2012-07-05   3000  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
12f55818bac7b89 Chris Wilson                  2012-07-05   3001  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
12f55818bac7b89 Chris Wilson                  2012-07-05   3002  #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
12f55818bac7b89 Chris Wilson                  2012-07-05   3003  #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
881f47b64723f4d Xiang, Haihao                 2010-09-19   3004  
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3005  /* On modern GEN architectures interrupt control consists of two sets
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3006   * of registers. The first set pertains to the ring generating the
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3007   * interrupt. The second control is for the functional block generating the
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3008   * interrupt. These are PM, GT, DE, etc.
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3009   *
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3010   * Luckily *knocks on wood* all the ring interrupt bits match up with the
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3011   * GT interrupt bits, so we don't need to duplicate the defines.
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3012   *
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3013   * These defines should cover us well from SNB->HSW with minor exceptions
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3014   * it can also work on ILK.
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3015   */
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3016  #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3017  #define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3018  #define GT_BLT_USER_INTERRUPT			(1 << 22)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3019  #define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3020  #define GT_BSD_USER_INTERRUPT			(1 << 12)
35a85ac60618521 Ben Widawsky                  2013-09-19   3021  #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
73d477f6bb17a1f Oscar Mateo                   2014-07-24   3022  #define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3023  #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3024  #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3025  #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3026  #define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3027  #define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3028  #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3029  
12638c57f319521 Ben Widawsky                  2013-05-28   3030  #define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
12638c57f319521 Ben Widawsky                  2013-05-28   3031  #define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
12638c57f319521 Ben Widawsky                  2013-05-28   3032  
772c2a519cec265 Tvrtko Ursulin                2016-10-13   3033  #define GT_PARITY_ERROR(dev_priv) \
35a85ac60618521 Ben Widawsky                  2013-09-19   3034  	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
772c2a519cec265 Tvrtko Ursulin                2016-10-13   3035  	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
35a85ac60618521 Ben Widawsky                  2013-09-19   3036  
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3037  /* These are all the "old" interrupts */
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3038  #define ILK_BSD_USER_INTERRUPT				(1 << 5)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3039  
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3040  #define I915_PM_INTERRUPT				(1 << 31)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3041  #define I915_ISP_INTERRUPT				(1 << 22)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3042  #define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3043  #define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
e7d7cad08d35329 Jani Nikula                   2014-11-14   3044  #define I915_MIPIC_INTERRUPT				(1 << 19)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3045  #define I915_MIPIA_INTERRUPT				(1 << 18)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3046  #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3047  #define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3048  #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3049  #define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3050  #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3051  #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3052  #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3053  #define I915_HWB_OOM_INTERRUPT				(1 << 13)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3054  #define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3055  #define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3056  #define I915_MISC_INTERRUPT				(1 << 11)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3057  #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3058  #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3059  #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3060  #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3061  #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3062  #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3063  #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3064  #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3065  #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3066  #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3067  #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3068  #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3069  #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3070  #define I915_DEBUG_INTERRUPT				(1 << 2)
fac12f6cdcb25ca Ville Syrjälä                 2014-04-09   3071  #define I915_WINVALID_INTERRUPT				(1 << 1)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3072  #define I915_USER_INTERRUPT				(1 << 1)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3073  #define I915_ASLE_INTERRUPT				(1 << 0)
cc609d5da5c78c9 Ben Widawsky                  2013-05-28   3074  #define I915_BSD_USER_INTERRUPT				(1 << 25)
881f47b64723f4d Xiang, Haihao                 2010-09-19   3075  
eef57324d926f0d Jerome Anand                  2017-01-25   3076  #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
eef57324d926f0d Jerome Anand                  2017-01-25   3077  #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
eef57324d926f0d Jerome Anand                  2017-01-25   3078  
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3079  /* DisplayPort Audio w/ LPE */
9db13e5f2d6dc85 Takashi Iwai                  2017-02-02   3080  #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
9db13e5f2d6dc85 Takashi Iwai                  2017-02-02   3081  #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
9db13e5f2d6dc85 Takashi Iwai                  2017-02-02   3082  
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3083  #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3084  #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3085  #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3086  #define VLV_AUD_PORT_EN_DBG(port)	_MMIO_PORT3((port) - PORT_B,	   \
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3087  						    _VLV_AUD_PORT_EN_B_DBG, \
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3088  						    _VLV_AUD_PORT_EN_C_DBG, \
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3089  						    _VLV_AUD_PORT_EN_D_DBG)
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3090  #define VLV_AMP_MUTE		        (1 << 1)
d5d8c3a19e43ca5 Pierre-Louis Bossart          2017-01-31   3091  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3092  #define GEN6_BSD_RNCID			_MMIO(0x12198)
881f47b64723f4d Xiang, Haihao                 2010-09-19   3093  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3094  #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3095  #define   GEN7_FF_SCHED_MASK		0x0077070
ab57fff1302c485 Ben Widawsky                  2013-12-12   3096  #define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3097  #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3098  #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3099  #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3100  #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
41c0b3a88c7bae9 Ben Widawsky                  2013-01-26   3101  #define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3102  #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3103  #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3104  #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
a1e969e0332de7a Ben Widawsky                  2012-04-14   3105  #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3106  #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3107  #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3108  #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
a1e969e0332de7a Ben Widawsky                  2012-04-14   3109  #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
a1e969e0332de7a Ben Widawsky                  2012-04-14   3110  
881f47b64723f4d Xiang, Haihao                 2010-09-19   3111  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3112   * Framebuffer compression (915+ only)
585fb111348f7cd Jesse Barnes                  2008-07-29   3113   */
585fb111348f7cd Jesse Barnes                  2008-07-29   3114  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3115  #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3116  #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3117  #define FBC_CONTROL		_MMIO(0x3208)
585fb111348f7cd Jesse Barnes                  2008-07-29   3118  #define   FBC_CTL_EN		(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   3119  #define   FBC_CTL_PERIODIC	(1 << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   3120  #define   FBC_CTL_INTERVAL_SHIFT (16)
585fb111348f7cd Jesse Barnes                  2008-07-29   3121  #define   FBC_CTL_UNCOMPRESSIBLE (1 << 14)
4967790112b284f Priit Laes                    2010-03-02   3122  #define   FBC_CTL_C3_IDLE	(1 << 13)
585fb111348f7cd Jesse Barnes                  2008-07-29   3123  #define   FBC_CTL_STRIDE_SHIFT	(5)
82f344967cca4d4 Ville Syrjälä                 2013-11-28   3124  #define   FBC_CTL_FENCENO_SHIFT	(0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3125  #define FBC_COMMAND		_MMIO(0x320c)
585fb111348f7cd Jesse Barnes                  2008-07-29   3126  #define   FBC_CMD_COMPRESS	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3127  #define FBC_STATUS		_MMIO(0x3210)
585fb111348f7cd Jesse Barnes                  2008-07-29   3128  #define   FBC_STAT_COMPRESSING	(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   3129  #define   FBC_STAT_COMPRESSED	(1 << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   3130  #define   FBC_STAT_MODIFIED	(1 << 29)
82f344967cca4d4 Ville Syrjälä                 2013-11-28   3131  #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3132  #define FBC_CONTROL2		_MMIO(0x3214)
585fb111348f7cd Jesse Barnes                  2008-07-29   3133  #define   FBC_CTL_FENCE_DBL	(0 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   3134  #define   FBC_CTL_IDLE_IMM	(0 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   3135  #define   FBC_CTL_IDLE_FULL	(1 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   3136  #define   FBC_CTL_IDLE_LINE	(2 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   3137  #define   FBC_CTL_IDLE_DEBUG	(3 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   3138  #define   FBC_CTL_CPU_FENCE	(1 << 1)
7f2cf220b867dad Ville Syrjälä                 2014-01-23   3139  #define   FBC_CTL_PLANE(plane)	((plane) << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3140  #define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3141  #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   3142  
585fb111348f7cd Jesse Barnes                  2008-07-29   3143  #define FBC_LL_SIZE		(1536)
585fb111348f7cd Jesse Barnes                  2008-07-29   3144  
44fff99ff25f1dd Mika Kuoppala                 2016-06-07   3145  #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
44fff99ff25f1dd Mika Kuoppala                 2016-06-07   3146  #define   FBC_LLC_FULLY_OPEN	(1 << 30)
44fff99ff25f1dd Mika Kuoppala                 2016-06-07   3147  
74dff282237ea8c Jesse Barnes                  2009-09-14   3148  /* Framebuffer compression for GM45+ */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3149  #define DPFC_CB_BASE		_MMIO(0x3200)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3150  #define DPFC_CONTROL		_MMIO(0x3208)
74dff282237ea8c Jesse Barnes                  2009-09-14   3151  #define   DPFC_CTL_EN		(1 << 31)
7f2cf220b867dad Ville Syrjälä                 2014-01-23   3152  #define   DPFC_CTL_PLANE(plane)	((plane) << 30)
7f2cf220b867dad Ville Syrjälä                 2014-01-23   3153  #define   IVB_DPFC_CTL_PLANE(plane)	((plane) << 29)
74dff282237ea8c Jesse Barnes                  2009-09-14   3154  #define   DPFC_CTL_FENCE_EN	(1 << 29)
abe959c7e06f62f Rodrigo Vivi                  2013-05-06   3155  #define   IVB_DPFC_CTL_FENCE_EN	(1 << 28)
9ce9d0695d15da2 Chris Wilson                  2011-07-08   3156  #define   DPFC_CTL_PERSISTENT_MODE	(1 << 25)
74dff282237ea8c Jesse Barnes                  2009-09-14   3157  #define   DPFC_SR_EN		(1 << 10)
74dff282237ea8c Jesse Barnes                  2009-09-14   3158  #define   DPFC_CTL_LIMIT_1X	(0 << 6)
74dff282237ea8c Jesse Barnes                  2009-09-14   3159  #define   DPFC_CTL_LIMIT_2X	(1 << 6)
74dff282237ea8c Jesse Barnes                  2009-09-14   3160  #define   DPFC_CTL_LIMIT_4X	(2 << 6)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3161  #define DPFC_RECOMP_CTL		_MMIO(0x320c)
74dff282237ea8c Jesse Barnes                  2009-09-14   3162  #define   DPFC_RECOMP_STALL_EN	(1 << 27)
74dff282237ea8c Jesse Barnes                  2009-09-14   3163  #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
74dff282237ea8c Jesse Barnes                  2009-09-14   3164  #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
74dff282237ea8c Jesse Barnes                  2009-09-14   3165  #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
74dff282237ea8c Jesse Barnes                  2009-09-14   3166  #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3167  #define DPFC_STATUS		_MMIO(0x3210)
74dff282237ea8c Jesse Barnes                  2009-09-14   3168  #define   DPFC_INVAL_SEG_SHIFT  (16)
74dff282237ea8c Jesse Barnes                  2009-09-14   3169  #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
74dff282237ea8c Jesse Barnes                  2009-09-14   3170  #define   DPFC_COMP_SEG_SHIFT	(0)
3fd5d1ecae2d91b Ville Syrjälä                 2017-06-06   3171  #define   DPFC_COMP_SEG_MASK	(0x000007ff)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3172  #define DPFC_STATUS2		_MMIO(0x3214)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3173  #define DPFC_FENCE_YOFF		_MMIO(0x3218)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3174  #define DPFC_CHICKEN		_MMIO(0x3224)
74dff282237ea8c Jesse Barnes                  2009-09-14   3175  #define   DPFC_HT_MODIFY	(1 << 31)
74dff282237ea8c Jesse Barnes                  2009-09-14   3176  
b52eb4dcab23fe0 Zhao Yakui                    2010-06-12   3177  /* Framebuffer compression for Ironlake */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3178  #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3179  #define ILK_DPFC_CONTROL	_MMIO(0x43208)
da46f936bb0396f Rodrigo Vivi                  2014-08-01   3180  #define   FBC_CTL_FALSE_COLOR	(1 << 10)
b52eb4dcab23fe0 Zhao Yakui                    2010-06-12   3181  /* The bit 28-8 is reserved */
b52eb4dcab23fe0 Zhao Yakui                    2010-06-12   3182  #define   DPFC_RESERVED		(0x1FFFFF00)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3183  #define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3184  #define ILK_DPFC_STATUS		_MMIO(0x43210)
3fd5d1ecae2d91b Ville Syrjälä                 2017-06-06   3185  #define  ILK_DPFC_COMP_SEG_MASK	0x7ff
3fd5d1ecae2d91b Ville Syrjälä                 2017-06-06   3186  #define IVB_FBC_STATUS2		_MMIO(0x43214)
3fd5d1ecae2d91b Ville Syrjälä                 2017-06-06   3187  #define  IVB_FBC_COMP_SEG_MASK	0x7ff
3fd5d1ecae2d91b Ville Syrjälä                 2017-06-06   3188  #define  BDW_FBC_COMP_SEG_MASK	0xfff
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3189  #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3190  #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
d1b4eefdea6d63a Mika Kuoppala                 2016-06-07   3191  #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
cc49abc2460fadc Matt Roper                    2019-06-12   3192  #define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL	(1 << 14)
031cd8c85aefad3 Mika Kuoppala                 2016-06-07   3193  #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1 << 23)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3194  #define ILK_FBC_RT_BASE		_MMIO(0x2128)
b52eb4dcab23fe0 Zhao Yakui                    2010-06-12   3195  #define   ILK_FBC_RT_VALID	(1 << 0)
abe959c7e06f62f Rodrigo Vivi                  2013-05-06   3196  #define   SNB_FBC_FRONT_BUFFER	(1 << 1)
b52eb4dcab23fe0 Zhao Yakui                    2010-06-12   3197  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3198  #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
b52eb4dcab23fe0 Zhao Yakui                    2010-06-12   3199  #define   ILK_FBCQ_DIS		(1 << 22)
1398261a2e84c53 Yuanhan Liu                   2010-12-15   3200  #define	  ILK_PABSTRETCH_DIS	(1 << 21)
1398261a2e84c53 Yuanhan Liu                   2010-12-15   3201  
b52eb4dcab23fe0 Zhao Yakui                    2010-06-12   3202  
585fb111348f7cd Jesse Barnes                  2008-07-29   3203  /*
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3204   * Framebuffer compression for Sandybridge
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3205   *
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3206   * The following two registers are of type GTTMMADR
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3207   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3208  #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3209  #define   SNB_CPU_FENCE_ENABLE	(1 << 29)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3210  #define DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3211  
abe959c7e06f62f Rodrigo Vivi                  2013-05-06   3212  /* Framebuffer compression for Ivybridge */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3213  #define IVB_FBC_RT_BASE			_MMIO(0x7020)
abe959c7e06f62f Rodrigo Vivi                  2013-05-06   3214  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3215  #define IPS_CTL		_MMIO(0x43408)
42db64efcd95014 Paulo Zanoni                  2013-05-31   3216  #define   IPS_ENABLE	(1 << 31)
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3217  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3218  #define MSG_FBC_REND_STATE	_MMIO(0x50380)
fd3da6c95b6d865 Rodrigo Vivi                  2013-06-06   3219  #define   FBC_REND_NUKE		(1 << 2)
fd3da6c95b6d865 Rodrigo Vivi                  2013-06-06   3220  #define   FBC_REND_CACHE_CLEAN	(1 << 1)
fd3da6c95b6d865 Rodrigo Vivi                  2013-06-06   3221  
9c04f015ebc2cc2 Yuanhan Liu                   2010-12-15   3222  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3223   * GPIO regs
585fb111348f7cd Jesse Barnes                  2008-07-29   3224   */
dce888798d3ed1c Lucas De Marchi               2018-07-27   3225  #define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
dce888798d3ed1c Lucas De Marchi               2018-07-27   3226  				      4 * (gpio))
dce888798d3ed1c Lucas De Marchi               2018-07-27   3227  
585fb111348f7cd Jesse Barnes                  2008-07-29   3228  # define GPIO_CLOCK_DIR_MASK		(1 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   3229  # define GPIO_CLOCK_DIR_IN		(0 << 1)
585fb111348f7cd Jesse Barnes                  2008-07-29   3230  # define GPIO_CLOCK_DIR_OUT		(1 << 1)
585fb111348f7cd Jesse Barnes                  2008-07-29   3231  # define GPIO_CLOCK_VAL_MASK		(1 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   3232  # define GPIO_CLOCK_VAL_OUT		(1 << 3)
585fb111348f7cd Jesse Barnes                  2008-07-29   3233  # define GPIO_CLOCK_VAL_IN		(1 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   3234  # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
585fb111348f7cd Jesse Barnes                  2008-07-29   3235  # define GPIO_DATA_DIR_MASK		(1 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   3236  # define GPIO_DATA_DIR_IN		(0 << 9)
585fb111348f7cd Jesse Barnes                  2008-07-29   3237  # define GPIO_DATA_DIR_OUT		(1 << 9)
585fb111348f7cd Jesse Barnes                  2008-07-29   3238  # define GPIO_DATA_VAL_MASK		(1 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   3239  # define GPIO_DATA_VAL_OUT		(1 << 11)
585fb111348f7cd Jesse Barnes                  2008-07-29   3240  # define GPIO_DATA_VAL_IN		(1 << 12)
585fb111348f7cd Jesse Barnes                  2008-07-29   3241  # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
585fb111348f7cd Jesse Barnes                  2008-07-29   3242  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3243  #define GMBUS0			_MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
07e17a75922a593 Sean Paul                     2018-01-08   3244  #define   GMBUS_AKSV_SELECT	(1 << 11)
f899fc64cda8569 Chris Wilson                  2010-07-20   3245  #define   GMBUS_RATE_100KHZ	(0 << 8)
f899fc64cda8569 Chris Wilson                  2010-07-20   3246  #define   GMBUS_RATE_50KHZ	(1 << 8)
f899fc64cda8569 Chris Wilson                  2010-07-20   3247  #define   GMBUS_RATE_400KHZ	(2 << 8) /* reserved on Pineview */
f899fc64cda8569 Chris Wilson                  2010-07-20   3248  #define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */
f899fc64cda8569 Chris Wilson                  2010-07-20   3249  #define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */
d5dc0f43f268bf2 Ramalingam C                  2018-06-28   3250  #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
988c70156ce1ae1 Jani Nikula                   2015-03-27   3251  #define   GMBUS_PIN_DISABLED	0
988c70156ce1ae1 Jani Nikula                   2015-03-27   3252  #define   GMBUS_PIN_SSC		1
988c70156ce1ae1 Jani Nikula                   2015-03-27   3253  #define   GMBUS_PIN_VGADDC	2
988c70156ce1ae1 Jani Nikula                   2015-03-27   3254  #define   GMBUS_PIN_PANEL	3
988c70156ce1ae1 Jani Nikula                   2015-03-27   3255  #define   GMBUS_PIN_DPD_CHV	3 /* HDMID_CHV */
988c70156ce1ae1 Jani Nikula                   2015-03-27   3256  #define   GMBUS_PIN_DPC		4 /* HDMIC */
988c70156ce1ae1 Jani Nikula                   2015-03-27   3257  #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
988c70156ce1ae1 Jani Nikula                   2015-03-27   3258  #define   GMBUS_PIN_DPD		6 /* HDMID */
988c70156ce1ae1 Jani Nikula                   2015-03-27   3259  #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
3d02352cd9e8b43 Rodrigo Vivi                  2017-06-02   3260  #define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
4c27283415ec9e3 Jani Nikula                   2015-04-01   3261  #define   GMBUS_PIN_2_BXT	2
4c27283415ec9e3 Jani Nikula                   2015-04-01   3262  #define   GMBUS_PIN_3_BXT	3
3d02352cd9e8b43 Rodrigo Vivi                  2017-06-02   3263  #define   GMBUS_PIN_4_CNP	4
5c749c522faca51 Anusha Srivatsa               2018-01-11   3264  #define   GMBUS_PIN_9_TC1_ICP	9
5c749c522faca51 Anusha Srivatsa               2018-01-11   3265  #define   GMBUS_PIN_10_TC2_ICP	10
5c749c522faca51 Anusha Srivatsa               2018-01-11   3266  #define   GMBUS_PIN_11_TC3_ICP	11
5c749c522faca51 Anusha Srivatsa               2018-01-11   3267  #define   GMBUS_PIN_12_TC4_ICP	12
3fd53262f0dd813 Mahesh Kumar                  2019-07-11   3268  #define   GMBUS_PIN_13_TC5_TGP	13
3fd53262f0dd813 Mahesh Kumar                  2019-07-11   3269  #define   GMBUS_PIN_14_TC6_TGP	14
5c749c522faca51 Anusha Srivatsa               2018-01-11   3270  
3fd53262f0dd813 Mahesh Kumar                  2019-07-11   3271  #define   GMBUS_NUM_PINS	15 /* including 0 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3272  #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
f899fc64cda8569 Chris Wilson                  2010-07-20   3273  #define   GMBUS_SW_CLR_INT	(1 << 31)
f899fc64cda8569 Chris Wilson                  2010-07-20   3274  #define   GMBUS_SW_RDY		(1 << 30)
f899fc64cda8569 Chris Wilson                  2010-07-20   3275  #define   GMBUS_ENT		(1 << 29) /* enable timeout */
f899fc64cda8569 Chris Wilson                  2010-07-20   3276  #define   GMBUS_CYCLE_NONE	(0 << 25)
f899fc64cda8569 Chris Wilson                  2010-07-20   3277  #define   GMBUS_CYCLE_WAIT	(1 << 25)
f899fc64cda8569 Chris Wilson                  2010-07-20   3278  #define   GMBUS_CYCLE_INDEX	(2 << 25)
f899fc64cda8569 Chris Wilson                  2010-07-20   3279  #define   GMBUS_CYCLE_STOP	(4 << 25)
f899fc64cda8569 Chris Wilson                  2010-07-20   3280  #define   GMBUS_BYTE_COUNT_SHIFT 16
9535c4757b881e0 Dmitry Torokhov               2015-04-21   3281  #define   GMBUS_BYTE_COUNT_MAX   256U
73675cf6979bb80 Ramalingam C                  2018-06-28   3282  #define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
f899fc64cda8569 Chris Wilson                  2010-07-20   3283  #define   GMBUS_SLAVE_INDEX_SHIFT 8
f899fc64cda8569 Chris Wilson                  2010-07-20   3284  #define   GMBUS_SLAVE_ADDR_SHIFT 1
f899fc64cda8569 Chris Wilson                  2010-07-20   3285  #define   GMBUS_SLAVE_READ	(1 << 0)
f899fc64cda8569 Chris Wilson                  2010-07-20   3286  #define   GMBUS_SLAVE_WRITE	(0 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3287  #define GMBUS2			_MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
f899fc64cda8569 Chris Wilson                  2010-07-20   3288  #define   GMBUS_INUSE		(1 << 15)
f899fc64cda8569 Chris Wilson                  2010-07-20   3289  #define   GMBUS_HW_WAIT_PHASE	(1 << 14)
f899fc64cda8569 Chris Wilson                  2010-07-20   3290  #define   GMBUS_STALL_TIMEOUT	(1 << 13)
f899fc64cda8569 Chris Wilson                  2010-07-20   3291  #define   GMBUS_INT		(1 << 12)
f899fc64cda8569 Chris Wilson                  2010-07-20   3292  #define   GMBUS_HW_RDY		(1 << 11)
f899fc64cda8569 Chris Wilson                  2010-07-20   3293  #define   GMBUS_SATOER		(1 << 10)
f899fc64cda8569 Chris Wilson                  2010-07-20   3294  #define   GMBUS_ACTIVE		(1 << 9)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3295  #define GMBUS3			_MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3296  #define GMBUS4			_MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
f899fc64cda8569 Chris Wilson                  2010-07-20   3297  #define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
f899fc64cda8569 Chris Wilson                  2010-07-20   3298  #define   GMBUS_NAK_EN		(1 << 3)
f899fc64cda8569 Chris Wilson                  2010-07-20   3299  #define   GMBUS_IDLE_EN		(1 << 2)
f899fc64cda8569 Chris Wilson                  2010-07-20   3300  #define   GMBUS_HW_WAIT_EN	(1 << 1)
f899fc64cda8569 Chris Wilson                  2010-07-20   3301  #define   GMBUS_HW_RDY_EN	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3302  #define GMBUS5			_MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
f899fc64cda8569 Chris Wilson                  2010-07-20   3303  #define   GMBUS_2BYTE_INDEX_EN	(1 << 31)
f0217c42c9ab3d7 Eric Anholt                   2009-12-01   3304  
585fb111348f7cd Jesse Barnes                  2008-07-29   3305  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3306   * Clock control & power management
585fb111348f7cd Jesse Barnes                  2008-07-29   3307   */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3308  #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3309  #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3310  #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3311  #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
585fb111348f7cd Jesse Barnes                  2008-07-29   3312  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3313  #define VGA0	_MMIO(0x6000)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3314  #define VGA1	_MMIO(0x6004)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3315  #define VGA_PD	_MMIO(0x6010)
585fb111348f7cd Jesse Barnes                  2008-07-29   3316  #define   VGA0_PD_P2_DIV_4	(1 << 7)
585fb111348f7cd Jesse Barnes                  2008-07-29   3317  #define   VGA0_PD_P1_DIV_2	(1 << 5)
585fb111348f7cd Jesse Barnes                  2008-07-29   3318  #define   VGA0_PD_P1_SHIFT	0
585fb111348f7cd Jesse Barnes                  2008-07-29   3319  #define   VGA0_PD_P1_MASK	(0x1f << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   3320  #define   VGA1_PD_P2_DIV_4	(1 << 15)
585fb111348f7cd Jesse Barnes                  2008-07-29   3321  #define   VGA1_PD_P1_DIV_2	(1 << 13)
585fb111348f7cd Jesse Barnes                  2008-07-29   3322  #define   VGA1_PD_P1_SHIFT	8
585fb111348f7cd Jesse Barnes                  2008-07-29   3323  #define   VGA1_PD_P1_MASK	(0x1f << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   3324  #define   DPLL_VCO_ENABLE		(1 << 31)
4a33e48d0e12195 Daniel Vetter                 2013-07-06   3325  #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
4a33e48d0e12195 Daniel Vetter                 2013-07-06   3326  #define   DPLL_DVO_2X_MODE		(1 << 30)
25eb05fc5ac7a43 Jesse Barnes                  2012-03-28   3327  #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   3328  #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
60bfe44f83c0a9d Ville Syrjälä                 2015-06-29   3329  #define   DPLL_REF_CLK_ENABLE_VLV	(1 << 29)
585fb111348f7cd Jesse Barnes                  2008-07-29   3330  #define   DPLL_VGA_MODE_DIS		(1 << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   3331  #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3332  #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3333  #define   DPLL_MODE_MASK		(3 << 26)
585fb111348f7cd Jesse Barnes                  2008-07-29   3334  #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3335  #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3336  #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3337  #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3338  #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3339  #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
f2b115e69d46344 Adam Jackson                  2009-12-03   3340  #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
a0c4da24eafb32a Jesse Barnes                  2012-06-15   3341  #define   DPLL_LOCK_VLV			(1 << 15)
598fac6bf8299ed Daniel Vetter                 2013-04-18   3342  #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1 << 14)
60bfe44f83c0a9d Ville Syrjälä                 2015-06-29   3343  #define   DPLL_INTEGRATED_REF_CLK_VLV	(1 << 13)
60bfe44f83c0a9d Ville Syrjälä                 2015-06-29   3344  #define   DPLL_SSC_REF_CLK_CHV		(1 << 13)
598fac6bf8299ed Daniel Vetter                 2013-04-18   3345  #define   DPLL_PORTC_READY_MASK		(0xf << 4)
598fac6bf8299ed Daniel Vetter                 2013-04-18   3346  #define   DPLL_PORTB_READY_MASK		(0xf)
585fb111348f7cd Jesse Barnes                  2008-07-29   3347  
585fb111348f7cd Jesse Barnes                  2008-07-29   3348  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
00fc31b72ea773f Chon Ming Lee                 2014-04-09   3349  
00fc31b72ea773f Chon Ming Lee                 2014-04-09   3350  /* Additional CHV pll/phy registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3351  #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
00fc31b72ea773f Chon Ming Lee                 2014-04-09   3352  #define   DPLL_PORTD_READY_MASK		(0xf)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3353  #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
e0fce78f0410148 Ville Syrjälä                 2015-07-08   3354  #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2 * (phy) + (ch) + 27))
bc284542dad8804 Ville Syrjälä                 2015-05-26   3355  #define   PHY_LDO_DELAY_0NS			0x0
bc284542dad8804 Ville Syrjälä                 2015-05-26   3356  #define   PHY_LDO_DELAY_200NS			0x1
bc284542dad8804 Ville Syrjälä                 2015-05-26   3357  #define   PHY_LDO_DELAY_600NS			0x2
bc284542dad8804 Ville Syrjälä                 2015-05-26   3358  #define   PHY_LDO_SEQ_DELAY(delay, phy)		((delay) << (2 * (phy) + 23))
e0fce78f0410148 Ville Syrjälä                 2015-07-08   3359  #define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)	((mask) << (8 * (phy) + 4 * (ch) + 11))
70722468872b075 Ville Syrjälä                 2015-04-10   3360  #define   PHY_CH_SU_PSR				0x1
70722468872b075 Ville Syrjälä                 2015-04-10   3361  #define   PHY_CH_DEEP_PSR			0x7
70722468872b075 Ville Syrjälä                 2015-04-10   3362  #define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6 * (phy) + 3 * (ch) + 2))
efd814b73cfcf4e Ville Syrjälä                 2014-06-27   3363  #define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3364  #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
efd814b73cfcf4e Ville Syrjälä                 2014-06-27   3365  #define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
30142273a3e8393 Ville Syrjälä                 2015-07-08   3366  #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6 - (6 * (phy) + 3 * (ch))))
30142273a3e8393 Ville Syrjälä                 2015-07-08   3367  #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
076ed3b2955e593 Chon Ming Lee                 2014-04-09   3368  
585fb111348f7cd Jesse Barnes                  2008-07-29   3369  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3370   * The i830 generation, in LVDS mode, defines P1 as the bit number set within
585fb111348f7cd Jesse Barnes                  2008-07-29   3371   * this field (only one bit may be set).
585fb111348f7cd Jesse Barnes                  2008-07-29   3372   */
585fb111348f7cd Jesse Barnes                  2008-07-29   3373  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   3374  #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
f2b115e69d46344 Adam Jackson                  2009-12-03   3375  #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
585fb111348f7cd Jesse Barnes                  2008-07-29   3376  /* i830, required in DVO non-gang */
585fb111348f7cd Jesse Barnes                  2008-07-29   3377  #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
585fb111348f7cd Jesse Barnes                  2008-07-29   3378  #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3379  #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
585fb111348f7cd Jesse Barnes                  2008-07-29   3380  #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
585fb111348f7cd Jesse Barnes                  2008-07-29   3381  #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
585fb111348f7cd Jesse Barnes                  2008-07-29   3382  #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
585fb111348f7cd Jesse Barnes                  2008-07-29   3383  #define   PLL_REF_INPUT_MASK		(3 << 13)
585fb111348f7cd Jesse Barnes                  2008-07-29   3384  #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
f2b115e69d46344 Adam Jackson                  2009-12-03   3385  /* Ironlake */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   3386  # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
b9055052d3e0388 Zhenyu Wang                   2009-06-05   3387  # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   3388  # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x) - 1) << 9)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   3389  # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
b9055052d3e0388 Zhenyu Wang                   2009-06-05   3390  # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
b9055052d3e0388 Zhenyu Wang                   2009-06-05   3391  
585fb111348f7cd Jesse Barnes                  2008-07-29   3392  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3393   * Parallel to Serial Load Pulse phase selection.
585fb111348f7cd Jesse Barnes                  2008-07-29   3394   * Selects the phase for the 10X DPLL clock for the PCIe
585fb111348f7cd Jesse Barnes                  2008-07-29   3395   * digital display port. The range is 4 to 13; 10 or more
585fb111348f7cd Jesse Barnes                  2008-07-29   3396   * is just a flip delay. The default is 6
585fb111348f7cd Jesse Barnes                  2008-07-29   3397   */
585fb111348f7cd Jesse Barnes                  2008-07-29   3398  #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
585fb111348f7cd Jesse Barnes                  2008-07-29   3399  #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   3400  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3401   * SDVO multiplier for 945G/GM. Not used on 965.
585fb111348f7cd Jesse Barnes                  2008-07-29   3402   */
585fb111348f7cd Jesse Barnes                  2008-07-29   3403  #define   SDVO_MULTIPLIER_MASK			0x000000ff
585fb111348f7cd Jesse Barnes                  2008-07-29   3404  #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
585fb111348f7cd Jesse Barnes                  2008-07-29   3405  #define   SDVO_MULTIPLIER_SHIFT_VGA		0
a57c774ab2b849b Antti Koskipaa                2014-02-04   3406  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3407  #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3408  #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3409  #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3410  #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
a57c774ab2b849b Antti Koskipaa                2014-02-04   3411  
585fb111348f7cd Jesse Barnes                  2008-07-29   3412  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3413   * UDI pixel divider, controlling how many pixels are stuffed into a packet.
585fb111348f7cd Jesse Barnes                  2008-07-29   3414   *
585fb111348f7cd Jesse Barnes                  2008-07-29   3415   * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
585fb111348f7cd Jesse Barnes                  2008-07-29   3416   */
585fb111348f7cd Jesse Barnes                  2008-07-29   3417  #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
585fb111348f7cd Jesse Barnes                  2008-07-29   3418  #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
585fb111348f7cd Jesse Barnes                  2008-07-29   3419  /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
585fb111348f7cd Jesse Barnes                  2008-07-29   3420  #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   3421  #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
585fb111348f7cd Jesse Barnes                  2008-07-29   3422  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3423   * SDVO/UDI pixel multiplier.
585fb111348f7cd Jesse Barnes                  2008-07-29   3424   *
585fb111348f7cd Jesse Barnes                  2008-07-29   3425   * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
585fb111348f7cd Jesse Barnes                  2008-07-29   3426   * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
585fb111348f7cd Jesse Barnes                  2008-07-29   3427   * modes, the bus rate would be below the limits, so SDVO allows for stuffing
585fb111348f7cd Jesse Barnes                  2008-07-29   3428   * dummy bytes in the datastream at an increased clock rate, with both sides of
585fb111348f7cd Jesse Barnes                  2008-07-29   3429   * the link knowing how many bytes are fill.
585fb111348f7cd Jesse Barnes                  2008-07-29   3430   *
585fb111348f7cd Jesse Barnes                  2008-07-29   3431   * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
585fb111348f7cd Jesse Barnes                  2008-07-29   3432   * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
585fb111348f7cd Jesse Barnes                  2008-07-29   3433   * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
585fb111348f7cd Jesse Barnes                  2008-07-29   3434   * through an SDVO command.
585fb111348f7cd Jesse Barnes                  2008-07-29   3435   *
585fb111348f7cd Jesse Barnes                  2008-07-29   3436   * This register field has values of multiplication factor minus 1, with
585fb111348f7cd Jesse Barnes                  2008-07-29   3437   * a maximum multiplier of 5 for SDVO.
585fb111348f7cd Jesse Barnes                  2008-07-29   3438   */
585fb111348f7cd Jesse Barnes                  2008-07-29   3439  #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
585fb111348f7cd Jesse Barnes                  2008-07-29   3440  #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
585fb111348f7cd Jesse Barnes                  2008-07-29   3441  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3442   * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
585fb111348f7cd Jesse Barnes                  2008-07-29   3443   * This best be set to the default value (3) or the CRT won't work. No,
585fb111348f7cd Jesse Barnes                  2008-07-29   3444   * I don't entirely understand what this does...
585fb111348f7cd Jesse Barnes                  2008-07-29   3445   */
585fb111348f7cd Jesse Barnes                  2008-07-29   3446  #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
585fb111348f7cd Jesse Barnes                  2008-07-29   3447  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
25eb05fc5ac7a43 Jesse Barnes                  2012-03-28   3448  
19ab4ed329393c0 Ville Syrjälä                 2016-04-27   3449  #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
19ab4ed329393c0 Ville Syrjälä                 2016-04-27   3450  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3451  #define _FPA0	0x6040
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3452  #define _FPA1	0x6044
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3453  #define _FPB0	0x6048
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3454  #define _FPB1	0x604c
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3455  #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3456  #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
585fb111348f7cd Jesse Barnes                  2008-07-29   3457  #define   FP_N_DIV_MASK		0x003f0000
f2b115e69d46344 Adam Jackson                  2009-12-03   3458  #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   3459  #define   FP_N_DIV_SHIFT		16
585fb111348f7cd Jesse Barnes                  2008-07-29   3460  #define   FP_M1_DIV_MASK	0x00003f00
585fb111348f7cd Jesse Barnes                  2008-07-29   3461  #define   FP_M1_DIV_SHIFT		 8
585fb111348f7cd Jesse Barnes                  2008-07-29   3462  #define   FP_M2_DIV_MASK	0x0000003f
f2b115e69d46344 Adam Jackson                  2009-12-03   3463  #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
585fb111348f7cd Jesse Barnes                  2008-07-29   3464  #define   FP_M2_DIV_SHIFT		 0
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3465  #define DPLL_TEST	_MMIO(0x606c)
585fb111348f7cd Jesse Barnes                  2008-07-29   3466  #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
585fb111348f7cd Jesse Barnes                  2008-07-29   3467  #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
585fb111348f7cd Jesse Barnes                  2008-07-29   3468  #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
585fb111348f7cd Jesse Barnes                  2008-07-29   3469  #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
585fb111348f7cd Jesse Barnes                  2008-07-29   3470  #define   DPLLB_TEST_N_BYPASS		(1 << 19)
585fb111348f7cd Jesse Barnes                  2008-07-29   3471  #define   DPLLB_TEST_M_BYPASS		(1 << 18)
585fb111348f7cd Jesse Barnes                  2008-07-29   3472  #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
585fb111348f7cd Jesse Barnes                  2008-07-29   3473  #define   DPLLA_TEST_N_BYPASS		(1 << 3)
585fb111348f7cd Jesse Barnes                  2008-07-29   3474  #define   DPLLA_TEST_M_BYPASS		(1 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   3475  #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3476  #define D_STATE		_MMIO(0x6104)
dc96e9b8e37641d Chris Wilson                  2010-10-01   3477  #define  DSTATE_GFX_RESET_I830			(1 << 6)
652c393a3368af8 Jesse Barnes                  2009-08-17   3478  #define  DSTATE_PLL_D3_OFF			(1 << 3)
652c393a3368af8 Jesse Barnes                  2009-08-17   3479  #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
652c393a3368af8 Jesse Barnes                  2009-08-17   3480  #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3481  #define DSPCLK_GATE_D	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
652c393a3368af8 Jesse Barnes                  2009-08-17   3482  # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3483  # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3484  # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3485  # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3486  # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3487  # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3488  # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
ad8059cf2e33042 Ville Syrjälä                 2017-12-08   3489  # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
652c393a3368af8 Jesse Barnes                  2009-08-17   3490  # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3491  # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3492  # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3493  # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3494  # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3495  # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3496  # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3497  # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3498  # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3499  # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3500  # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3501  # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3502  # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
652c393a3368af8 Jesse Barnes                  2009-08-17   3503  # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
652c393a3368af8 Jesse Barnes                  2009-08-17   3504  # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
652c393a3368af8 Jesse Barnes                  2009-08-17   3505  # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
652c393a3368af8 Jesse Barnes                  2009-08-17   3506  # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
652c393a3368af8 Jesse Barnes                  2009-08-17   3507  # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3508  # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3509  # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
652c393a3368af8 Jesse Barnes                  2009-08-17   3510  # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3511  /*
652c393a3368af8 Jesse Barnes                  2009-08-17   3512   * This bit must be set on the 830 to prevent hangs when turning off the
652c393a3368af8 Jesse Barnes                  2009-08-17   3513   * overlay scaler.
652c393a3368af8 Jesse Barnes                  2009-08-17   3514   */
652c393a3368af8 Jesse Barnes                  2009-08-17   3515  # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
652c393a3368af8 Jesse Barnes                  2009-08-17   3516  # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
652c393a3368af8 Jesse Barnes                  2009-08-17   3517  # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
652c393a3368af8 Jesse Barnes                  2009-08-17   3518  # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3519  # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3520  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3521  #define RENCLK_GATE_D1		_MMIO(0x6204)
652c393a3368af8 Jesse Barnes                  2009-08-17   3522  # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
652c393a3368af8 Jesse Barnes                  2009-08-17   3523  # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
652c393a3368af8 Jesse Barnes                  2009-08-17   3524  # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
652c393a3368af8 Jesse Barnes                  2009-08-17   3525  # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
652c393a3368af8 Jesse Barnes                  2009-08-17   3526  # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
652c393a3368af8 Jesse Barnes                  2009-08-17   3527  # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
652c393a3368af8 Jesse Barnes                  2009-08-17   3528  # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
652c393a3368af8 Jesse Barnes                  2009-08-17   3529  # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
652c393a3368af8 Jesse Barnes                  2009-08-17   3530  # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3531  /* This bit must be unset on 855,865 */
652c393a3368af8 Jesse Barnes                  2009-08-17   3532  # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
652c393a3368af8 Jesse Barnes                  2009-08-17   3533  # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
652c393a3368af8 Jesse Barnes                  2009-08-17   3534  # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
652c393a3368af8 Jesse Barnes                  2009-08-17   3535  # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3536  /* This bit must be set on 855,865. */
652c393a3368af8 Jesse Barnes                  2009-08-17   3537  # define SV_CLOCK_GATE_DISABLE			(1 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17   3538  # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
652c393a3368af8 Jesse Barnes                  2009-08-17   3539  # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
652c393a3368af8 Jesse Barnes                  2009-08-17   3540  # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
652c393a3368af8 Jesse Barnes                  2009-08-17   3541  # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
652c393a3368af8 Jesse Barnes                  2009-08-17   3542  # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
652c393a3368af8 Jesse Barnes                  2009-08-17   3543  # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
652c393a3368af8 Jesse Barnes                  2009-08-17   3544  # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
652c393a3368af8 Jesse Barnes                  2009-08-17   3545  # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
652c393a3368af8 Jesse Barnes                  2009-08-17   3546  # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
652c393a3368af8 Jesse Barnes                  2009-08-17   3547  # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
652c393a3368af8 Jesse Barnes                  2009-08-17   3548  # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
652c393a3368af8 Jesse Barnes                  2009-08-17   3549  # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
652c393a3368af8 Jesse Barnes                  2009-08-17   3550  # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
652c393a3368af8 Jesse Barnes                  2009-08-17   3551  # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
652c393a3368af8 Jesse Barnes                  2009-08-17   3552  # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
652c393a3368af8 Jesse Barnes                  2009-08-17   3553  # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
652c393a3368af8 Jesse Barnes                  2009-08-17   3554  # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17   3555  
652c393a3368af8 Jesse Barnes                  2009-08-17   3556  # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3557  /* This bit must always be set on 965G/965GM */
652c393a3368af8 Jesse Barnes                  2009-08-17   3558  # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
652c393a3368af8 Jesse Barnes                  2009-08-17   3559  # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
652c393a3368af8 Jesse Barnes                  2009-08-17   3560  # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
652c393a3368af8 Jesse Barnes                  2009-08-17   3561  # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
652c393a3368af8 Jesse Barnes                  2009-08-17   3562  # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
652c393a3368af8 Jesse Barnes                  2009-08-17   3563  # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3564  /* This bit must always be set on 965G */
652c393a3368af8 Jesse Barnes                  2009-08-17   3565  # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
652c393a3368af8 Jesse Barnes                  2009-08-17   3566  # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
652c393a3368af8 Jesse Barnes                  2009-08-17   3567  # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
652c393a3368af8 Jesse Barnes                  2009-08-17   3568  # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
652c393a3368af8 Jesse Barnes                  2009-08-17   3569  # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
652c393a3368af8 Jesse Barnes                  2009-08-17   3570  # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
652c393a3368af8 Jesse Barnes                  2009-08-17   3571  # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
652c393a3368af8 Jesse Barnes                  2009-08-17   3572  # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
652c393a3368af8 Jesse Barnes                  2009-08-17   3573  # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
652c393a3368af8 Jesse Barnes                  2009-08-17   3574  # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
652c393a3368af8 Jesse Barnes                  2009-08-17   3575  # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
652c393a3368af8 Jesse Barnes                  2009-08-17   3576  # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
652c393a3368af8 Jesse Barnes                  2009-08-17   3577  # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
652c393a3368af8 Jesse Barnes                  2009-08-17   3578  # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
652c393a3368af8 Jesse Barnes                  2009-08-17   3579  # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
652c393a3368af8 Jesse Barnes                  2009-08-17   3580  # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
652c393a3368af8 Jesse Barnes                  2009-08-17   3581  # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
652c393a3368af8 Jesse Barnes                  2009-08-17   3582  # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
652c393a3368af8 Jesse Barnes                  2009-08-17   3583  # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
652c393a3368af8 Jesse Barnes                  2009-08-17   3584  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3585  #define RENCLK_GATE_D2		_MMIO(0x6208)
652c393a3368af8 Jesse Barnes                  2009-08-17   3586  #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
652c393a3368af8 Jesse Barnes                  2009-08-17   3587  #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
652c393a3368af8 Jesse Barnes                  2009-08-17   3588  #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
fa4f53c4416de49 Ville Syrjälä                 2014-05-19   3589  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3590  #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
fa4f53c4416de49 Ville Syrjälä                 2014-05-19   3591  #define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
fa4f53c4416de49 Ville Syrjälä                 2014-05-19   3592  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3593  #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3594  #define DEUC			_MMIO(0x6214)          /* CRL only */
585fb111348f7cd Jesse Barnes                  2008-07-29   3595  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3596  #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
ceb042468763db2 Jesse Barnes                  2012-03-28   3597  #define  FW_CSPWRDWNEN		(1 << 15)
ceb042468763db2 Jesse Barnes                  2012-03-28   3598  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3599  #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
e0d8d59b0831523 Ville Syrjälä                 2013-06-12   3600  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3601  #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
24eb2d599b6a2bf Chon Ming Lee                 2013-09-27   3602  #define   CDCLK_FREQ_SHIFT	4
24eb2d599b6a2bf Chon Ming Lee                 2013-09-27   3603  #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
24eb2d599b6a2bf Chon Ming Lee                 2013-09-27   3604  #define   CZCLK_FREQ_MASK	0xf
1e69cd74af22cce Vidya Srinivas                2015-03-05   3605  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3606  #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
1e69cd74af22cce Vidya Srinivas                2015-03-05   3607  #define   PFI_CREDIT_63		(9 << 28)		/* chv only */
1e69cd74af22cce Vidya Srinivas                2015-03-05   3608  #define   PFI_CREDIT_31		(8 << 28)		/* chv only */
1e69cd74af22cce Vidya Srinivas                2015-03-05   3609  #define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
1e69cd74af22cce Vidya Srinivas                2015-03-05   3610  #define   PFI_CREDIT_RESEND	(1 << 27)
1e69cd74af22cce Vidya Srinivas                2015-03-05   3611  #define   VGA_FAST_MODE_DISABLE	(1 << 14)
1e69cd74af22cce Vidya Srinivas                2015-03-05   3612  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3613  #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
24eb2d599b6a2bf Chon Ming Lee                 2013-09-27   3614  
585fb111348f7cd Jesse Barnes                  2008-07-29   3615  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   3616   * Palette regs
585fb111348f7cd Jesse Barnes                  2008-07-29   3617   */
74c1e826427ae59 Jani Nikula                   2018-10-31   3618  #define _PALETTE_A		0xa000
74c1e826427ae59 Jani Nikula                   2018-10-31   3619  #define _PALETTE_B		0xa800
74c1e826427ae59 Jani Nikula                   2018-10-31   3620  #define _CHV_PALETTE_C		0xc000
ed5eb1b78a88302 Jani Nikula                   2018-12-31   3621  #define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
74c1e826427ae59 Jani Nikula                   2018-10-31   3622  				      _PICK((pipe), _PALETTE_A,		\
74c1e826427ae59 Jani Nikula                   2018-10-31   3623  					    _PALETTE_B, _CHV_PALETTE_C) + \
74c1e826427ae59 Jani Nikula                   2018-10-31   3624  				      (i) * 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   3625  
673a394b1e3b69b Eric Anholt                   2008-07-30   3626  /* MCH MMIO space */
673a394b1e3b69b Eric Anholt                   2008-07-30   3627  
673a394b1e3b69b Eric Anholt                   2008-07-30   3628  /*
673a394b1e3b69b Eric Anholt                   2008-07-30   3629   * MCHBAR mirror.
673a394b1e3b69b Eric Anholt                   2008-07-30   3630   *
673a394b1e3b69b Eric Anholt                   2008-07-30   3631   * This mirrors the MCHBAR MMIO space whose location is determined by
673a394b1e3b69b Eric Anholt                   2008-07-30   3632   * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
673a394b1e3b69b Eric Anholt                   2008-07-30   3633   * every way.  It is not accessible from the CP register read instructions.
673a394b1e3b69b Eric Anholt                   2008-07-30   3634   *
515b239269fb67f Paulo Zanoni                  2013-09-10   3635   * Starting from Haswell, you can't write registers using the MCHBAR mirror,
515b239269fb67f Paulo Zanoni                  2013-09-10   3636   * just read.
673a394b1e3b69b Eric Anholt                   2008-07-30   3637   */
673a394b1e3b69b Eric Anholt                   2008-07-30   3638  #define MCHBAR_MIRROR_BASE	0x10000
673a394b1e3b69b Eric Anholt                   2008-07-30   3639  
1398261a2e84c53 Yuanhan Liu                   2010-12-15   3640  #define MCHBAR_MIRROR_BASE_SNB	0x140000
1398261a2e84c53 Yuanhan Liu                   2010-12-15   3641  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3642  #define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3643  #define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
7d316aecf883a19 Ville Syrjälä                 2015-09-16   3644  #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
7d316aecf883a19 Ville Syrjälä                 2015-09-16   3645  #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
db7fb60593e4282 Ville Syrjälä                 2017-11-02   3646  #define G4X_STOLEN_RESERVED_ENABLE	(1 << 0)
7d316aecf883a19 Ville Syrjälä                 2015-09-16   3647  
3ebecd07d382c02 Chris Wilson                  2013-04-12   3648  /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3649  #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3ebecd07d382c02 Chris Wilson                  2013-04-12   3650  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3651  /* 915-945 and GM965 MCH register controlling DRAM channel access */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3652  #define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
673a394b1e3b69b Eric Anholt                   2008-07-30   3653  #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
673a394b1e3b69b Eric Anholt                   2008-07-30   3654  #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
673a394b1e3b69b Eric Anholt                   2008-07-30   3655  #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
673a394b1e3b69b Eric Anholt                   2008-07-30   3656  #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
673a394b1e3b69b Eric Anholt                   2008-07-30   3657  #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
a7f014f2de04893 Eric Anholt                   2008-11-25   3658  #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3659  #define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
656bfa3afc14e45 Daniel Vetter                 2014-11-20   3660  #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
673a394b1e3b69b Eric Anholt                   2008-07-30   3661  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3662  /* Pineview MCH register contains DDR3 setting */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3663  #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
9553426372eef71 Li Peng                       2010-05-18   3664  #define CSHRDDR3CTL_DDR3       (1 << 2)
9553426372eef71 Li Peng                       2010-05-18   3665  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3666  /* 965 MCH register controlling DRAM channel configuration */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3667  #define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3668  #define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)
673a394b1e3b69b Eric Anholt                   2008-07-30   3669  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3670  /* snb MCH registers for reading the DRAM channel configuration */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3671  #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3672  #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3673  #define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3674  #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3675  #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3676  #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3677  #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3678  #define   MAD_DIMM_ECC_ON		(0x3 << 24)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3679  #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3680  #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3681  #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
f691e2f4cec334e Daniel Vetter                 2012-02-02   3682  #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
f691e2f4cec334e Daniel Vetter                 2012-02-02   3683  #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3684  #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3685  #define   MAD_DIMM_A_SELECT		(0x1 << 16)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3686  /* DIMM sizes are in multiples of 256mb. */
f691e2f4cec334e Daniel Vetter                 2012-02-02   3687  #define   MAD_DIMM_B_SIZE_SHIFT		8
f691e2f4cec334e Daniel Vetter                 2012-02-02   3688  #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3689  #define   MAD_DIMM_A_SIZE_SHIFT		0
f691e2f4cec334e Daniel Vetter                 2012-02-02   3690  #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
f691e2f4cec334e Daniel Vetter                 2012-02-02   3691  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   3692  /* snb MCH registers for priority tuning */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3693  #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1d7aaa0cfe3d1b5 Daniel Vetter                 2013-02-09   3694  #define   MCH_SSKPD_WM0_MASK		0x3f
1d7aaa0cfe3d1b5 Daniel Vetter                 2013-02-09   3695  #define   MCH_SSKPD_WM0_VAL		0xc
f691e2f4cec334e Daniel Vetter                 2012-02-02   3696  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3697  #define MCH_SECP_NRG_STTS		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
ec013e7f491ccee Jesse Barnes                  2013-08-20   3698  
b11248df4c0decb Keith Packard                 2009-06-11   3699  /* Clocking configuration register */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3700  #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
7662c8bd6545c12 Shaohua Li                    2009-06-26   3701  #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
b11248df4c0decb Keith Packard                 2009-06-11   3702  #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
b11248df4c0decb Keith Packard                 2009-06-11   3703  #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
b11248df4c0decb Keith Packard                 2009-06-11   3704  #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
b11248df4c0decb Keith Packard                 2009-06-11   3705  #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
6f38123ecaac446 Ville Syrjälä                 2017-05-04   3706  #define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */
b11248df4c0decb Keith Packard                 2009-06-11   3707  #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
6f38123ecaac446 Ville Syrjälä                 2017-05-04   3708  /*
6f38123ecaac446 Ville Syrjälä                 2017-05-04   3709   * Note that on at least on ELK the below value is reported for both
6f38123ecaac446 Ville Syrjälä                 2017-05-04   3710   * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
6f38123ecaac446 Ville Syrjälä                 2017-05-04   3711   * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
6f38123ecaac446 Ville Syrjälä                 2017-05-04   3712   */
6f38123ecaac446 Ville Syrjälä                 2017-05-04   3713  #define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */
b11248df4c0decb Keith Packard                 2009-06-11   3714  #define CLKCFG_FSB_MASK					(7 << 0)
7662c8bd6545c12 Shaohua Li                    2009-06-26   3715  #define CLKCFG_MEM_533					(1 << 4)
7662c8bd6545c12 Shaohua Li                    2009-06-26   3716  #define CLKCFG_MEM_667					(2 << 4)
7662c8bd6545c12 Shaohua Li                    2009-06-26   3717  #define CLKCFG_MEM_800					(3 << 4)
7662c8bd6545c12 Shaohua Li                    2009-06-26   3718  #define CLKCFG_MEM_MASK					(7 << 4)
b11248df4c0decb Keith Packard                 2009-06-11   3719  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3720  #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3721  #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
34edce2fea6960c Ville Syrjälä                 2015-05-22   3722  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3723  #define TSC1			_MMIO(0x11001)
ea056c14a269be3 Jesse Barnes                  2010-09-10   3724  #define   TSE			(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3725  #define TR1			_MMIO(0x11006)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3726  #define TSFS			_MMIO(0x11020)
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3727  #define   TSFS_SLOPE_MASK	0x0000ff00
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3728  #define   TSFS_SLOPE_SHIFT	8
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3729  #define   TSFS_INTR_MASK	0x000000ff
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3730  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3731  #define CRSTANDVID		_MMIO(0x11100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3732  #define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3733  #define   PXVFREQ_PX_MASK	0x7f000000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3734  #define   PXVFREQ_PX_SHIFT	24
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3735  #define VIDFREQ_BASE		_MMIO(0x11110)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3736  #define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3737  #define VIDFREQ2		_MMIO(0x11114)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3738  #define VIDFREQ3		_MMIO(0x11118)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3739  #define VIDFREQ4		_MMIO(0x1111c)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3740  #define   VIDFREQ_P0_MASK	0x1f000000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3741  #define   VIDFREQ_P0_SHIFT	24
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3742  #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3743  #define   VIDFREQ_P0_CSCLK_SHIFT 20
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3744  #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3745  #define   VIDFREQ_P0_CRCLK_SHIFT 16
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3746  #define   VIDFREQ_P1_MASK	0x00001f00
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3747  #define   VIDFREQ_P1_SHIFT	8
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3748  #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3749  #define   VIDFREQ_P1_CSCLK_SHIFT 4
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3750  #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3751  #define INTTOEXT_BASE_ILK	_MMIO(0x11300)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3752  #define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3753  #define   INTTOEXT_MAP3_SHIFT	24
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3754  #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3755  #define   INTTOEXT_MAP2_SHIFT	16
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3756  #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3757  #define   INTTOEXT_MAP1_SHIFT	8
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3758  #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3759  #define   INTTOEXT_MAP0_SHIFT	0
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3760  #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3761  #define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3762  #define   MEMCTL_CMD_MASK	0xe000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3763  #define   MEMCTL_CMD_SHIFT	13
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3764  #define   MEMCTL_CMD_RCLK_OFF	0
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3765  #define   MEMCTL_CMD_RCLK_ON	1
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3766  #define   MEMCTL_CMD_CHFREQ	2
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3767  #define   MEMCTL_CMD_CHVID	3
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3768  #define   MEMCTL_CMD_VMMOFF	4
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3769  #define   MEMCTL_CMD_VMMON	5
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3770  #define   MEMCTL_CMD_STS	(1 << 12) /* write 1 triggers command, clears
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3771  					   when command complete */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3772  #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3773  #define   MEMCTL_FREQ_SHIFT	8
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3774  #define   MEMCTL_SFCAVM		(1 << 7)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3775  #define   MEMCTL_TGT_VID_MASK	0x007f
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3776  #define MEMIHYST		_MMIO(0x1117c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3777  #define MEMINTREN		_MMIO(0x11180) /* 16 bits */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3778  #define   MEMINT_RSEXIT_EN	(1 << 8)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3779  #define   MEMINT_CX_SUPR_EN	(1 << 7)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3780  #define   MEMINT_CONT_BUSY_EN	(1 << 6)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3781  #define   MEMINT_AVG_BUSY_EN	(1 << 5)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3782  #define   MEMINT_EVAL_CHG_EN	(1 << 4)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3783  #define   MEMINT_MON_IDLE_EN	(1 << 3)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3784  #define   MEMINT_UP_EVAL_EN	(1 << 2)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3785  #define   MEMINT_DOWN_EVAL_EN	(1 << 1)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3786  #define   MEMINT_SW_CMD_EN	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3787  #define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3788  #define   MEM_RSEXIT_MASK	0xc000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3789  #define   MEM_RSEXIT_SHIFT	14
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3790  #define   MEM_CONT_BUSY_MASK	0x3000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3791  #define   MEM_CONT_BUSY_SHIFT	12
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3792  #define   MEM_AVG_BUSY_MASK	0x0c00
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3793  #define   MEM_AVG_BUSY_SHIFT	10
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3794  #define   MEM_EVAL_CHG_MASK	0x0300
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3795  #define   MEM_EVAL_BUSY_SHIFT	8
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3796  #define   MEM_MON_IDLE_MASK	0x00c0
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3797  #define   MEM_MON_IDLE_SHIFT	6
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3798  #define   MEM_UP_EVAL_MASK	0x0030
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3799  #define   MEM_UP_EVAL_SHIFT	4
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3800  #define   MEM_DOWN_EVAL_MASK	0x000c
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3801  #define   MEM_DOWN_EVAL_SHIFT	2
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3802  #define   MEM_SW_CMD_MASK	0x0003
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3803  #define   MEM_INT_STEER_GFX	0
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3804  #define   MEM_INT_STEER_CMR	1
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3805  #define   MEM_INT_STEER_SMI	2
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3806  #define   MEM_INT_STEER_SCI	3
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3807  #define MEMINTRSTS		_MMIO(0x11184)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3808  #define   MEMINT_RSEXIT		(1 << 7)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3809  #define   MEMINT_CONT_BUSY	(1 << 6)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3810  #define   MEMINT_AVG_BUSY	(1 << 5)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3811  #define   MEMINT_EVAL_CHG	(1 << 4)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3812  #define   MEMINT_MON_IDLE	(1 << 3)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3813  #define   MEMINT_UP_EVAL	(1 << 2)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3814  #define   MEMINT_DOWN_EVAL	(1 << 1)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3815  #define   MEMINT_SW_CMD		(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3816  #define MEMMODECTL		_MMIO(0x11190)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3817  #define   MEMMODE_BOOST_EN	(1 << 31)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3818  #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3819  #define   MEMMODE_BOOST_FREQ_SHIFT 24
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3820  #define   MEMMODE_IDLE_MODE_MASK 0x00030000
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3821  #define   MEMMODE_IDLE_MODE_SHIFT 16
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3822  #define   MEMMODE_IDLE_MODE_EVAL 0
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3823  #define   MEMMODE_IDLE_MODE_CONT 1
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3824  #define   MEMMODE_HWIDLE_EN	(1 << 15)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3825  #define   MEMMODE_SWMODE_EN	(1 << 14)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3826  #define   MEMMODE_RCLK_GATE	(1 << 13)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3827  #define   MEMMODE_HW_UPDATE	(1 << 12)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3828  #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3829  #define   MEMMODE_FSTART_SHIFT	8
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3830  #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3831  #define   MEMMODE_FMAX_SHIFT	4
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3832  #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3833  #define RCBMAXAVG		_MMIO(0x1119c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3834  #define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3835  #define   SWMEMCMD_RENDER_OFF	(0 << 13)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3836  #define   SWMEMCMD_RENDER_ON	(1 << 13)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3837  #define   SWMEMCMD_SWFREQ	(2 << 13)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3838  #define   SWMEMCMD_TARVID	(3 << 13)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3839  #define   SWMEMCMD_VRM_OFF	(4 << 13)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3840  #define   SWMEMCMD_VRM_ON	(5 << 13)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3841  #define   CMDSTS		(1 << 12)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3842  #define   SFCAVM		(1 << 11)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3843  #define   SWFREQ_MASK		0x0380 /* P0-7 */
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3844  #define   SWFREQ_SHIFT		7
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3845  #define   TARVID_MASK		0x001f
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3846  #define MEMSTAT_CTG		_MMIO(0x111a0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3847  #define RCBMINAVG		_MMIO(0x111a0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3848  #define RCUPEI			_MMIO(0x111b0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3849  #define RCDNEI			_MMIO(0x111b4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3850  #define RSTDBYCTL		_MMIO(0x111b8)
88271da3f3da75d Jesse Barnes                  2011-01-05   3851  #define   RS1EN			(1 << 31)
88271da3f3da75d Jesse Barnes                  2011-01-05   3852  #define   RS2EN			(1 << 30)
88271da3f3da75d Jesse Barnes                  2011-01-05   3853  #define   RS3EN			(1 << 29)
88271da3f3da75d Jesse Barnes                  2011-01-05   3854  #define   D3RS3EN		(1 << 28) /* Display D3 imlies RS3 */
88271da3f3da75d Jesse Barnes                  2011-01-05   3855  #define   SWPROMORSX		(1 << 27) /* RSx promotion timers ignored */
88271da3f3da75d Jesse Barnes                  2011-01-05   3856  #define   RCWAKERW		(1 << 26) /* Resetwarn from PCH causes wakeup */
88271da3f3da75d Jesse Barnes                  2011-01-05   3857  #define   DPRSLPVREN		(1 << 25) /* Fast voltage ramp enable */
88271da3f3da75d Jesse Barnes                  2011-01-05   3858  #define   GFXTGHYST		(1 << 24) /* Hysteresis to allow trunk gating */
88271da3f3da75d Jesse Barnes                  2011-01-05   3859  #define   RCX_SW_EXIT		(1 << 23) /* Leave RSx and prevent re-entry */
88271da3f3da75d Jesse Barnes                  2011-01-05   3860  #define   RSX_STATUS_MASK	(7 << 20)
88271da3f3da75d Jesse Barnes                  2011-01-05   3861  #define   RSX_STATUS_ON		(0 << 20)
88271da3f3da75d Jesse Barnes                  2011-01-05   3862  #define   RSX_STATUS_RC1	(1 << 20)
88271da3f3da75d Jesse Barnes                  2011-01-05   3863  #define   RSX_STATUS_RC1E	(2 << 20)
88271da3f3da75d Jesse Barnes                  2011-01-05   3864  #define   RSX_STATUS_RS1	(3 << 20)
88271da3f3da75d Jesse Barnes                  2011-01-05   3865  #define   RSX_STATUS_RS2	(4 << 20) /* aka rc6 */
88271da3f3da75d Jesse Barnes                  2011-01-05   3866  #define   RSX_STATUS_RSVD	(5 << 20) /* deep rc6 unsupported on ilk */
88271da3f3da75d Jesse Barnes                  2011-01-05   3867  #define   RSX_STATUS_RS3	(6 << 20) /* rs3 unsupported on ilk */
88271da3f3da75d Jesse Barnes                  2011-01-05   3868  #define   RSX_STATUS_RSVD2	(7 << 20)
88271da3f3da75d Jesse Barnes                  2011-01-05   3869  #define   UWRCRSXE		(1 << 19) /* wake counter limit prevents rsx */
88271da3f3da75d Jesse Barnes                  2011-01-05   3870  #define   RSCRP			(1 << 18) /* rs requests control on rs1/2 reqs */
88271da3f3da75d Jesse Barnes                  2011-01-05   3871  #define   JRSC			(1 << 17) /* rsx coupled to cpu c-state */
88271da3f3da75d Jesse Barnes                  2011-01-05   3872  #define   RS2INC0		(1 << 16) /* allow rs2 in cpu c0 */
88271da3f3da75d Jesse Barnes                  2011-01-05   3873  #define   RS1CONTSAV_MASK	(3 << 14)
88271da3f3da75d Jesse Barnes                  2011-01-05   3874  #define   RS1CONTSAV_NO_RS1	(0 << 14) /* rs1 doesn't save/restore context */
88271da3f3da75d Jesse Barnes                  2011-01-05   3875  #define   RS1CONTSAV_RSVD	(1 << 14)
88271da3f3da75d Jesse Barnes                  2011-01-05   3876  #define   RS1CONTSAV_SAVE_RS1	(2 << 14) /* rs1 saves context */
88271da3f3da75d Jesse Barnes                  2011-01-05   3877  #define   RS1CONTSAV_FULL_RS1	(3 << 14) /* rs1 saves and restores context */
88271da3f3da75d Jesse Barnes                  2011-01-05   3878  #define   NORMSLEXLAT_MASK	(3 << 12)
88271da3f3da75d Jesse Barnes                  2011-01-05   3879  #define   SLOW_RS123		(0 << 12)
88271da3f3da75d Jesse Barnes                  2011-01-05   3880  #define   SLOW_RS23		(1 << 12)
88271da3f3da75d Jesse Barnes                  2011-01-05   3881  #define   SLOW_RS3		(2 << 12)
88271da3f3da75d Jesse Barnes                  2011-01-05   3882  #define   NORMAL_RS123		(3 << 12)
88271da3f3da75d Jesse Barnes                  2011-01-05   3883  #define   RCMODE_TIMEOUT	(1 << 11) /* 0 is eval interval method */
88271da3f3da75d Jesse Barnes                  2011-01-05   3884  #define   IMPROMOEN		(1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
88271da3f3da75d Jesse Barnes                  2011-01-05   3885  #define   RCENTSYNC		(1 << 9) /* rs coupled to cpu c-state (3/6/7) */
88271da3f3da75d Jesse Barnes                  2011-01-05   3886  #define   STATELOCK		(1 << 7) /* locked to rs_cstate if 0 */
88271da3f3da75d Jesse Barnes                  2011-01-05   3887  #define   RS_CSTATE_MASK	(3 << 4)
88271da3f3da75d Jesse Barnes                  2011-01-05   3888  #define   RS_CSTATE_C367_RS1	(0 << 4)
88271da3f3da75d Jesse Barnes                  2011-01-05   3889  #define   RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
88271da3f3da75d Jesse Barnes                  2011-01-05   3890  #define   RS_CSTATE_RSVD	(2 << 4)
88271da3f3da75d Jesse Barnes                  2011-01-05   3891  #define   RS_CSTATE_C367_RS2	(3 << 4)
88271da3f3da75d Jesse Barnes                  2011-01-05   3892  #define   REDSAVES		(1 << 3) /* no context save if was idle during rs0 */
88271da3f3da75d Jesse Barnes                  2011-01-05   3893  #define   REDRESTORES		(1 << 2) /* no restore if was idle during rs0 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3894  #define VIDCTL			_MMIO(0x111c0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3895  #define VIDSTS			_MMIO(0x111c8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3896  #define VIDSTART		_MMIO(0x111cc) /* 8 bits */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3897  #define MEMSTAT_ILK		_MMIO(0x111f8)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3898  #define   MEMSTAT_VID_MASK	0x7f00
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3899  #define   MEMSTAT_VID_SHIFT	8
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3900  #define   MEMSTAT_PSTATE_MASK	0x00f8
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3901  #define   MEMSTAT_PSTATE_SHIFT  3
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3902  #define   MEMSTAT_MON_ACTV	(1 << 2)
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3903  #define   MEMSTAT_SRC_CTL_MASK	0x0003
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3904  #define   MEMSTAT_SRC_CTL_CORE	0
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3905  #define   MEMSTAT_SRC_CTL_TRB	1
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3906  #define   MEMSTAT_SRC_CTL_THM	2
f97108d1d0facc7 Jesse Barnes                  2010-01-29   3907  #define   MEMSTAT_SRC_CTL_STDBY 3
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3908  #define RCPREVBSYTUPAVG		_MMIO(0x113b8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3909  #define RCPREVBSYTDNAVG		_MMIO(0x113bc)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3910  #define PMMISC			_MMIO(0x11214)
ea056c14a269be3 Jesse Barnes                  2010-09-10   3911  #define   MCPPCE_EN		(1 << 0) /* enable PM_MSG from PCH->MPC */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3912  #define SDEW			_MMIO(0x1124c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3913  #define CSIEW0			_MMIO(0x11250)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3914  #define CSIEW1			_MMIO(0x11254)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3915  #define CSIEW2			_MMIO(0x11258)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3916  #define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3917  #define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3918  #define MCHAFE			_MMIO(0x112c0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3919  #define CSIEC			_MMIO(0x112e0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3920  #define DMIEC			_MMIO(0x112e4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3921  #define DDREC			_MMIO(0x112e8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3922  #define PEG0EC			_MMIO(0x112ec)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3923  #define PEG1EC			_MMIO(0x112f0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3924  #define GFXEC			_MMIO(0x112f4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3925  #define RPPREVBSYTUPAVG		_MMIO(0x113b8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3926  #define RPPREVBSYTDNAVG		_MMIO(0x113bc)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3927  #define ECR			_MMIO(0x11600)
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3928  #define   ECR_GPFE		(1 << 31)
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3929  #define   ECR_IMONE		(1 << 30)
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3930  #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3931  #define OGW0			_MMIO(0x11608)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3932  #define OGW1			_MMIO(0x1160c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3933  #define EG0			_MMIO(0x11610)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3934  #define EG1			_MMIO(0x11614)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3935  #define EG2			_MMIO(0x11618)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3936  #define EG3			_MMIO(0x1161c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3937  #define EG4			_MMIO(0x11620)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3938  #define EG5			_MMIO(0x11624)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3939  #define EG6			_MMIO(0x11628)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3940  #define EG7			_MMIO(0x1162c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3941  #define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3942  #define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3943  #define LCFUSE02		_MMIO(0x116c0)
7648fa99eb77a2e Jesse Barnes                  2010-05-20   3944  #define   LCFUSE_HIV_MASK	0x000000ff
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3945  #define CSIPLL0			_MMIO(0x12c10)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3946  #define DDRMPLL1		_MMIO(0X12c20)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3947  #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
7d57382e65994ab Eric Anholt                   2009-01-02   3948  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3949  #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
c4de7b0ffda2bb4 Chris Wilson                  2012-07-02   3950  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
c4de7b0ffda2bb4 Chris Wilson                  2012-07-02   3951  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3952  #define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3953  #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3954  #define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3955  #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   3956  #define BXT_RP_STATE_CAP        _MMIO(0x138170)
3b8d8d91d51c7d1 Jesse Barnes                  2010-12-17   3957  
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3958  /*
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3959   * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3960   * 8300) freezing up around GPU hangs. Looks as if even
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3961   * scheduling/timer interrupts start misbehaving if the RPS
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3962   * EI/thresholds are "bad", leading to a very sluggish or even
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3963   * frozen machine.
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3964   */
8a292d016d1cc49 Ville Syrjälä                 2016-04-20   3965  #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
de43ae9dd263d50 Akash Goel                    2015-03-06   3966  #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
26148bd3c0f1fbd Akash Goel                    2015-09-18   3967  #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
35ceabf3cdb557b Rodrigo Vivi                  2017-07-06   3968  #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
cc3f90f0633c5f0 Ander Conselvan de Oliveira   2016-12-02   3969  				(IS_GEN9_LP(dev_priv) ? \
26148bd3c0f1fbd Akash Goel                    2015-09-18   3970  				INTERVAL_0_833_US(us) : \
26148bd3c0f1fbd Akash Goel                    2015-09-18   3971  				INTERVAL_1_33_US(us)) : \
de43ae9dd263d50 Akash Goel                    2015-03-06   3972  				INTERVAL_1_28_US(us))
de43ae9dd263d50 Akash Goel                    2015-03-06   3973  
52530cbadcdf786 Akash Goel                    2016-04-23   3974  #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
52530cbadcdf786 Akash Goel                    2016-04-23   3975  #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
52530cbadcdf786 Akash Goel                    2016-04-23   3976  #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
35ceabf3cdb557b Rodrigo Vivi                  2017-07-06   3977  #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
cc3f90f0633c5f0 Ander Conselvan de Oliveira   2016-12-02   3978                             (IS_GEN9_LP(dev_priv) ? \
52530cbadcdf786 Akash Goel                    2016-04-23   3979                             INTERVAL_0_833_TO_US(interval) : \
52530cbadcdf786 Akash Goel                    2016-04-23   3980                             INTERVAL_1_33_TO_US(interval)) : \
52530cbadcdf786 Akash Goel                    2016-04-23   3981                             INTERVAL_1_28_TO_US(interval))
52530cbadcdf786 Akash Goel                    2016-04-23   3982  
585fb111348f7cd Jesse Barnes                  2008-07-29   3983  /*
aa40d6bbb9cf88f Zou Nan hai                   2010-06-25   3984   * Logical Context regs
aa40d6bbb9cf88f Zou Nan hai                   2010-06-25   3985   */
baba6e572b38ecd Daniele Ceraolo Spurio        2019-03-25   3986  #define CCID(base)			_MMIO((base) + 0x180)
ec62ed3e1d93843 Chris Wilson                  2017-02-07   3987  #define   CCID_EN			BIT(0)
ec62ed3e1d93843 Chris Wilson                  2017-02-07   3988  #define   CCID_EXTENDED_STATE_RESTORE	BIT(2)
ec62ed3e1d93843 Chris Wilson                  2017-02-07   3989  #define   CCID_EXTENDED_STATE_SAVE	BIT(3)
e8016055335687b Ville Syrjälä                 2013-08-22   3990  /*
e8016055335687b Ville Syrjälä                 2013-08-22   3991   * Notes on SNB/IVB/VLV context size:
e8016055335687b Ville Syrjälä                 2013-08-22   3992   * - Power context is saved elsewhere (LLC or stolen)
e8016055335687b Ville Syrjälä                 2013-08-22   3993   * - Ring/execlist context is saved on SNB, not on IVB
e8016055335687b Ville Syrjälä                 2013-08-22   3994   * - Extended context size already includes render context size
e8016055335687b Ville Syrjälä                 2013-08-22   3995   * - We always need to follow the extended context size.
e8016055335687b Ville Syrjälä                 2013-08-22   3996   *   SNB BSpec has comments indicating that we should use the
e8016055335687b Ville Syrjälä                 2013-08-22   3997   *   render context size instead if execlists are disabled, but
e8016055335687b Ville Syrjälä                 2013-08-22   3998   *   based on empirical testing that's just nonsense.
e8016055335687b Ville Syrjälä                 2013-08-22   3999   * - Pipelined/VF state is saved on SNB/IVB respectively
e8016055335687b Ville Syrjälä                 2013-08-22   4000   * - GT1 size just indicates how much of render context
e8016055335687b Ville Syrjälä                 2013-08-22   4001   *   doesn't need saving on GT1
e8016055335687b Ville Syrjälä                 2013-08-22   4002   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4003  #define CXT_SIZE		_MMIO(0x21a0)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4004  #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4005  #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4006  #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4007  #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4008  #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
e8016055335687b Ville Syrjälä                 2013-08-22   4009  #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
fe1cc68fcb11ca1 Ben Widawsky                  2012-06-04   4010  					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
fe1cc68fcb11ca1 Ben Widawsky                  2012-06-04   4011  					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4012  #define GEN7_CXT_SIZE		_MMIO(0x21a8)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4013  #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4014  #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4015  #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4016  #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4017  #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   4018  #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
e8016055335687b Ville Syrjälä                 2013-08-22   4019  #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4f91dd6f27f015f Ben Widawsky                  2012-07-18   4020  					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
8897644a6db05c6 Ben Widawsky                  2013-11-02   4021  
c01fc5322956eb0 Zhi Wang                      2016-06-16   4022  enum {
c01fc5322956eb0 Zhi Wang                      2016-06-16   4023  	INTEL_ADVANCED_CONTEXT = 0,
c01fc5322956eb0 Zhi Wang                      2016-06-16   4024  	INTEL_LEGACY_32B_CONTEXT,
c01fc5322956eb0 Zhi Wang                      2016-06-16   4025  	INTEL_ADVANCED_AD_CONTEXT,
c01fc5322956eb0 Zhi Wang                      2016-06-16   4026  	INTEL_LEGACY_64B_CONTEXT
c01fc5322956eb0 Zhi Wang                      2016-06-16   4027  };
c01fc5322956eb0 Zhi Wang                      2016-06-16   4028  
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4029  enum {
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4030  	FAULT_AND_HANG = 0,
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4031  	FAULT_AND_HALT, /* Debug only */
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4032  	FAULT_AND_STREAM,
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4033  	FAULT_AND_CONTINUE /* Unsupported */
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4034  };
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4035  
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4036  #define GEN8_CTX_VALID (1 << 0)
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4037  #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4038  #define GEN8_CTX_FORCE_RESTORE (1 << 2)
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4039  #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4040  #define GEN8_CTX_PRIVILEGE (1 << 8)
c01fc5322956eb0 Zhi Wang                      2016-06-16   4041  #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
c01fc5322956eb0 Zhi Wang                      2016-06-16   4042  
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4043  #define GEN8_CTX_ID_SHIFT 32
2355cf088d469f6 Mika Kuoppala                 2017-01-27   4044  #define GEN8_CTX_ID_WIDTH 21
ac52da6af826d05 Daniele Ceraolo Spurio        2018-03-02   4045  #define GEN11_SW_CTX_ID_SHIFT 37
ac52da6af826d05 Daniele Ceraolo Spurio        2018-03-02   4046  #define GEN11_SW_CTX_ID_WIDTH 11
ac52da6af826d05 Daniele Ceraolo Spurio        2018-03-02   4047  #define GEN11_ENGINE_CLASS_SHIFT 61
ac52da6af826d05 Daniele Ceraolo Spurio        2018-03-02   4048  #define GEN11_ENGINE_CLASS_WIDTH 3
ac52da6af826d05 Daniele Ceraolo Spurio        2018-03-02   4049  #define GEN11_ENGINE_INSTANCE_SHIFT 48
ac52da6af826d05 Daniele Ceraolo Spurio        2018-03-02   4050  #define GEN11_ENGINE_INSTANCE_WIDTH 6
c01fc5322956eb0 Zhi Wang                      2016-06-16   4051  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4052  #define CHV_CLK_CTL1			_MMIO(0x101100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4053  #define VLV_CLK_CTL2			_MMIO(0x101104)
e454a05da623c26 Jesse Barnes                  2013-09-26   4054  #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
e454a05da623c26 Jesse Barnes                  2013-09-26   4055  
aa40d6bbb9cf88f Zou Nan hai                   2010-06-25   4056  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4057   * Overlay regs
585fb111348f7cd Jesse Barnes                  2008-07-29   4058   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4059  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4060  #define OVADD			_MMIO(0x30000)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4061  #define DOVSTA			_MMIO(0x30008)
585fb111348f7cd Jesse Barnes                  2008-07-29   4062  #define OC_BUF			(0x3 << 20)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4063  #define OGAMC5			_MMIO(0x30010)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4064  #define OGAMC4			_MMIO(0x30014)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4065  #define OGAMC3			_MMIO(0x30018)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4066  #define OGAMC2			_MMIO(0x3001c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4067  #define OGAMC1			_MMIO(0x30020)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4068  #define OGAMC0			_MMIO(0x30024)
585fb111348f7cd Jesse Barnes                  2008-07-29   4069  
585fb111348f7cd Jesse Barnes                  2008-07-29   4070  /*
d965e7ac7a196c2 Imre Deak                     2015-12-01   4071   * GEN9 clock gating regs
d965e7ac7a196c2 Imre Deak                     2015-12-01   4072   */
d965e7ac7a196c2 Imre Deak                     2015-12-01   4073  #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
df49ec8223050d5 Rodrigo Vivi                  2017-11-10   4074  #define   DARBF_GATING_DIS		(1 << 27)
d965e7ac7a196c2 Imre Deak                     2015-12-01   4075  #define   PWM2_GATING_DIS		(1 << 14)
d965e7ac7a196c2 Imre Deak                     2015-12-01   4076  #define   PWM1_GATING_DIS		(1 << 13)
d965e7ac7a196c2 Imre Deak                     2015-12-01   4077  
6481d5ed076e69d Ville Syrjälä                 2017-12-21   4078  #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
6481d5ed076e69d Ville Syrjälä                 2017-12-21   4079  #define   BXT_GMBUS_GATING_DIS		(1 << 14)
6481d5ed076e69d Ville Syrjälä                 2017-12-21   4080  
ed69cd40685c949 Imre Deak                     2017-10-02   4081  #define _CLKGATE_DIS_PSL_A		0x46520
ed69cd40685c949 Imre Deak                     2017-10-02   4082  #define _CLKGATE_DIS_PSL_B		0x46524
ed69cd40685c949 Imre Deak                     2017-10-02   4083  #define _CLKGATE_DIS_PSL_C		0x46528
c4a4efa91737e61 Vidya Srinivas                2018-04-09   4084  #define   DUPS1_GATING_DIS		(1 << 15)
c4a4efa91737e61 Vidya Srinivas                2018-04-09   4085  #define   DUPS2_GATING_DIS		(1 << 19)
c4a4efa91737e61 Vidya Srinivas                2018-04-09   4086  #define   DUPS3_GATING_DIS		(1 << 23)
ed69cd40685c949 Imre Deak                     2017-10-02   4087  #define   DPF_GATING_DIS		(1 << 10)
ed69cd40685c949 Imre Deak                     2017-10-02   4088  #define   DPF_RAM_GATING_DIS		(1 << 9)
ed69cd40685c949 Imre Deak                     2017-10-02   4089  #define   DPFR_GATING_DIS		(1 << 8)
ed69cd40685c949 Imre Deak                     2017-10-02   4090  
ed69cd40685c949 Imre Deak                     2017-10-02   4091  #define CLKGATE_DIS_PSL(pipe) \
ed69cd40685c949 Imre Deak                     2017-10-02   4092  	_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
ed69cd40685c949 Imre Deak                     2017-10-02   4093  
d965e7ac7a196c2 Imre Deak                     2015-12-01   4094  /*
90007bca61627bb Rodrigo Vivi                  2017-08-15   4095   * GEN10 clock gating regs
90007bca61627bb Rodrigo Vivi                  2017-08-15   4096   */
90007bca61627bb Rodrigo Vivi                  2017-08-15   4097  #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
90007bca61627bb Rodrigo Vivi                  2017-08-15   4098  #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
0a60797a0efbc49 Rafael Antognolli             2017-11-03   4099  #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
0a437d498165061 Oscar Mateo                   2018-05-08   4100  #define  MSCUNIT_CLKGATE_DIS		(1 << 10)
90007bca61627bb Rodrigo Vivi                  2017-08-15   4101  
a4713c5a8d612b4 Rodrigo Vivi                  2018-03-07   4102  #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
a4713c5a8d612b4 Rodrigo Vivi                  2018-03-07   4103  #define  GWUNIT_CLKGATE_DIS		(1 << 16)
a4713c5a8d612b4 Rodrigo Vivi                  2018-03-07   4104  
01ab0f9216070f3 Rafael Antognolli             2017-12-15   4105  #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
01ab0f9216070f3 Rafael Antognolli             2017-12-15   4106  #define  VFUNIT_CLKGATE_DIS		(1 << 20)
01ab0f9216070f3 Rafael Antognolli             2017-12-15   4107  
5ba700c73a89b0b Oscar Mateo                   2018-05-08   4108  #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
5ba700c73a89b0b Oscar Mateo                   2018-05-08   4109  #define   CGPSF_CLKGATE_DIS		(1 << 3)
5ba700c73a89b0b Oscar Mateo                   2018-05-08   4110  
90007bca61627bb Rodrigo Vivi                  2017-08-15   4111  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4112   * Display engine regs
585fb111348f7cd Jesse Barnes                  2008-07-29   4113   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4114  
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4115  /* Pipe A CRC regs */
a57c774ab2b849b Antti Koskipaa                2014-02-04   4116  #define _PIPE_CRC_CTL_A			0x60050
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4117  #define   PIPE_CRC_ENABLE		(1 << 31)
207a815d8603946 Ville Syrjälä                 2019-02-14   4118  /* skl+ source selection */
207a815d8603946 Ville Syrjälä                 2019-02-14   4119  #define   PIPE_CRC_SOURCE_PLANE_1_SKL	(0 << 28)
207a815d8603946 Ville Syrjälä                 2019-02-14   4120  #define   PIPE_CRC_SOURCE_PLANE_2_SKL	(2 << 28)
207a815d8603946 Ville Syrjälä                 2019-02-14   4121  #define   PIPE_CRC_SOURCE_DMUX_SKL	(4 << 28)
207a815d8603946 Ville Syrjälä                 2019-02-14   4122  #define   PIPE_CRC_SOURCE_PLANE_3_SKL	(6 << 28)
207a815d8603946 Ville Syrjälä                 2019-02-14   4123  #define   PIPE_CRC_SOURCE_PLANE_4_SKL	(7 << 28)
207a815d8603946 Ville Syrjälä                 2019-02-14   4124  #define   PIPE_CRC_SOURCE_PLANE_5_SKL	(5 << 28)
207a815d8603946 Ville Syrjälä                 2019-02-14   4125  #define   PIPE_CRC_SOURCE_PLANE_6_SKL	(3 << 28)
207a815d8603946 Ville Syrjälä                 2019-02-14   4126  #define   PIPE_CRC_SOURCE_PLANE_7_SKL	(1 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4127  /* ivb+ source selection */
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4128  #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4129  #define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4130  #define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
b4437a4139f455d Daniel Vetter                 2013-10-16   4131  /* ilk+ source selection */
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4132  #define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4133  #define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4134  #define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4135  /* embedded DP port on the north display block, reserved on ivb */
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4136  #define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4137  #define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
b4437a4139f455d Daniel Vetter                 2013-10-16   4138  /* vlv source selection */
b4437a4139f455d Daniel Vetter                 2013-10-16   4139  #define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
b4437a4139f455d Daniel Vetter                 2013-10-16   4140  #define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
b4437a4139f455d Daniel Vetter                 2013-10-16   4141  #define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
b4437a4139f455d Daniel Vetter                 2013-10-16   4142  /* with DP port the pipe source is invalid */
b4437a4139f455d Daniel Vetter                 2013-10-16   4143  #define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
b4437a4139f455d Daniel Vetter                 2013-10-16   4144  #define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
b4437a4139f455d Daniel Vetter                 2013-10-16   4145  #define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
b4437a4139f455d Daniel Vetter                 2013-10-16   4146  /* gen3+ source selection */
b4437a4139f455d Daniel Vetter                 2013-10-16   4147  #define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4148  #define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4149  #define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4150  /* with DP/TV port the pipe source is invalid */
b4437a4139f455d Daniel Vetter                 2013-10-16   4151  #define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4152  #define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4153  #define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4154  #define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4155  #define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
b4437a4139f455d Daniel Vetter                 2013-10-16   4156  /* gen2 doesn't have source selection bits */
52f843f6ccbd734 Daniel Vetter                 2013-10-21   4157  #define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
b4437a4139f455d Daniel Vetter                 2013-10-16   4158  
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4159  #define _PIPE_CRC_RES_1_A_IVB		0x60064
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4160  #define _PIPE_CRC_RES_2_A_IVB		0x60068
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4161  #define _PIPE_CRC_RES_3_A_IVB		0x6006c
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4162  #define _PIPE_CRC_RES_4_A_IVB		0x60070
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4163  #define _PIPE_CRC_RES_5_A_IVB		0x60074
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4164  
a57c774ab2b849b Antti Koskipaa                2014-02-04   4165  #define _PIPE_CRC_RES_RED_A		0x60060
a57c774ab2b849b Antti Koskipaa                2014-02-04   4166  #define _PIPE_CRC_RES_GREEN_A		0x60064
a57c774ab2b849b Antti Koskipaa                2014-02-04   4167  #define _PIPE_CRC_RES_BLUE_A		0x60068
a57c774ab2b849b Antti Koskipaa                2014-02-04   4168  #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
a57c774ab2b849b Antti Koskipaa                2014-02-04   4169  #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4170  
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4171  /* Pipe B CRC regs */
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4172  #define _PIPE_CRC_RES_1_B_IVB		0x61064
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4173  #define _PIPE_CRC_RES_2_B_IVB		0x61068
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4174  #define _PIPE_CRC_RES_3_B_IVB		0x6106c
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4175  #define _PIPE_CRC_RES_4_B_IVB		0x61070
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4176  #define _PIPE_CRC_RES_5_B_IVB		0x61074
8bf1e9f1d2aa1fa Shuang He                     2013-10-15   4177  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4178  #define PIPE_CRC_CTL(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4179  #define PIPE_CRC_RES_1_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4180  #define PIPE_CRC_RES_2_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4181  #define PIPE_CRC_RES_3_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4182  #define PIPE_CRC_RES_4_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4183  #define PIPE_CRC_RES_5_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4184  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4185  #define PIPE_CRC_RES_RED(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4186  #define PIPE_CRC_RES_GREEN(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4187  #define PIPE_CRC_RES_BLUE(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4188  #define PIPE_CRC_RES_RES1_I915(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4189  #define PIPE_CRC_RES_RES2_G4X(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
5a6b5c84e494336 Daniel Vetter                 2013-10-16   4190  
585fb111348f7cd Jesse Barnes                  2008-07-29   4191  /* Pipe A timing regs */
a57c774ab2b849b Antti Koskipaa                2014-02-04   4192  #define _HTOTAL_A	0x60000
a57c774ab2b849b Antti Koskipaa                2014-02-04   4193  #define _HBLANK_A	0x60004
a57c774ab2b849b Antti Koskipaa                2014-02-04   4194  #define _HSYNC_A	0x60008
a57c774ab2b849b Antti Koskipaa                2014-02-04   4195  #define _VTOTAL_A	0x6000c
a57c774ab2b849b Antti Koskipaa                2014-02-04   4196  #define _VBLANK_A	0x60010
a57c774ab2b849b Antti Koskipaa                2014-02-04   4197  #define _VSYNC_A	0x60014
a57c774ab2b849b Antti Koskipaa                2014-02-04   4198  #define _PIPEASRC	0x6001c
a57c774ab2b849b Antti Koskipaa                2014-02-04   4199  #define _BCLRPAT_A	0x60020
a57c774ab2b849b Antti Koskipaa                2014-02-04   4200  #define _VSYNCSHIFT_A	0x60028
ebb69c951756099 Clint Taylor                  2014-09-30   4201  #define _PIPE_MULT_A	0x6002c
585fb111348f7cd Jesse Barnes                  2008-07-29   4202  
585fb111348f7cd Jesse Barnes                  2008-07-29   4203  /* Pipe B timing regs */
a57c774ab2b849b Antti Koskipaa                2014-02-04   4204  #define _HTOTAL_B	0x61000
a57c774ab2b849b Antti Koskipaa                2014-02-04   4205  #define _HBLANK_B	0x61004
a57c774ab2b849b Antti Koskipaa                2014-02-04   4206  #define _HSYNC_B	0x61008
a57c774ab2b849b Antti Koskipaa                2014-02-04   4207  #define _VTOTAL_B	0x6100c
a57c774ab2b849b Antti Koskipaa                2014-02-04   4208  #define _VBLANK_B	0x61010
a57c774ab2b849b Antti Koskipaa                2014-02-04   4209  #define _VSYNC_B	0x61014
a57c774ab2b849b Antti Koskipaa                2014-02-04   4210  #define _PIPEBSRC	0x6101c
a57c774ab2b849b Antti Koskipaa                2014-02-04   4211  #define _BCLRPAT_B	0x61020
a57c774ab2b849b Antti Koskipaa                2014-02-04   4212  #define _VSYNCSHIFT_B	0x61028
ebb69c951756099 Clint Taylor                  2014-09-30   4213  #define _PIPE_MULT_B	0x6102c
a57c774ab2b849b Antti Koskipaa                2014-02-04   4214  
7b56caf36376f6d Madhav Chauhan                2018-10-15   4215  /* DSI 0 timing regs */
7b56caf36376f6d Madhav Chauhan                2018-10-15   4216  #define _HTOTAL_DSI0		0x6b000
7b56caf36376f6d Madhav Chauhan                2018-10-15   4217  #define _HSYNC_DSI0		0x6b008
7b56caf36376f6d Madhav Chauhan                2018-10-15   4218  #define _VTOTAL_DSI0		0x6b00c
7b56caf36376f6d Madhav Chauhan                2018-10-15   4219  #define _VSYNC_DSI0		0x6b014
7b56caf36376f6d Madhav Chauhan                2018-10-15   4220  #define _VSYNCSHIFT_DSI0	0x6b028
7b56caf36376f6d Madhav Chauhan                2018-10-15   4221  
7b56caf36376f6d Madhav Chauhan                2018-10-15   4222  /* DSI 1 timing regs */
7b56caf36376f6d Madhav Chauhan                2018-10-15   4223  #define _HTOTAL_DSI1		0x6b800
7b56caf36376f6d Madhav Chauhan                2018-10-15   4224  #define _HSYNC_DSI1		0x6b808
7b56caf36376f6d Madhav Chauhan                2018-10-15   4225  #define _VTOTAL_DSI1		0x6b80c
7b56caf36376f6d Madhav Chauhan                2018-10-15   4226  #define _VSYNC_DSI1		0x6b814
7b56caf36376f6d Madhav Chauhan                2018-10-15   4227  #define _VSYNCSHIFT_DSI1	0x6b828
7b56caf36376f6d Madhav Chauhan                2018-10-15   4228  
a57c774ab2b849b Antti Koskipaa                2014-02-04   4229  #define TRANSCODER_A_OFFSET 0x60000
a57c774ab2b849b Antti Koskipaa                2014-02-04   4230  #define TRANSCODER_B_OFFSET 0x61000
a57c774ab2b849b Antti Koskipaa                2014-02-04   4231  #define TRANSCODER_C_OFFSET 0x62000
84fd4f4e18885fc Rafael Barbalho               2014-04-28   4232  #define CHV_TRANSCODER_C_OFFSET 0x63000
f1f1d4fa5869c8b Lucas De Marchi               2019-07-11   4233  #define TRANSCODER_D_OFFSET 0x63000
a57c774ab2b849b Antti Koskipaa                2014-02-04   4234  #define TRANSCODER_EDP_OFFSET 0x6f000
49edbd49786ee32 Madhav Chauhan                2018-10-15   4235  #define TRANSCODER_DSI0_OFFSET	0x6b000
49edbd49786ee32 Madhav Chauhan                2018-10-15   4236  #define TRANSCODER_DSI1_OFFSET	0x6b800
a57c774ab2b849b Antti Koskipaa                2014-02-04   4237  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4238  #define HTOTAL(trans)		_MMIO_TRANS2(trans, _HTOTAL_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4239  #define HBLANK(trans)		_MMIO_TRANS2(trans, _HBLANK_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4240  #define HSYNC(trans)		_MMIO_TRANS2(trans, _HSYNC_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4241  #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4242  #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4243  #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4244  #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4245  #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4246  #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4247  #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   4248  
ed8546ac1f99b85 Ben Widawsky                  2013-11-04   4249  /* HSW+ eDP PSR registers */
443a389f43c05e4 Ville Syrjälä                 2015-11-11   4250  #define HSW_EDP_PSR_BASE	0x64800
443a389f43c05e4 Ville Syrjälä                 2015-11-11   4251  #define BDW_EDP_PSR_BASE	0x6f800
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4252  #define EDP_PSR_CTL				_MMIO(dev_priv->psr_mmio_base + 0)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4253  #define   EDP_PSR_ENABLE			(1 << 31)
82c562549b4c862 Rodrigo Vivi                  2014-06-12   4254  #define   BDW_PSR_SINGLE_FRAME			(1 << 30)
912d64123d354dd Jim Bride                     2017-08-08   4255  #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	(1 << 29) /* SW can't modify */
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4256  #define   EDP_PSR_LINK_STANDBY			(1 << 27)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4257  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3 << 25)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4258  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0 << 25)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4259  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES	(1 << 25)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4260  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2 << 25)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4261  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3 << 25)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4262  #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4263  #define   EDP_PSR_SKIP_AUX_EXIT			(1 << 12)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4264  #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4265  #define   EDP_PSR_TP1_TP3_SEL			(1 << 11)
00c8f19463ab42d José Roberto de Souza         2018-06-26   4266  #define   EDP_PSR_CRC_ENABLE			(1 << 10) /* BDW+ */
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4267  #define   EDP_PSR_TP2_TP3_TIME_500us		(0 << 8)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4268  #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4269  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4270  #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
8a9a5608a31b23a José Roberto de Souza         2019-03-12   4271  #define   EDP_PSR_TP4_TIME_0US			(3 << 6) /* ICL+ */
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4272  #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4273  #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4274  #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4275  #define   EDP_PSR_TP1_TIME_0us			(3 << 4)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4276  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4277  
fc34044248b611e Daniel Vetter                 2018-04-05   4278  /* Bspec claims those aren't shifted but stay at 0x64800 */
fc34044248b611e Daniel Vetter                 2018-04-05   4279  #define EDP_PSR_IMR				_MMIO(0x64834)
fc34044248b611e Daniel Vetter                 2018-04-05   4280  #define EDP_PSR_IIR				_MMIO(0x64838)
c0871805ce1c716 Imre Deak                     2018-11-20   4281  #define   EDP_PSR_ERROR(shift)			(1 << ((shift) + 2))
c0871805ce1c716 Imre Deak                     2018-11-20   4282  #define   EDP_PSR_POST_EXIT(shift)		(1 << ((shift) + 1))
c0871805ce1c716 Imre Deak                     2018-11-20   4283  #define   EDP_PSR_PRE_ENTRY(shift)		(1 << (shift))
c0871805ce1c716 Imre Deak                     2018-11-20   4284  #define   EDP_PSR_TRANSCODER_C_SHIFT		24
c0871805ce1c716 Imre Deak                     2018-11-20   4285  #define   EDP_PSR_TRANSCODER_B_SHIFT		16
c0871805ce1c716 Imre Deak                     2018-11-20   4286  #define   EDP_PSR_TRANSCODER_A_SHIFT		8
c0871805ce1c716 Imre Deak                     2018-11-20   4287  #define   EDP_PSR_TRANSCODER_EDP_SHIFT		0
fc34044248b611e Daniel Vetter                 2018-04-05   4288  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4289  #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
d544e918ff13248 Dhinakaran Pandiyan           2018-03-12   4290  #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
d544e918ff13248 Dhinakaran Pandiyan           2018-03-12   4291  #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
d544e918ff13248 Dhinakaran Pandiyan           2018-03-12   4292  #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
d544e918ff13248 Dhinakaran Pandiyan           2018-03-12   4293  #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
d544e918ff13248 Dhinakaran Pandiyan           2018-03-12   4294  #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
d544e918ff13248 Dhinakaran Pandiyan           2018-03-12   4295  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4296  #define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4297  
861023e0b6c44d6 Dhinakaran Pandiyan           2017-12-20   4298  #define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4299  #define   EDP_PSR_STATUS_STATE_MASK		(7 << 29)
00b062967f1524d Vathsala Nagaraju             2018-06-27   4300  #define   EDP_PSR_STATUS_STATE_SHIFT		29
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4301  #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4302  #define   EDP_PSR_STATUS_STATE_SRDONACK		(1 << 29)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4303  #define   EDP_PSR_STATUS_STATE_SRDENT		(2 << 29)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4304  #define   EDP_PSR_STATUS_STATE_BUFOFF		(3 << 29)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4305  #define   EDP_PSR_STATUS_STATE_BUFON		(4 << 29)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4306  #define   EDP_PSR_STATUS_STATE_AUXACK		(5 << 29)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4307  #define   EDP_PSR_STATUS_STATE_SRDOFFACK	(6 << 29)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4308  #define   EDP_PSR_STATUS_LINK_MASK		(3 << 26)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4309  #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0 << 26)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4310  #define   EDP_PSR_STATUS_LINK_FULL_ON		(1 << 26)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4311  #define   EDP_PSR_STATUS_LINK_STANDBY		(2 << 26)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4312  #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT	20
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4313  #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4314  #define   EDP_PSR_STATUS_COUNT_SHIFT		16
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4315  #define   EDP_PSR_STATUS_COUNT_MASK		0xf
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4316  #define   EDP_PSR_STATUS_AUX_ERROR		(1 << 15)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4317  #define   EDP_PSR_STATUS_AUX_SENDING		(1 << 12)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4318  #define   EDP_PSR_STATUS_SENDING_IDLE		(1 << 9)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4319  #define   EDP_PSR_STATUS_SENDING_TP2_TP3	(1 << 8)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4320  #define   EDP_PSR_STATUS_SENDING_TP1		(1 << 4)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4321  #define   EDP_PSR_STATUS_IDLE_MASK		0xf
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4322  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4323  #define EDP_PSR_PERF_CNT		_MMIO(dev_priv->psr_mmio_base + 0x44)
e91fd8c6dec2ffa Rodrigo Vivi                  2013-07-11   4324  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4325  
62801bf61567929 Dhinakaran Pandiyan           2018-03-12   4326  #define EDP_PSR_DEBUG				_MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
6433226b0f51cdd Nagaraju, Vathsala            2017-01-13   4327  #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4328  #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4329  #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4330  #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
fc6ff9dc9ecf7e1 José Roberto de Souza         2018-10-03   4331  #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
62801bf61567929 Dhinakaran Pandiyan           2018-03-12   4332  #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4333  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4334  #define EDP_PSR2_CTL			_MMIO(0x6f900)
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4335  #define   EDP_PSR2_ENABLE		(1 << 31)
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4336  #define   EDP_SU_TRACK_ENABLE		(1 << 30)
5e87325f5c57ba5 José Roberto de Souza         2018-03-28   4337  #define   EDP_Y_COORDINATE_VALID	(1 << 26) /* GLK and CNL+ */
5e87325f5c57ba5 José Roberto de Souza         2018-03-28   4338  #define   EDP_Y_COORDINATE_ENABLE	(1 << 25) /* GLK and CNL+ */
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4339  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t) << 20)
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4340  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f << 20)
77312ae8f071fb3 Vathsala Nagaraju             2018-05-22   4341  #define   EDP_PSR2_TP2_TIME_500us	(0 << 8)
77312ae8f071fb3 Vathsala Nagaraju             2018-05-22   4342  #define   EDP_PSR2_TP2_TIME_100us	(1 << 8)
77312ae8f071fb3 Vathsala Nagaraju             2018-05-22   4343  #define   EDP_PSR2_TP2_TIME_2500us	(2 << 8)
77312ae8f071fb3 Vathsala Nagaraju             2018-05-22   4344  #define   EDP_PSR2_TP2_TIME_50us	(3 << 8)
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4345  #define   EDP_PSR2_TP2_TIME_MASK	(3 << 8)
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4346  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4347  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf << 4)
977da084cc3c179 vathsala nagaraju             2017-09-26   4348  #define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a) << 4)
fe36181be371f3d José Roberto de Souza         2018-03-28   4349  #define   EDP_PSR2_IDLE_FRAME_MASK	0xf
fe36181be371f3d José Roberto de Souza         2018-03-28   4350  #define   EDP_PSR2_IDLE_FRAME_SHIFT	0
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4351  
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4352  #define _PSR_EVENT_TRANS_A			0x60848
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4353  #define _PSR_EVENT_TRANS_B			0x61848
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4354  #define _PSR_EVENT_TRANS_C			0x62848
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4355  #define _PSR_EVENT_TRANS_D			0x63848
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4356  #define _PSR_EVENT_TRANS_EDP			0x6F848
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4357  #define PSR_EVENT(trans)			_MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4358  #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE		(1 << 17)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4359  #define  PSR_EVENT_PSR2_DISABLED		(1 << 16)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4360  #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN	(1 << 15)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4361  #define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN		(1 << 14)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4362  #define  PSR_EVENT_GRAPHICS_RESET		(1 << 12)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4363  #define  PSR_EVENT_PCH_INTERRUPT		(1 << 11)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4364  #define  PSR_EVENT_MEMORY_UP			(1 << 10)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4365  #define  PSR_EVENT_FRONT_BUFFER_MODIFY		(1 << 9)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4366  #define  PSR_EVENT_WD_TIMER_EXPIRE		(1 << 8)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4367  #define  PSR_EVENT_PIPE_REGISTERS_UPDATE	(1 << 6)
fc6ff9dc9ecf7e1 José Roberto de Souza         2018-10-03   4368  #define  PSR_EVENT_REGISTER_UPDATE		(1 << 5) /* Reserved in ICL+ */
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4369  #define  PSR_EVENT_HDCP_ENABLE			(1 << 4)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4370  #define  PSR_EVENT_KVMR_SESSION_ENABLE		(1 << 3)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4371  #define  PSR_EVENT_VBI_ENABLE			(1 << 2)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4372  #define  PSR_EVENT_LPSP_MODE_EXIT		(1 << 1)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4373  #define  PSR_EVENT_PSR_DISABLE			(1 << 0)
bc18b4df0fcb9fa José Roberto de Souza         2018-04-25   4374  
861023e0b6c44d6 Dhinakaran Pandiyan           2017-12-20   4375  #define EDP_PSR2_STATUS			_MMIO(0x6f940)
3fcb0ca1d8dbfdc Nagaraju, Vathsala            2017-01-12   4376  #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
6ba1f9e1772f3ff Nagaraju, Vathsala            2017-01-06   4377  #define EDP_PSR2_STATUS_STATE_SHIFT    28
474d1ec4a3d7775 Sonika Jindal                 2015-04-02   4378  
cc8853f57e00511 José Roberto de Souza         2019-01-17   4379  #define _PSR2_SU_STATUS_0		0x6F914
cc8853f57e00511 José Roberto de Souza         2019-01-17   4380  #define _PSR2_SU_STATUS_1		0x6F918
cc8853f57e00511 José Roberto de Souza         2019-01-17   4381  #define _PSR2_SU_STATUS_2		0x6F91C
cc8853f57e00511 José Roberto de Souza         2019-01-17   4382  #define _PSR2_SU_STATUS(index)		_MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
cc8853f57e00511 José Roberto de Souza         2019-01-17   4383  #define PSR2_SU_STATUS(frame)		(_PSR2_SU_STATUS((frame) / 3))
cc8853f57e00511 José Roberto de Souza         2019-01-17   4384  #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
cc8853f57e00511 José Roberto de Souza         2019-01-17   4385  #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
cc8853f57e00511 José Roberto de Souza         2019-01-17   4386  #define PSR2_SU_STATUS_FRAMES		8
cc8853f57e00511 José Roberto de Souza         2019-01-17   4387  
585fb111348f7cd Jesse Barnes                  2008-07-29   4388  /* VGA port control */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4389  #define ADPA			_MMIO(0x61100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4390  #define PCH_ADPA                _MMIO(0xe1100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4391  #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4392  
585fb111348f7cd Jesse Barnes                  2008-07-29   4393  #define   ADPA_DAC_ENABLE	(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   4394  #define   ADPA_DAC_DISABLE	0
6102a8ee8ad60c5 Ville Syrjälä                 2018-05-14   4395  #define   ADPA_PIPE_SEL_SHIFT		30
6102a8ee8ad60c5 Ville Syrjälä                 2018-05-14   4396  #define   ADPA_PIPE_SEL_MASK		(1 << 30)
6102a8ee8ad60c5 Ville Syrjälä                 2018-05-14   4397  #define   ADPA_PIPE_SEL(pipe)		((pipe) << 30)
6102a8ee8ad60c5 Ville Syrjälä                 2018-05-14   4398  #define   ADPA_PIPE_SEL_SHIFT_CPT	29
6102a8ee8ad60c5 Ville Syrjälä                 2018-05-14   4399  #define   ADPA_PIPE_SEL_MASK_CPT	(3 << 29)
6102a8ee8ad60c5 Ville Syrjälä                 2018-05-14   4400  #define   ADPA_PIPE_SEL_CPT(pipe)	((pipe) << 29)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4401  #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4402  #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4403  #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3 << 24)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4404  #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4405  #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2 << 24)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4406  #define   ADPA_CRT_HOTPLUG_ENABLE        (1 << 23)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4407  #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4408  #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1 << 22)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4409  #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4410  #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1 << 21)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4411  #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4412  #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1 << 20)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4413  #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4414  #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1 << 18)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4415  #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2 << 18)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4416  #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3 << 18)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4417  #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4418  #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1 << 17)
ebc0fd882b000b1 Daniel Vetter                 2012-07-11   4419  #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
585fb111348f7cd Jesse Barnes                  2008-07-29   4420  #define   ADPA_USE_VGA_HVPOLARITY (1 << 15)
585fb111348f7cd Jesse Barnes                  2008-07-29   4421  #define   ADPA_SETS_HVPOLARITY	0
60222c0c2b4d813 Patrik Jakobsson              2013-03-05   4422  #define   ADPA_VSYNC_CNTL_DISABLE (1 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4423  #define   ADPA_VSYNC_CNTL_ENABLE 0
60222c0c2b4d813 Patrik Jakobsson              2013-03-05   4424  #define   ADPA_HSYNC_CNTL_DISABLE (1 << 11)
585fb111348f7cd Jesse Barnes                  2008-07-29   4425  #define   ADPA_HSYNC_CNTL_ENABLE 0
585fb111348f7cd Jesse Barnes                  2008-07-29   4426  #define   ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   4427  #define   ADPA_VSYNC_ACTIVE_LOW	0
585fb111348f7cd Jesse Barnes                  2008-07-29   4428  #define   ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
585fb111348f7cd Jesse Barnes                  2008-07-29   4429  #define   ADPA_HSYNC_ACTIVE_LOW	0
585fb111348f7cd Jesse Barnes                  2008-07-29   4430  #define   ADPA_DPMS_MASK	(~(3 << 10))
585fb111348f7cd Jesse Barnes                  2008-07-29   4431  #define   ADPA_DPMS_ON		(0 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4432  #define   ADPA_DPMS_SUSPEND	(1 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4433  #define   ADPA_DPMS_STANDBY	(2 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4434  #define   ADPA_DPMS_OFF		(3 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4435  
939fe4d7d6e2c92 Chris Wilson                  2010-10-09   4436  
585fb111348f7cd Jesse Barnes                  2008-07-29   4437  /* Hotplug control (945+ only) */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4438  #define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
26739f12cf210cb Daniel Vetter                 2013-02-07   4439  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
26739f12cf210cb Daniel Vetter                 2013-02-07   4440  #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
26739f12cf210cb Daniel Vetter                 2013-02-07   4441  #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
585fb111348f7cd Jesse Barnes                  2008-07-29   4442  #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
585fb111348f7cd Jesse Barnes                  2008-07-29   4443  #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
585fb111348f7cd Jesse Barnes                  2008-07-29   4444  #define   TV_HOTPLUG_INT_EN			(1 << 18)
585fb111348f7cd Jesse Barnes                  2008-07-29   4445  #define   CRT_HOTPLUG_INT_EN			(1 << 9)
e5868a318d1ae28 Egbert Eich                   2013-02-28   4446  #define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4447  						 PORTC_HOTPLUG_INT_EN | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4448  						 PORTD_HOTPLUG_INT_EN | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4449  						 SDVOC_HOTPLUG_INT_EN | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4450  						 SDVOB_HOTPLUG_INT_EN | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4451  						 CRT_HOTPLUG_INT_EN)
585fb111348f7cd Jesse Barnes                  2008-07-29   4452  #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
771cb081354161e Zhao Yakui                    2009-03-03   4453  #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
771cb081354161e Zhao Yakui                    2009-03-03   4454  /* must use period 64 on GM45 according to docs */
771cb081354161e Zhao Yakui                    2009-03-03   4455  #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
771cb081354161e Zhao Yakui                    2009-03-03   4456  #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
771cb081354161e Zhao Yakui                    2009-03-03   4457  #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
771cb081354161e Zhao Yakui                    2009-03-03   4458  #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
771cb081354161e Zhao Yakui                    2009-03-03   4459  #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
771cb081354161e Zhao Yakui                    2009-03-03   4460  #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
771cb081354161e Zhao Yakui                    2009-03-03   4461  #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
771cb081354161e Zhao Yakui                    2009-03-03   4462  #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
771cb081354161e Zhao Yakui                    2009-03-03   4463  #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
771cb081354161e Zhao Yakui                    2009-03-03   4464  #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
771cb081354161e Zhao Yakui                    2009-03-03   4465  #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
771cb081354161e Zhao Yakui                    2009-03-03   4466  #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   4467  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4468  #define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
0ce99f749b3834e Daniel Vetter                 2013-07-26   4469  /*
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4470   * HDMI/DP bits are g4x+
0ce99f749b3834e Daniel Vetter                 2013-07-26   4471   *
0ce99f749b3834e Daniel Vetter                 2013-07-26   4472   * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
0ce99f749b3834e Daniel Vetter                 2013-07-26   4473   * Please check the detailed lore in the commit message for for experimental
0ce99f749b3834e Daniel Vetter                 2013-07-26   4474   * evidence.
0ce99f749b3834e Daniel Vetter                 2013-07-26   4475   */
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4476  /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4477  #define   PORTD_HOTPLUG_LIVE_STATUS_GM45	(1 << 29)
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4478  #define   PORTC_HOTPLUG_LIVE_STATUS_GM45	(1 << 28)
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4479  #define   PORTB_HOTPLUG_LIVE_STATUS_GM45	(1 << 27)
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4480  /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4481  #define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
232a6ee9af8adb1 Todd Previte                  2014-01-23   4482  #define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
0780cd36c7af70c Ville Syrjälä                 2016-02-10   4483  #define   PORTB_HOTPLUG_LIVE_STATUS_G4X		(1 << 29)
26739f12cf210cb Daniel Vetter                 2013-02-07   4484  #define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
a211b497eb95b0b Daniel Vetter                 2014-06-05   4485  #define   PORTD_HOTPLUG_INT_LONG_PULSE		(2 << 21)
a211b497eb95b0b Daniel Vetter                 2014-06-05   4486  #define   PORTD_HOTPLUG_INT_SHORT_PULSE		(1 << 21)
26739f12cf210cb Daniel Vetter                 2013-02-07   4487  #define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
a211b497eb95b0b Daniel Vetter                 2014-06-05   4488  #define   PORTC_HOTPLUG_INT_LONG_PULSE		(2 << 19)
a211b497eb95b0b Daniel Vetter                 2014-06-05   4489  #define   PORTC_HOTPLUG_INT_SHORT_PULSE		(1 << 19)
26739f12cf210cb Daniel Vetter                 2013-02-07   4490  #define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
a211b497eb95b0b Daniel Vetter                 2014-06-05   4491  #define   PORTB_HOTPLUG_INT_LONG_PULSE		(2 << 17)
a211b497eb95b0b Daniel Vetter                 2014-06-05   4492  #define   PORTB_HOTPLUG_INT_SHORT_PLUSE		(1 << 17)
084b612ecf8e599 Chris Wilson                  2012-05-11   4493  /* CRT/TV common between gen3+ */
585fb111348f7cd Jesse Barnes                  2008-07-29   4494  #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
585fb111348f7cd Jesse Barnes                  2008-07-29   4495  #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4496  #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   4497  #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   4498  #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   4499  #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
4aeebd7443e36b0 Daniel Vetter                 2013-10-31   4500  #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X	(1 << 6)
4aeebd7443e36b0 Daniel Vetter                 2013-10-31   4501  #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X	(1 << 5)
4aeebd7443e36b0 Daniel Vetter                 2013-10-31   4502  #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X	(1 << 4)
bfbdb420f514579 Imre Deak                     2014-01-16   4503  #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X	(7 << 4)
bfbdb420f514579 Imre Deak                     2014-01-16   4504  
084b612ecf8e599 Chris Wilson                  2012-05-11   4505  /* SDVO is different across gen3/4 */
084b612ecf8e599 Chris Wilson                  2012-05-11   4506  #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
084b612ecf8e599 Chris Wilson                  2012-05-11   4507  #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
4f7fd7095d85cd3 Daniel Vetter                 2013-06-24   4508  /*
4f7fd7095d85cd3 Daniel Vetter                 2013-06-24   4509   * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4f7fd7095d85cd3 Daniel Vetter                 2013-06-24   4510   * since reality corrobates that they're the same as on gen3. But keep these
4f7fd7095d85cd3 Daniel Vetter                 2013-06-24   4511   * bits here (and the comment!) to help any other lost wanderers back onto the
4f7fd7095d85cd3 Daniel Vetter                 2013-06-24   4512   * right tracks.
4f7fd7095d85cd3 Daniel Vetter                 2013-06-24   4513   */
084b612ecf8e599 Chris Wilson                  2012-05-11   4514  #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
084b612ecf8e599 Chris Wilson                  2012-05-11   4515  #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
084b612ecf8e599 Chris Wilson                  2012-05-11   4516  #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
084b612ecf8e599 Chris Wilson                  2012-05-11   4517  #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
e5868a318d1ae28 Egbert Eich                   2013-02-28   4518  #define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4519  						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4520  						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4521  						 PORTB_HOTPLUG_INT_STATUS | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4522  						 PORTC_HOTPLUG_INT_STATUS | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4523  						 PORTD_HOTPLUG_INT_STATUS)
e5868a318d1ae28 Egbert Eich                   2013-02-28   4524  
e5868a318d1ae28 Egbert Eich                   2013-02-28   4525  #define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4526  						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4527  						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4528  						 PORTB_HOTPLUG_INT_STATUS | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4529  						 PORTC_HOTPLUG_INT_STATUS | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   4530  						 PORTD_HOTPLUG_INT_STATUS)
585fb111348f7cd Jesse Barnes                  2008-07-29   4531  
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4532  /* SDVO and HDMI port control.
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4533   * The same register may be used for SDVO or HDMI */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4534  #define _GEN3_SDVOB	0x61140
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4535  #define _GEN3_SDVOC	0x61160
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4536  #define GEN3_SDVOB	_MMIO(_GEN3_SDVOB)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4537  #define GEN3_SDVOC	_MMIO(_GEN3_SDVOC)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4538  #define GEN4_HDMIB	GEN3_SDVOB
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4539  #define GEN4_HDMIC	GEN3_SDVOC
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4540  #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4541  #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4542  #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4543  #define PCH_SDVOB	_MMIO(0xe1140)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4544  #define PCH_HDMIB	PCH_SDVOB
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4545  #define PCH_HDMIC	_MMIO(0xe1150)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4546  #define PCH_HDMID	_MMIO(0xe1160)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4547  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4548  #define PORT_DFT_I9XX				_MMIO(0x61150)
8409360381ebaaa Daniel Vetter                 2013-11-01   4549  #define   DC_BALANCE_RESET			(1 << 25)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4550  #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
8409360381ebaaa Daniel Vetter                 2013-11-01   4551  #define   DC_BALANCE_RESET_VLV			(1 << 31)
eb736679aa7e6d6 Ville Syrjälä                 2014-12-09   4552  #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
eb736679aa7e6d6 Ville Syrjälä                 2014-12-09   4553  #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
8409360381ebaaa Daniel Vetter                 2013-11-01   4554  #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
8409360381ebaaa Daniel Vetter                 2013-11-01   4555  #define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
8409360381ebaaa Daniel Vetter                 2013-11-01   4556  
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4557  /* Gen 3 SDVO bits: */
585fb111348f7cd Jesse Barnes                  2008-07-29   4558  #define   SDVO_ENABLE				(1 << 31)
762034675ee7476 Ville Syrjälä                 2018-05-14   4559  #define   SDVO_PIPE_SEL_SHIFT			30
dc0fa7181132b1f Paulo Zanoni                  2013-02-19   4560  #define   SDVO_PIPE_SEL_MASK			(1 << 30)
762034675ee7476 Ville Syrjälä                 2018-05-14   4561  #define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   4562  #define   SDVO_STALL_SELECT			(1 << 29)
585fb111348f7cd Jesse Barnes                  2008-07-29   4563  #define   SDVO_INTERRUPT_ENABLE			(1 << 26)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4564  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4565   * 915G/GM SDVO pixel multiplier.
585fb111348f7cd Jesse Barnes                  2008-07-29   4566   * Programmed value is multiplier - 1, up to 5x.
585fb111348f7cd Jesse Barnes                  2008-07-29   4567   * \sa DPLL_MD_UDI_MULTIPLIER_MASK
585fb111348f7cd Jesse Barnes                  2008-07-29   4568   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4569  #define   SDVO_PORT_MULTIPLY_MASK		(7 << 23)
585fb111348f7cd Jesse Barnes                  2008-07-29   4570  #define   SDVO_PORT_MULTIPLY_SHIFT		23
585fb111348f7cd Jesse Barnes                  2008-07-29   4571  #define   SDVO_PHASE_SELECT_MASK		(15 << 19)
585fb111348f7cd Jesse Barnes                  2008-07-29   4572  #define   SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
585fb111348f7cd Jesse Barnes                  2008-07-29   4573  #define   SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4574  #define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4575  #define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4576  #define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4577  #define   SDVO_DETECTED				(1 << 2)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4578  /* Bits to be preserved when writing */
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4579  #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4580  			       SDVO_INTERRUPT_ENABLE)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4581  #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4582  
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4583  /* Gen 4 SDVO/HDMI bits: */
4f3a8bc7ba6e344 Paulo Zanoni                  2013-02-19   4584  #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
18442d08786472c Ville Syrjälä                 2013-09-13   4585  #define   SDVO_COLOR_FORMAT_MASK		(7 << 26)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4586  #define   SDVO_ENCODING_SDVO			(0 << 10)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4587  #define   SDVO_ENCODING_HDMI			(2 << 10)
dc0fa7181132b1f Paulo Zanoni                  2013-02-19   4588  #define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
dc0fa7181132b1f Paulo Zanoni                  2013-02-19   4589  #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
4f3a8bc7ba6e344 Paulo Zanoni                  2013-02-19   4590  #define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
dd6090f8780a213 Ville Syrjälä                 2019-04-09   4591  #define   HDMI_AUDIO_ENABLE			(1 << 6) /* HDMI only */
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4592  /* VSYNC/HSYNC bits new with 965, default is to be set */
7d57382e65994ab Eric Anholt                   2009-01-02   4593  #define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)
7d57382e65994ab Eric Anholt                   2009-01-02   4594  #define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4595  
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4596  /* Gen 5 (IBX) SDVO/HDMI bits: */
4f3a8bc7ba6e344 Paulo Zanoni                  2013-02-19   4597  #define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4598  #define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4599  
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4600  /* Gen 6 (CPT) SDVO/HDMI bits: */
762034675ee7476 Ville Syrjälä                 2018-05-14   4601  #define   SDVO_PIPE_SEL_SHIFT_CPT		29
dc0fa7181132b1f Paulo Zanoni                  2013-02-19   4602  #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
762034675ee7476 Ville Syrjälä                 2018-05-14   4603  #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
c20cd31252554b9 Paulo Zanoni                  2013-02-19   4604  
44f37d1f528a5b7 Chon Ming Lee                 2014-04-09   4605  /* CHV SDVO/HDMI bits: */
762034675ee7476 Ville Syrjälä                 2018-05-14   4606  #define   SDVO_PIPE_SEL_SHIFT_CHV		24
44f37d1f528a5b7 Chon Ming Lee                 2014-04-09   4607  #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
762034675ee7476 Ville Syrjälä                 2018-05-14   4608  #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
44f37d1f528a5b7 Chon Ming Lee                 2014-04-09   4609  
585fb111348f7cd Jesse Barnes                  2008-07-29   4610  
585fb111348f7cd Jesse Barnes                  2008-07-29   4611  /* DVO port control */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4612  #define _DVOA			0x61120
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4613  #define DVOA			_MMIO(_DVOA)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4614  #define _DVOB			0x61140
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4615  #define DVOB			_MMIO(_DVOB)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4616  #define _DVOC			0x61160
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4617  #define DVOC			_MMIO(_DVOC)
585fb111348f7cd Jesse Barnes                  2008-07-29   4618  #define   DVO_ENABLE			(1 << 31)
b45a258897a4a37 Ville Syrjälä                 2018-05-14   4619  #define   DVO_PIPE_SEL_SHIFT		30
b45a258897a4a37 Ville Syrjälä                 2018-05-14   4620  #define   DVO_PIPE_SEL_MASK		(1 << 30)
b45a258897a4a37 Ville Syrjälä                 2018-05-14   4621  #define   DVO_PIPE_SEL(pipe)		((pipe) << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   4622  #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   4623  #define   DVO_PIPE_STALL		(1 << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   4624  #define   DVO_PIPE_STALL_TV		(2 << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   4625  #define   DVO_PIPE_STALL_MASK		(3 << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   4626  #define   DVO_USE_VGA_SYNC		(1 << 15)
585fb111348f7cd Jesse Barnes                  2008-07-29   4627  #define   DVO_DATA_ORDER_I740		(0 << 14)
585fb111348f7cd Jesse Barnes                  2008-07-29   4628  #define   DVO_DATA_ORDER_FP		(1 << 14)
585fb111348f7cd Jesse Barnes                  2008-07-29   4629  #define   DVO_VSYNC_DISABLE		(1 << 11)
585fb111348f7cd Jesse Barnes                  2008-07-29   4630  #define   DVO_HSYNC_DISABLE		(1 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4631  #define   DVO_VSYNC_TRISTATE		(1 << 9)
585fb111348f7cd Jesse Barnes                  2008-07-29   4632  #define   DVO_HSYNC_TRISTATE		(1 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   4633  #define   DVO_BORDER_ENABLE		(1 << 7)
585fb111348f7cd Jesse Barnes                  2008-07-29   4634  #define   DVO_DATA_ORDER_GBRG		(1 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4635  #define   DVO_DATA_ORDER_RGGB		(0 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4636  #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4637  #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4638  #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   4639  #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
585fb111348f7cd Jesse Barnes                  2008-07-29   4640  #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   4641  #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
585fb111348f7cd Jesse Barnes                  2008-07-29   4642  #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
585fb111348f7cd Jesse Barnes                  2008-07-29   4643  #define   DVO_PRESERVE_MASK		(0x7 << 24)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4644  #define DVOA_SRCDIM		_MMIO(0x61124)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4645  #define DVOB_SRCDIM		_MMIO(0x61144)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4646  #define DVOC_SRCDIM		_MMIO(0x61164)
585fb111348f7cd Jesse Barnes                  2008-07-29   4647  #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
585fb111348f7cd Jesse Barnes                  2008-07-29   4648  #define   DVO_SRCDIM_VERTICAL_SHIFT	0
585fb111348f7cd Jesse Barnes                  2008-07-29   4649  
585fb111348f7cd Jesse Barnes                  2008-07-29   4650  /* LVDS port control */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4651  #define LVDS			_MMIO(0x61180)
585fb111348f7cd Jesse Barnes                  2008-07-29   4652  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4653   * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
585fb111348f7cd Jesse Barnes                  2008-07-29   4654   * the DPLL semantics change when the LVDS is assigned to that pipe.
585fb111348f7cd Jesse Barnes                  2008-07-29   4655   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4656  #define   LVDS_PORT_EN			(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   4657  /* Selects pipe B for LVDS data.  Must be set on pre-965. */
a44628b9293b81b Ville Syrjälä                 2018-05-14   4658  #define   LVDS_PIPE_SEL_SHIFT		30
a44628b9293b81b Ville Syrjälä                 2018-05-14   4659  #define   LVDS_PIPE_SEL_MASK		(1 << 30)
a44628b9293b81b Ville Syrjälä                 2018-05-14   4660  #define   LVDS_PIPE_SEL(pipe)		((pipe) << 30)
a44628b9293b81b Ville Syrjälä                 2018-05-14   4661  #define   LVDS_PIPE_SEL_SHIFT_CPT	29
a44628b9293b81b Ville Syrjälä                 2018-05-14   4662  #define   LVDS_PIPE_SEL_MASK_CPT	(3 << 29)
a44628b9293b81b Ville Syrjälä                 2018-05-14   4663  #define   LVDS_PIPE_SEL_CPT(pipe)	((pipe) << 29)
898822ce9561ab9 Zhao Yakui                    2010-01-04   4664  /* LVDS dithering flag on 965/g4x platform */
898822ce9561ab9 Zhao Yakui                    2010-01-04   4665  #define   LVDS_ENABLE_DITHER		(1 << 25)
aa9b500ddf1a631 Bryan Freed                   2011-01-12   4666  /* LVDS sync polarity flags. Set to invert (i.e. negative) */
aa9b500ddf1a631 Bryan Freed                   2011-01-12   4667  #define   LVDS_VSYNC_POLARITY		(1 << 21)
aa9b500ddf1a631 Bryan Freed                   2011-01-12   4668  #define   LVDS_HSYNC_POLARITY		(1 << 20)
aa9b500ddf1a631 Bryan Freed                   2011-01-12   4669  
a3e17eb8f4080a7 Zhao Yakui                    2009-10-10   4670  /* Enable border for unscaled (or aspect-scaled) display */
a3e17eb8f4080a7 Zhao Yakui                    2009-10-10   4671  #define   LVDS_BORDER_ENABLE		(1 << 15)
585fb111348f7cd Jesse Barnes                  2008-07-29   4672  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4673   * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
585fb111348f7cd Jesse Barnes                  2008-07-29   4674   * pixel.
585fb111348f7cd Jesse Barnes                  2008-07-29   4675   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4676  #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   4677  #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   4678  #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   4679  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4680   * Controls the A3 data pair, which contains the additional LSBs for 24 bit
585fb111348f7cd Jesse Barnes                  2008-07-29   4681   * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
585fb111348f7cd Jesse Barnes                  2008-07-29   4682   * on.
585fb111348f7cd Jesse Barnes                  2008-07-29   4683   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4684  #define   LVDS_A3_POWER_MASK		(3 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4685  #define   LVDS_A3_POWER_DOWN		(0 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4686  #define   LVDS_A3_POWER_UP		(3 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4687  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4688   * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
585fb111348f7cd Jesse Barnes                  2008-07-29   4689   * is set.
585fb111348f7cd Jesse Barnes                  2008-07-29   4690   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4691  #define   LVDS_CLKB_POWER_MASK		(3 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   4692  #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   4693  #define   LVDS_CLKB_POWER_UP		(3 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   4694  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4695   * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
585fb111348f7cd Jesse Barnes                  2008-07-29   4696   * setting for whether we are in dual-channel mode.  The B3 pair will
585fb111348f7cd Jesse Barnes                  2008-07-29   4697   * additionally only be powered up when LVDS_A3_POWER_UP is set.
585fb111348f7cd Jesse Barnes                  2008-07-29   4698   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4699  #define   LVDS_B0B3_POWER_MASK		(3 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   4700  #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   4701  #define   LVDS_B0B3_POWER_UP		(3 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   4702  
3c17fe4b8f40a11 David Härdeman                2010-09-24   4703  /* Video Data Island Packet control */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4704  #define VIDEO_DIP_DATA		_MMIO(0x61178)
fd0753cf8052bc6 Yannick Guerrini              2015-02-28   4705  /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
adf00b26d18e1b3 Paulo Zanoni                  2012-09-25   4706   * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
adf00b26d18e1b3 Paulo Zanoni                  2012-09-25   4707   * of the infoframe structure specified by CEA-861. */
adf00b26d18e1b3 Paulo Zanoni                  2012-09-25   4708  #define   VIDEO_DIP_DATA_SIZE	32
2b28bb1b6440fad Rodrigo Vivi                  2013-07-11   4709  #define   VIDEO_DIP_VSC_DATA_SIZE	36
4c614831d59bb3d Manasi Navare                 2018-11-28   4710  #define   VIDEO_DIP_PPS_DATA_SIZE	132
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4711  #define VIDEO_DIP_CTL		_MMIO(0x61170)
2da8af54059bd8c Paulo Zanoni                  2012-05-14   4712  /* Pre HSW: */
3c17fe4b8f40a11 David Härdeman                2010-09-24   4713  #define   VIDEO_DIP_ENABLE		(1 << 31)
822cdc52936e026 Ville Syrjälä                 2014-01-23   4714  #define   VIDEO_DIP_PORT(port)		((port) << 29)
3e6e63952f6f7a4 Paulo Zanoni                  2012-05-04   4715  #define   VIDEO_DIP_PORT_MASK		(3 << 29)
5cb3c1a123fc337 Ville Syrjälä                 2019-02-25   4716  #define   VIDEO_DIP_ENABLE_GCP		(1 << 25) /* ilk+ */
3c17fe4b8f40a11 David Härdeman                2010-09-24   4717  #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
3c17fe4b8f40a11 David Härdeman                2010-09-24   4718  #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
5cb3c1a123fc337 Ville Syrjälä                 2019-02-25   4719  #define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21) /* ilk+ */
3c17fe4b8f40a11 David Härdeman                2010-09-24   4720  #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
3c17fe4b8f40a11 David Härdeman                2010-09-24   4721  #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
3c17fe4b8f40a11 David Härdeman                2010-09-24   4722  #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
5cb3c1a123fc337 Ville Syrjälä                 2019-02-25   4723  #define   VIDEO_DIP_SELECT_GAMUT	(2 << 19)
3c17fe4b8f40a11 David Härdeman                2010-09-24   4724  #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
45187ace97f7b3d Jesse Barnes                  2011-08-03   4725  #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
3c17fe4b8f40a11 David Härdeman                2010-09-24   4726  #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
3c17fe4b8f40a11 David Härdeman                2010-09-24   4727  #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
3c17fe4b8f40a11 David Härdeman                2010-09-24   4728  #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
60c5ea2dd981d92 Paulo Zanoni                  2012-05-04   4729  #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
2da8af54059bd8c Paulo Zanoni                  2012-05-14   4730  /* HSW and later: */
44b42ebfccfd9d6 Ville Syrjälä                 2019-05-17   4731  #define   VIDEO_DIP_ENABLE_DRM_GLK	(1 << 28)
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   4732  #define   PSR_VSC_BIT_7_SET		(1 << 27)
09209662618f9fd Dhinakaran Pandiyan           2018-10-05   4733  #define   VSC_SELECT_MASK		(0x3 << 25)
09209662618f9fd Dhinakaran Pandiyan           2018-10-05   4734  #define   VSC_SELECT_SHIFT		25
09209662618f9fd Dhinakaran Pandiyan           2018-10-05   4735  #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
09209662618f9fd Dhinakaran Pandiyan           2018-10-05   4736  #define   VSC_DIP_HW_HEA_SW_DATA	(1 << 25)
09209662618f9fd Dhinakaran Pandiyan           2018-10-05   4737  #define   VSC_DIP_HW_DATA_SW_HEA	(2 << 25)
09209662618f9fd Dhinakaran Pandiyan           2018-10-05   4738  #define   VSC_DIP_SW_HEA_DATA		(3 << 25)
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   4739  #define   VDIP_ENABLE_PPS		(1 << 24)
a670be330501243 Dhinakaran Pandiyan           2018-10-05   4740  #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
a670be330501243 Dhinakaran Pandiyan           2018-10-05   4741  #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
a670be330501243 Dhinakaran Pandiyan           2018-10-05   4742  #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
a670be330501243 Dhinakaran Pandiyan           2018-10-05   4743  #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
a670be330501243 Dhinakaran Pandiyan           2018-10-05   4744  #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
a670be330501243 Dhinakaran Pandiyan           2018-10-05   4745  #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   4746  
585fb111348f7cd Jesse Barnes                  2008-07-29   4747  /* Panel power sequencing */
44cb734cd2ea09e Imre Deak                     2016-08-10   4748  #define PPS_BASE			0x61200
44cb734cd2ea09e Imre Deak                     2016-08-10   4749  #define VLV_PPS_BASE			(VLV_DISPLAY_BASE + PPS_BASE)
44cb734cd2ea09e Imre Deak                     2016-08-10   4750  #define PCH_PPS_BASE			0xC7200
44cb734cd2ea09e Imre Deak                     2016-08-10   4751  
44cb734cd2ea09e Imre Deak                     2016-08-10   4752  #define _MMIO_PPS(pps_idx, reg)		_MMIO(dev_priv->pps_mmio_base -	\
44cb734cd2ea09e Imre Deak                     2016-08-10   4753  					      PPS_BASE + (reg) +	\
44cb734cd2ea09e Imre Deak                     2016-08-10   4754  					      (pps_idx) * 0x100)
44cb734cd2ea09e Imre Deak                     2016-08-10   4755  
44cb734cd2ea09e Imre Deak                     2016-08-10   4756  #define _PP_STATUS			0x61200
44cb734cd2ea09e Imre Deak                     2016-08-10   4757  #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4758  #define   PP_ON				REG_BIT(31)
f4ff2120301d85c Madhav Chauhan                2018-11-29   4759  
f4ff2120301d85c Madhav Chauhan                2018-11-29   4760  #define _PP_CONTROL_1			0xc7204
f4ff2120301d85c Madhav Chauhan                2018-11-29   4761  #define _PP_CONTROL_2			0xc7304
f4ff2120301d85c Madhav Chauhan                2018-11-29   4762  #define ICP_PP_CONTROL(x)		_MMIO(((x) == 1) ? _PP_CONTROL_1 : \
f4ff2120301d85c Madhav Chauhan                2018-11-29   4763  					      _PP_CONTROL_2)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4764  #define  POWER_CYCLE_DELAY_MASK		REG_GENMASK(8, 4)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4765  #define  VDD_OVERRIDE_FORCE		REG_BIT(3)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4766  #define  BACKLIGHT_ENABLE		REG_BIT(2)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4767  #define  PWR_DOWN_ON_RESET		REG_BIT(1)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4768  #define  PWR_STATE_TARGET		REG_BIT(0)
585fb111348f7cd Jesse Barnes                  2008-07-29   4769  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4770   * Indicates that all dependencies of the panel are on:
585fb111348f7cd Jesse Barnes                  2008-07-29   4771   *
585fb111348f7cd Jesse Barnes                  2008-07-29   4772   * - PLL enabled
585fb111348f7cd Jesse Barnes                  2008-07-29   4773   * - pipe enabled
585fb111348f7cd Jesse Barnes                  2008-07-29   4774   * - LVDS/DVOB/DVOC on
585fb111348f7cd Jesse Barnes                  2008-07-29   4775   */
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4776  #define   PP_READY			REG_BIT(30)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4777  #define   PP_SEQUENCE_MASK		REG_GENMASK(29, 28)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4778  #define   PP_SEQUENCE_NONE		REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4779  #define   PP_SEQUENCE_POWER_UP		REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4780  #define   PP_SEQUENCE_POWER_DOWN	REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4781  #define   PP_CYCLE_DELAY_ACTIVE		REG_BIT(27)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4782  #define   PP_SEQUENCE_STATE_MASK	REG_GENMASK(3, 0)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4783  #define   PP_SEQUENCE_STATE_OFF_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4784  #define   PP_SEQUENCE_STATE_OFF_S0_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4785  #define   PP_SEQUENCE_STATE_OFF_S0_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4786  #define   PP_SEQUENCE_STATE_OFF_S0_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4787  #define   PP_SEQUENCE_STATE_ON_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4788  #define   PP_SEQUENCE_STATE_ON_S1_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4789  #define   PP_SEQUENCE_STATE_ON_S1_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4790  #define   PP_SEQUENCE_STATE_ON_S1_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4791  #define   PP_SEQUENCE_STATE_RESET	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
44cb734cd2ea09e Imre Deak                     2016-08-10   4792  
44cb734cd2ea09e Imre Deak                     2016-08-10   4793  #define _PP_CONTROL			0x61204
44cb734cd2ea09e Imre Deak                     2016-08-10   4794  #define PP_CONTROL(pps_idx)		_MMIO_PPS(pps_idx, _PP_CONTROL)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4795  #define  PANEL_UNLOCK_MASK		REG_GENMASK(31, 16)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4796  #define  PANEL_UNLOCK_REGS		REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4797  #define  BXT_POWER_CYCLE_DELAY_MASK	REG_GENMASK(8, 4)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4798  #define  EDP_FORCE_VDD			REG_BIT(3)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4799  #define  EDP_BLC_ENABLE			REG_BIT(2)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4800  #define  PANEL_POWER_RESET		REG_BIT(1)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4801  #define  PANEL_POWER_ON			REG_BIT(0)
44cb734cd2ea09e Imre Deak                     2016-08-10   4802  
44cb734cd2ea09e Imre Deak                     2016-08-10   4803  #define _PP_ON_DELAYS			0x61208
44cb734cd2ea09e Imre Deak                     2016-08-10   4804  #define PP_ON_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_ON_DELAYS)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4805  #define  PANEL_PORT_SELECT_MASK		REG_GENMASK(31, 30)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4806  #define  PANEL_PORT_SELECT_LVDS		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4807  #define  PANEL_PORT_SELECT_DPA		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4808  #define  PANEL_PORT_SELECT_DPC		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4809  #define  PANEL_PORT_SELECT_DPD		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
baa09e7d2f423a6 Jani Nikula                   2019-03-15   4810  #define  PANEL_PORT_SELECT_VLV(port)	REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4811  #define  PANEL_POWER_UP_DELAY_MASK	REG_GENMASK(28, 16)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4812  #define  PANEL_LIGHT_ON_DELAY_MASK	REG_GENMASK(12, 0)
44cb734cd2ea09e Imre Deak                     2016-08-10   4813  
44cb734cd2ea09e Imre Deak                     2016-08-10   4814  #define _PP_OFF_DELAYS			0x6120C
44cb734cd2ea09e Imre Deak                     2016-08-10   4815  #define PP_OFF_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4816  #define  PANEL_POWER_DOWN_DELAY_MASK	REG_GENMASK(28, 16)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4817  #define  PANEL_LIGHT_OFF_DELAY_MASK	REG_GENMASK(12, 0)
44cb734cd2ea09e Imre Deak                     2016-08-10   4818  
44cb734cd2ea09e Imre Deak                     2016-08-10   4819  #define _PP_DIVISOR			0x61210
44cb734cd2ea09e Imre Deak                     2016-08-10   4820  #define PP_DIVISOR(pps_idx)		_MMIO_PPS(pps_idx, _PP_DIVISOR)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4821  #define  PP_REFERENCE_DIVIDER_MASK	REG_GENMASK(31, 8)
09b434d4f6d22e1 Jani Nikula                   2019-03-15   4822  #define  PANEL_POWER_CYCLE_DELAY_MASK	REG_GENMASK(4, 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   4823  
585fb111348f7cd Jesse Barnes                  2008-07-29   4824  /* Panel fitting */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4825  #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
585fb111348f7cd Jesse Barnes                  2008-07-29   4826  #define   PFIT_ENABLE		(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   4827  #define   PFIT_PIPE_MASK	(3 << 29)
585fb111348f7cd Jesse Barnes                  2008-07-29   4828  #define   PFIT_PIPE_SHIFT	29
585fb111348f7cd Jesse Barnes                  2008-07-29   4829  #define   VERT_INTERP_DISABLE	(0 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4830  #define   VERT_INTERP_BILINEAR	(1 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4831  #define   VERT_INTERP_MASK	(3 << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   4832  #define   VERT_AUTO_SCALE	(1 << 9)
585fb111348f7cd Jesse Barnes                  2008-07-29   4833  #define   HORIZ_INTERP_DISABLE	(0 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4834  #define   HORIZ_INTERP_BILINEAR	(1 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4835  #define   HORIZ_INTERP_MASK	(3 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   4836  #define   HORIZ_AUTO_SCALE	(1 << 5)
585fb111348f7cd Jesse Barnes                  2008-07-29   4837  #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4838  #define   PFIT_FILTER_FUZZY	(0 << 24)
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4839  #define   PFIT_SCALING_AUTO	(0 << 26)
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4840  #define   PFIT_SCALING_PROGRAMMED (1 << 26)
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4841  #define   PFIT_SCALING_PILLAR	(2 << 26)
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4842  #define   PFIT_SCALING_LETTER	(3 << 26)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4843  #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4844  /* Pre-965 */
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4845  #define		PFIT_VERT_SCALE_SHIFT		20
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4846  #define		PFIT_VERT_SCALE_MASK		0xfff00000
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4847  #define		PFIT_HORIZ_SCALE_SHIFT		4
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4848  #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4849  /* 965+ */
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4850  #define		PFIT_VERT_SCALE_SHIFT_965	16
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4851  #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4852  #define		PFIT_HORIZ_SCALE_SHIFT_965	0
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4853  #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
3fbe18d65d66054 Zhao Yakui                    2009-06-22   4854  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4855  #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
585fb111348f7cd Jesse Barnes                  2008-07-29   4856  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4857  #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4858  #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4859  #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
07bf139b906013e Jesse Barnes                  2013-10-31   4860  					 _VLV_BLC_PWM_CTL2_B)
07bf139b906013e Jesse Barnes                  2013-10-31   4861  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4862  #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4863  #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4864  #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
07bf139b906013e Jesse Barnes                  2013-10-31   4865  					_VLV_BLC_PWM_CTL_B)
07bf139b906013e Jesse Barnes                  2013-10-31   4866  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4867  #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4868  #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4869  #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
07bf139b906013e Jesse Barnes                  2013-10-31   4870  					 _VLV_BLC_HIST_CTL_B)
07bf139b906013e Jesse Barnes                  2013-10-31   4871  
585fb111348f7cd Jesse Barnes                  2008-07-29   4872  /* Backlight control */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4873  #define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
7cf4160148136de Daniel Vetter                 2012-06-05   4874  #define   BLM_PWM_ENABLE		(1 << 31)
7cf4160148136de Daniel Vetter                 2012-06-05   4875  #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
7cf4160148136de Daniel Vetter                 2012-06-05   4876  #define   BLM_PIPE_SELECT		(1 << 29)
7cf4160148136de Daniel Vetter                 2012-06-05   4877  #define   BLM_PIPE_SELECT_IVB		(3 << 29)
7cf4160148136de Daniel Vetter                 2012-06-05   4878  #define   BLM_PIPE_A			(0 << 29)
7cf4160148136de Daniel Vetter                 2012-06-05   4879  #define   BLM_PIPE_B			(1 << 29)
7cf4160148136de Daniel Vetter                 2012-06-05   4880  #define   BLM_PIPE_C			(2 << 29) /* ivb + */
35ffda4883a8d3f Jani Nikula                   2013-04-25   4881  #define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
35ffda4883a8d3f Jani Nikula                   2013-04-25   4882  #define   BLM_TRANSCODER_B		BLM_PIPE_B
35ffda4883a8d3f Jani Nikula                   2013-04-25   4883  #define   BLM_TRANSCODER_C		BLM_PIPE_C
35ffda4883a8d3f Jani Nikula                   2013-04-25   4884  #define   BLM_TRANSCODER_EDP		(3 << 29)
7cf4160148136de Daniel Vetter                 2012-06-05   4885  #define   BLM_PIPE(pipe)		((pipe) << 29)
7cf4160148136de Daniel Vetter                 2012-06-05   4886  #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
7cf4160148136de Daniel Vetter                 2012-06-05   4887  #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
7cf4160148136de Daniel Vetter                 2012-06-05   4888  #define   BLM_PHASE_IN_ENABLE		(1 << 25)
7cf4160148136de Daniel Vetter                 2012-06-05   4889  #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
7cf4160148136de Daniel Vetter                 2012-06-05   4890  #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
7cf4160148136de Daniel Vetter                 2012-06-05   4891  #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
7cf4160148136de Daniel Vetter                 2012-06-05   4892  #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
7cf4160148136de Daniel Vetter                 2012-06-05   4893  #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
7cf4160148136de Daniel Vetter                 2012-06-05   4894  #define   BLM_PHASE_IN_INCR_SHIFT	(0)
7cf4160148136de Daniel Vetter                 2012-06-05   4895  #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4896  #define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
ba3820ade317ee3 Takashi Iwai                  2011-03-10   4897  /*
ba3820ade317ee3 Takashi Iwai                  2011-03-10   4898   * This is the most significant 15 bits of the number of backlight cycles in a
ba3820ade317ee3 Takashi Iwai                  2011-03-10   4899   * complete cycle of the modulated backlight control.
ba3820ade317ee3 Takashi Iwai                  2011-03-10   4900   *
ba3820ade317ee3 Takashi Iwai                  2011-03-10   4901   * The actual value is this field multiplied by two.
ba3820ade317ee3 Takashi Iwai                  2011-03-10   4902   */
7cf4160148136de Daniel Vetter                 2012-06-05   4903  #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
ba3820ade317ee3 Takashi Iwai                  2011-03-10   4904  #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
7cf4160148136de Daniel Vetter                 2012-06-05   4905  #define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
585fb111348f7cd Jesse Barnes                  2008-07-29   4906  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   4907   * This is the number of cycles out of the backlight modulation cycle for which
585fb111348f7cd Jesse Barnes                  2008-07-29   4908   * the backlight is on.
585fb111348f7cd Jesse Barnes                  2008-07-29   4909   *
585fb111348f7cd Jesse Barnes                  2008-07-29   4910   * This field must be no greater than the number of cycles in the complete
585fb111348f7cd Jesse Barnes                  2008-07-29   4911   * backlight modulation cycle.
585fb111348f7cd Jesse Barnes                  2008-07-29   4912   */
585fb111348f7cd Jesse Barnes                  2008-07-29   4913  #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
585fb111348f7cd Jesse Barnes                  2008-07-29   4914  #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
534b5a5341cb7e1 Daniel Vetter                 2012-06-05   4915  #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
534b5a5341cb7e1 Daniel Vetter                 2012-06-05   4916  #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
585fb111348f7cd Jesse Barnes                  2008-07-29   4917  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   4918  #define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
2059ac3b1304cb6 Jani Nikula                   2015-06-26   4919  #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
0eb96d6ed38430b Jesse Barnes                  2009-10-14   4920  
7cf4160148136de Daniel Vetter                 2012-06-05   4921  /* New registers for PCH-split platforms. Safe where new bits show up, the
7cf4160148136de Daniel Vetter                 2012-06-05   4922   * register layout machtes with gen4 BLC_PWM_CTL[12]. */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4923  #define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4924  #define BLC_PWM_CPU_CTL		_MMIO(0x48254)
7cf4160148136de Daniel Vetter                 2012-06-05   4925  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4926  #define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
be256dc70284c02 Paulo Zanoni                  2013-07-23   4927  
7cf4160148136de Daniel Vetter                 2012-06-05   4928  /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
7cf4160148136de Daniel Vetter                 2012-06-05   4929   * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4930  #define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
4b4147c38f89dea Daniel Vetter                 2012-07-11   4931  #define   BLM_PCH_PWM_ENABLE			(1 << 31)
7cf4160148136de Daniel Vetter                 2012-06-05   4932  #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
7cf4160148136de Daniel Vetter                 2012-06-05   4933  #define   BLM_PCH_POLARITY			(1 << 29)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4934  #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
7cf4160148136de Daniel Vetter                 2012-06-05   4935  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4936  #define UTIL_PIN_CTL		_MMIO(0x48400)
be256dc70284c02 Paulo Zanoni                  2013-07-23   4937  #define   UTIL_PIN_ENABLE	(1 << 31)
be256dc70284c02 Paulo Zanoni                  2013-07-23   4938  
022e4e52a750066 Sunil Kamath                  2015-09-30   4939  #define   UTIL_PIN_PIPE(x)     ((x) << 29)
022e4e52a750066 Sunil Kamath                  2015-09-30   4940  #define   UTIL_PIN_PIPE_MASK   (3 << 29)
022e4e52a750066 Sunil Kamath                  2015-09-30   4941  #define   UTIL_PIN_MODE_PWM    (1 << 24)
022e4e52a750066 Sunil Kamath                  2015-09-30   4942  #define   UTIL_PIN_MODE_MASK   (0xf << 24)
022e4e52a750066 Sunil Kamath                  2015-09-30   4943  #define   UTIL_PIN_POLARITY    (1 << 22)
022e4e52a750066 Sunil Kamath                  2015-09-30   4944  
0fb890c01349c52 Vandana Kannan                2015-05-05   4945  /* BXT backlight register definition. */
022e4e52a750066 Sunil Kamath                  2015-09-30   4946  #define _BXT_BLC_PWM_CTL1			0xC8250
0fb890c01349c52 Vandana Kannan                2015-05-05   4947  #define   BXT_BLC_PWM_ENABLE			(1 << 31)
0fb890c01349c52 Vandana Kannan                2015-05-05   4948  #define   BXT_BLC_PWM_POLARITY			(1 << 29)
022e4e52a750066 Sunil Kamath                  2015-09-30   4949  #define _BXT_BLC_PWM_FREQ1			0xC8254
022e4e52a750066 Sunil Kamath                  2015-09-30   4950  #define _BXT_BLC_PWM_DUTY1			0xC8258
022e4e52a750066 Sunil Kamath                  2015-09-30   4951  
022e4e52a750066 Sunil Kamath                  2015-09-30   4952  #define _BXT_BLC_PWM_CTL2			0xC8350
022e4e52a750066 Sunil Kamath                  2015-09-30   4953  #define _BXT_BLC_PWM_FREQ2			0xC8354
022e4e52a750066 Sunil Kamath                  2015-09-30   4954  #define _BXT_BLC_PWM_DUTY2			0xC8358
022e4e52a750066 Sunil Kamath                  2015-09-30   4955  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4956  #define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
022e4e52a750066 Sunil Kamath                  2015-09-30   4957  					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4958  #define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
022e4e52a750066 Sunil Kamath                  2015-09-30   4959  					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4960  #define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
022e4e52a750066 Sunil Kamath                  2015-09-30   4961  					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
0fb890c01349c52 Vandana Kannan                2015-05-05   4962  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4963  #define PCH_GTC_CTL		_MMIO(0xe7000)
be256dc70284c02 Paulo Zanoni                  2013-07-23   4964  #define   PCH_GTC_ENABLE	(1 << 31)
be256dc70284c02 Paulo Zanoni                  2013-07-23   4965  
585fb111348f7cd Jesse Barnes                  2008-07-29   4966  /* TV port control */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   4967  #define TV_CTL			_MMIO(0x68000)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4968  /* Enables the TV encoder */
585fb111348f7cd Jesse Barnes                  2008-07-29   4969  # define TV_ENC_ENABLE			(1 << 31)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4970  /* Sources the TV encoder input from pipe B instead of A. */
4add0f6bde05066 Ville Syrjälä                 2018-05-14   4971  # define TV_ENC_PIPE_SEL_SHIFT		30
4add0f6bde05066 Ville Syrjälä                 2018-05-14   4972  # define TV_ENC_PIPE_SEL_MASK		(1 << 30)
4add0f6bde05066 Ville Syrjälä                 2018-05-14   4973  # define TV_ENC_PIPE_SEL(pipe)		((pipe) << 30)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4974  /* Outputs composite video (DAC A only) */
585fb111348f7cd Jesse Barnes                  2008-07-29   4975  # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4976  /* Outputs SVideo video (DAC B/C) */
585fb111348f7cd Jesse Barnes                  2008-07-29   4977  # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4978  /* Outputs Component video (DAC A/B/C) */
585fb111348f7cd Jesse Barnes                  2008-07-29   4979  # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4980  /* Outputs Composite and SVideo (DAC A/B/C) */
585fb111348f7cd Jesse Barnes                  2008-07-29   4981  # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   4982  # define TV_TRILEVEL_SYNC		(1 << 21)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4983  /* Enables slow sync generation (945GM only) */
585fb111348f7cd Jesse Barnes                  2008-07-29   4984  # define TV_SLOW_SYNC			(1 << 20)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4985  /* Selects 4x oversampling for 480i and 576p */
585fb111348f7cd Jesse Barnes                  2008-07-29   4986  # define TV_OVERSAMPLE_4X		(0 << 18)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4987  /* Selects 2x oversampling for 720p and 1080i */
585fb111348f7cd Jesse Barnes                  2008-07-29   4988  # define TV_OVERSAMPLE_2X		(1 << 18)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4989  /* Selects no oversampling for 1080p */
585fb111348f7cd Jesse Barnes                  2008-07-29   4990  # define TV_OVERSAMPLE_NONE		(2 << 18)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4991  /* Selects 8x oversampling */
585fb111348f7cd Jesse Barnes                  2008-07-29   4992  # define TV_OVERSAMPLE_8X		(3 << 18)
e3bb355c7d8b2e5 Ville Syrjälä                 2018-11-12   4993  # define TV_OVERSAMPLE_MASK		(3 << 18)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4994  /* Selects progressive mode rather than interlaced */
585fb111348f7cd Jesse Barnes                  2008-07-29   4995  # define TV_PROGRESSIVE			(1 << 17)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4996  /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
585fb111348f7cd Jesse Barnes                  2008-07-29   4997  # define TV_PAL_BURST			(1 << 16)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   4998  /* Field for setting delay of Y compared to C */
585fb111348f7cd Jesse Barnes                  2008-07-29   4999  # define TV_YC_SKEW_MASK		(7 << 12)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5000  /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
585fb111348f7cd Jesse Barnes                  2008-07-29   5001  # define TV_ENC_SDP_FIX			(1 << 11)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5002  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5003   * Enables a fix for the 915GM only.
585fb111348f7cd Jesse Barnes                  2008-07-29   5004   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5005   * Not sure what it does.
585fb111348f7cd Jesse Barnes                  2008-07-29   5006   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5007  # define TV_ENC_C0_FIX			(1 << 10)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5008  /* Bits that must be preserved by software */
d2d9f23240a7ec2 Zhenyu Wang                   2009-03-04   5009  # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
585fb111348f7cd Jesse Barnes                  2008-07-29   5010  # define TV_FUSE_STATE_MASK		(3 << 4)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5011  /* Read-only state that reports all features enabled */
585fb111348f7cd Jesse Barnes                  2008-07-29   5012  # define TV_FUSE_STATE_ENABLED		(0 << 4)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5013  /* Read-only state that reports that Macrovision is disabled in hardware*/
585fb111348f7cd Jesse Barnes                  2008-07-29   5014  # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5015  /* Read-only state that reports that TV-out is disabled in hardware. */
585fb111348f7cd Jesse Barnes                  2008-07-29   5016  # define TV_FUSE_STATE_DISABLED		(2 << 4)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5017  /* Normal operation */
585fb111348f7cd Jesse Barnes                  2008-07-29   5018  # define TV_TEST_MODE_NORMAL		(0 << 0)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5019  /* Encoder test pattern 1 - combo pattern */
585fb111348f7cd Jesse Barnes                  2008-07-29   5020  # define TV_TEST_MODE_PATTERN_1		(1 << 0)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5021  /* Encoder test pattern 2 - full screen vertical 75% color bars */
585fb111348f7cd Jesse Barnes                  2008-07-29   5022  # define TV_TEST_MODE_PATTERN_2		(2 << 0)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5023  /* Encoder test pattern 3 - full screen horizontal 75% color bars */
585fb111348f7cd Jesse Barnes                  2008-07-29   5024  # define TV_TEST_MODE_PATTERN_3		(3 << 0)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5025  /* Encoder test pattern 4 - random noise */
585fb111348f7cd Jesse Barnes                  2008-07-29   5026  # define TV_TEST_MODE_PATTERN_4		(4 << 0)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5027  /* Encoder test pattern 5 - linear color ramps */
585fb111348f7cd Jesse Barnes                  2008-07-29   5028  # define TV_TEST_MODE_PATTERN_5		(5 << 0)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5029  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5030   * This test mode forces the DACs to 50% of full output.
585fb111348f7cd Jesse Barnes                  2008-07-29   5031   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5032   * This is used for load detection in combination with TVDAC_SENSE_MASK
585fb111348f7cd Jesse Barnes                  2008-07-29   5033   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5034  # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   5035  # define TV_TEST_MODE_MASK		(7 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   5036  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5037  #define TV_DAC			_MMIO(0x68004)
b8ed2a4f12870bf Chris Wilson                  2010-09-05   5038  # define TV_DAC_SAVE		0x00ffff00
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5039  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5040   * Reports that DAC state change logic has reported change (RO).
585fb111348f7cd Jesse Barnes                  2008-07-29   5041   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5042   * This gets cleared when TV_DAC_STATE_EN is cleared
585fb111348f7cd Jesse Barnes                  2008-07-29   5043  */
585fb111348f7cd Jesse Barnes                  2008-07-29   5044  # define TVDAC_STATE_CHG		(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   5045  # define TVDAC_SENSE_MASK		(7 << 28)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5046  /* Reports that DAC A voltage is above the detect threshold */
585fb111348f7cd Jesse Barnes                  2008-07-29   5047  # define TVDAC_A_SENSE			(1 << 30)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5048  /* Reports that DAC B voltage is above the detect threshold */
585fb111348f7cd Jesse Barnes                  2008-07-29   5049  # define TVDAC_B_SENSE			(1 << 29)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5050  /* Reports that DAC C voltage is above the detect threshold */
585fb111348f7cd Jesse Barnes                  2008-07-29   5051  # define TVDAC_C_SENSE			(1 << 28)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5052  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5053   * Enables DAC state detection logic, for load-based TV detection.
585fb111348f7cd Jesse Barnes                  2008-07-29   5054   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5055   * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
585fb111348f7cd Jesse Barnes                  2008-07-29   5056   * to off, for load detection to work.
585fb111348f7cd Jesse Barnes                  2008-07-29   5057   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5058  # define TVDAC_STATE_CHG_EN		(1 << 27)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5059  /* Sets the DAC A sense value to high */
585fb111348f7cd Jesse Barnes                  2008-07-29   5060  # define TVDAC_A_SENSE_CTL		(1 << 26)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5061  /* Sets the DAC B sense value to high */
585fb111348f7cd Jesse Barnes                  2008-07-29   5062  # define TVDAC_B_SENSE_CTL		(1 << 25)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5063  /* Sets the DAC C sense value to high */
585fb111348f7cd Jesse Barnes                  2008-07-29   5064  # define TVDAC_C_SENSE_CTL		(1 << 24)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5065  /* Overrides the ENC_ENABLE and DAC voltage levels */
585fb111348f7cd Jesse Barnes                  2008-07-29   5066  # define DAC_CTL_OVERRIDE		(1 << 7)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5067  /* Sets the slew rate.  Must be preserved in software */
585fb111348f7cd Jesse Barnes                  2008-07-29   5068  # define ENC_TVDAC_SLEW_FAST		(1 << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   5069  # define DAC_A_1_3_V			(0 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   5070  # define DAC_A_1_1_V			(1 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   5071  # define DAC_A_0_7_V			(2 << 4)
cb66c692d1ae257 Ma Ling                       2009-05-31   5072  # define DAC_A_MASK			(3 << 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   5073  # define DAC_B_1_3_V			(0 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   5074  # define DAC_B_1_1_V			(1 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   5075  # define DAC_B_0_7_V			(2 << 2)
cb66c692d1ae257 Ma Ling                       2009-05-31   5076  # define DAC_B_MASK			(3 << 2)
585fb111348f7cd Jesse Barnes                  2008-07-29   5077  # define DAC_C_1_3_V			(0 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   5078  # define DAC_C_1_1_V			(1 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   5079  # define DAC_C_0_7_V			(2 << 0)
cb66c692d1ae257 Ma Ling                       2009-05-31   5080  # define DAC_C_MASK			(3 << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   5081  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5082  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5083   * CSC coefficients are stored in a floating point format with 9 bits of
585fb111348f7cd Jesse Barnes                  2008-07-29   5084   * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
585fb111348f7cd Jesse Barnes                  2008-07-29   5085   * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
585fb111348f7cd Jesse Barnes                  2008-07-29   5086   * -1 (0x3) being the only legal negative value.
585fb111348f7cd Jesse Barnes                  2008-07-29   5087   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5088  #define TV_CSC_Y		_MMIO(0x68010)
585fb111348f7cd Jesse Barnes                  2008-07-29   5089  # define TV_RY_MASK			0x07ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5090  # define TV_RY_SHIFT			16
585fb111348f7cd Jesse Barnes                  2008-07-29   5091  # define TV_GY_MASK			0x00000fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5092  # define TV_GY_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5093  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5094  #define TV_CSC_Y2		_MMIO(0x68014)
585fb111348f7cd Jesse Barnes                  2008-07-29   5095  # define TV_BY_MASK			0x07ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5096  # define TV_BY_SHIFT			16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5097  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5098   * Y attenuation for component video.
585fb111348f7cd Jesse Barnes                  2008-07-29   5099   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5100   * Stored in 1.9 fixed point.
585fb111348f7cd Jesse Barnes                  2008-07-29   5101   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5102  # define TV_AY_MASK			0x000003ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5103  # define TV_AY_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5104  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5105  #define TV_CSC_U		_MMIO(0x68018)
585fb111348f7cd Jesse Barnes                  2008-07-29   5106  # define TV_RU_MASK			0x07ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5107  # define TV_RU_SHIFT			16
585fb111348f7cd Jesse Barnes                  2008-07-29   5108  # define TV_GU_MASK			0x000007ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5109  # define TV_GU_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5110  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5111  #define TV_CSC_U2		_MMIO(0x6801c)
585fb111348f7cd Jesse Barnes                  2008-07-29   5112  # define TV_BU_MASK			0x07ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5113  # define TV_BU_SHIFT			16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5114  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5115   * U attenuation for component video.
585fb111348f7cd Jesse Barnes                  2008-07-29   5116   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5117   * Stored in 1.9 fixed point.
585fb111348f7cd Jesse Barnes                  2008-07-29   5118   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5119  # define TV_AU_MASK			0x000003ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5120  # define TV_AU_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5121  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5122  #define TV_CSC_V		_MMIO(0x68020)
585fb111348f7cd Jesse Barnes                  2008-07-29   5123  # define TV_RV_MASK			0x0fff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5124  # define TV_RV_SHIFT			16
585fb111348f7cd Jesse Barnes                  2008-07-29   5125  # define TV_GV_MASK			0x000007ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5126  # define TV_GV_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5127  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5128  #define TV_CSC_V2		_MMIO(0x68024)
585fb111348f7cd Jesse Barnes                  2008-07-29   5129  # define TV_BV_MASK			0x07ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5130  # define TV_BV_SHIFT			16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5131  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5132   * V attenuation for component video.
585fb111348f7cd Jesse Barnes                  2008-07-29   5133   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5134   * Stored in 1.9 fixed point.
585fb111348f7cd Jesse Barnes                  2008-07-29   5135   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5136  # define TV_AV_MASK			0x000007ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5137  # define TV_AV_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5138  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5139  #define TV_CLR_KNOBS		_MMIO(0x68028)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5140  /* 2s-complement brightness adjustment */
585fb111348f7cd Jesse Barnes                  2008-07-29   5141  # define TV_BRIGHTNESS_MASK		0xff000000
585fb111348f7cd Jesse Barnes                  2008-07-29   5142  # define TV_BRIGHTNESS_SHIFT		24
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5143  /* Contrast adjustment, as a 2.6 unsigned floating point number */
585fb111348f7cd Jesse Barnes                  2008-07-29   5144  # define TV_CONTRAST_MASK		0x00ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5145  # define TV_CONTRAST_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5146  /* Saturation adjustment, as a 2.6 unsigned floating point number */
585fb111348f7cd Jesse Barnes                  2008-07-29   5147  # define TV_SATURATION_MASK		0x0000ff00
585fb111348f7cd Jesse Barnes                  2008-07-29   5148  # define TV_SATURATION_SHIFT		8
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5149  /* Hue adjustment, as an integer phase angle in degrees */
585fb111348f7cd Jesse Barnes                  2008-07-29   5150  # define TV_HUE_MASK			0x000000ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5151  # define TV_HUE_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5152  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5153  #define TV_CLR_LEVEL		_MMIO(0x6802c)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5154  /* Controls the DAC level for black */
585fb111348f7cd Jesse Barnes                  2008-07-29   5155  # define TV_BLACK_LEVEL_MASK		0x01ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5156  # define TV_BLACK_LEVEL_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5157  /* Controls the DAC level for blanking */
585fb111348f7cd Jesse Barnes                  2008-07-29   5158  # define TV_BLANK_LEVEL_MASK		0x000001ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5159  # define TV_BLANK_LEVEL_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5160  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5161  #define TV_H_CTL_1		_MMIO(0x68030)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5162  /* Number of pixels in the hsync. */
585fb111348f7cd Jesse Barnes                  2008-07-29   5163  # define TV_HSYNC_END_MASK		0x1fff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5164  # define TV_HSYNC_END_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5165  /* Total number of pixels minus one in the line (display and blanking). */
585fb111348f7cd Jesse Barnes                  2008-07-29   5166  # define TV_HTOTAL_MASK			0x00001fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5167  # define TV_HTOTAL_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5168  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5169  #define TV_H_CTL_2		_MMIO(0x68034)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5170  /* Enables the colorburst (needed for non-component color) */
585fb111348f7cd Jesse Barnes                  2008-07-29   5171  # define TV_BURST_ENA			(1 << 31)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5172  /* Offset of the colorburst from the start of hsync, in pixels minus one. */
585fb111348f7cd Jesse Barnes                  2008-07-29   5173  # define TV_HBURST_START_SHIFT		16
585fb111348f7cd Jesse Barnes                  2008-07-29   5174  # define TV_HBURST_START_MASK		0x1fff0000
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5175  /* Length of the colorburst */
585fb111348f7cd Jesse Barnes                  2008-07-29   5176  # define TV_HBURST_LEN_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5177  # define TV_HBURST_LEN_MASK		0x0001fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5178  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5179  #define TV_H_CTL_3		_MMIO(0x68038)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5180  /* End of hblank, measured in pixels minus one from start of hsync */
585fb111348f7cd Jesse Barnes                  2008-07-29   5181  # define TV_HBLANK_END_SHIFT		16
585fb111348f7cd Jesse Barnes                  2008-07-29   5182  # define TV_HBLANK_END_MASK		0x1fff0000
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5183  /* Start of hblank, measured in pixels minus one from start of hsync */
585fb111348f7cd Jesse Barnes                  2008-07-29   5184  # define TV_HBLANK_START_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5185  # define TV_HBLANK_START_MASK		0x0001fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5186  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5187  #define TV_V_CTL_1		_MMIO(0x6803c)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5188  /* XXX */
585fb111348f7cd Jesse Barnes                  2008-07-29   5189  # define TV_NBR_END_SHIFT		16
585fb111348f7cd Jesse Barnes                  2008-07-29   5190  # define TV_NBR_END_MASK		0x07ff0000
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5191  /* XXX */
585fb111348f7cd Jesse Barnes                  2008-07-29   5192  # define TV_VI_END_F1_SHIFT		8
585fb111348f7cd Jesse Barnes                  2008-07-29   5193  # define TV_VI_END_F1_MASK		0x00003f00
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5194  /* XXX */
585fb111348f7cd Jesse Barnes                  2008-07-29   5195  # define TV_VI_END_F2_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5196  # define TV_VI_END_F2_MASK		0x0000003f
585fb111348f7cd Jesse Barnes                  2008-07-29   5197  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5198  #define TV_V_CTL_2		_MMIO(0x68040)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5199  /* Length of vsync, in half lines */
585fb111348f7cd Jesse Barnes                  2008-07-29   5200  # define TV_VSYNC_LEN_MASK		0x07ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5201  # define TV_VSYNC_LEN_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5202  /* Offset of the start of vsync in field 1, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5203   * number of half lines.
585fb111348f7cd Jesse Barnes                  2008-07-29   5204   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5205  # define TV_VSYNC_START_F1_MASK		0x00007f00
585fb111348f7cd Jesse Barnes                  2008-07-29   5206  # define TV_VSYNC_START_F1_SHIFT	8
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5207  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5208   * Offset of the start of vsync in field 2, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5209   * number of half lines.
585fb111348f7cd Jesse Barnes                  2008-07-29   5210   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5211  # define TV_VSYNC_START_F2_MASK		0x0000007f
585fb111348f7cd Jesse Barnes                  2008-07-29   5212  # define TV_VSYNC_START_F2_SHIFT	0
585fb111348f7cd Jesse Barnes                  2008-07-29   5213  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5214  #define TV_V_CTL_3		_MMIO(0x68044)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5215  /* Enables generation of the equalization signal */
585fb111348f7cd Jesse Barnes                  2008-07-29   5216  # define TV_EQUAL_ENA			(1 << 31)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5217  /* Length of vsync, in half lines */
585fb111348f7cd Jesse Barnes                  2008-07-29   5218  # define TV_VEQ_LEN_MASK		0x007f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5219  # define TV_VEQ_LEN_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5220  /* Offset of the start of equalization in field 1, measured in one less than
585fb111348f7cd Jesse Barnes                  2008-07-29   5221   * the number of half lines.
585fb111348f7cd Jesse Barnes                  2008-07-29   5222   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5223  # define TV_VEQ_START_F1_MASK		0x0007f00
585fb111348f7cd Jesse Barnes                  2008-07-29   5224  # define TV_VEQ_START_F1_SHIFT		8
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5225  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5226   * Offset of the start of equalization in field 2, measured in one less than
585fb111348f7cd Jesse Barnes                  2008-07-29   5227   * the number of half lines.
585fb111348f7cd Jesse Barnes                  2008-07-29   5228   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5229  # define TV_VEQ_START_F2_MASK		0x000007f
585fb111348f7cd Jesse Barnes                  2008-07-29   5230  # define TV_VEQ_START_F2_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5231  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5232  #define TV_V_CTL_4		_MMIO(0x68048)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5233  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5234   * Offset to start of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5235   * number of lines from vertical start.
585fb111348f7cd Jesse Barnes                  2008-07-29   5236   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5237  # define TV_VBURST_START_F1_MASK	0x003f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5238  # define TV_VBURST_START_F1_SHIFT	16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5239  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5240   * Offset to the end of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5241   * number of lines from the start of NBR.
585fb111348f7cd Jesse Barnes                  2008-07-29   5242   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5243  # define TV_VBURST_END_F1_MASK		0x000000ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5244  # define TV_VBURST_END_F1_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5245  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5246  #define TV_V_CTL_5		_MMIO(0x6804c)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5247  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5248   * Offset to start of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5249   * number of lines from vertical start.
585fb111348f7cd Jesse Barnes                  2008-07-29   5250   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5251  # define TV_VBURST_START_F2_MASK	0x003f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5252  # define TV_VBURST_START_F2_SHIFT	16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5253  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5254   * Offset to the end of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5255   * number of lines from the start of NBR.
585fb111348f7cd Jesse Barnes                  2008-07-29   5256   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5257  # define TV_VBURST_END_F2_MASK		0x000000ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5258  # define TV_VBURST_END_F2_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5259  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5260  #define TV_V_CTL_6		_MMIO(0x68050)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5261  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5262   * Offset to start of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5263   * number of lines from vertical start.
585fb111348f7cd Jesse Barnes                  2008-07-29   5264   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5265  # define TV_VBURST_START_F3_MASK	0x003f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5266  # define TV_VBURST_START_F3_SHIFT	16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5267  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5268   * Offset to the end of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5269   * number of lines from the start of NBR.
585fb111348f7cd Jesse Barnes                  2008-07-29   5270   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5271  # define TV_VBURST_END_F3_MASK		0x000000ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5272  # define TV_VBURST_END_F3_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5273  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5274  #define TV_V_CTL_7		_MMIO(0x68054)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5275  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5276   * Offset to start of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5277   * number of lines from vertical start.
585fb111348f7cd Jesse Barnes                  2008-07-29   5278   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5279  # define TV_VBURST_START_F4_MASK	0x003f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5280  # define TV_VBURST_START_F4_SHIFT	16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5281  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5282   * Offset to the end of vertical colorburst, measured in one less than the
585fb111348f7cd Jesse Barnes                  2008-07-29   5283   * number of lines from the start of NBR.
585fb111348f7cd Jesse Barnes                  2008-07-29   5284   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5285  # define TV_VBURST_END_F4_MASK		0x000000ff
585fb111348f7cd Jesse Barnes                  2008-07-29   5286  # define TV_VBURST_END_F4_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5287  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5288  #define TV_SC_CTL_1		_MMIO(0x68060)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5289  /* Turns on the first subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5290  # define TV_SC_DDA1_EN			(1 << 31)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5291  /* Turns on the first subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5292  # define TV_SC_DDA2_EN			(1 << 30)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5293  /* Turns on the first subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5294  # define TV_SC_DDA3_EN			(1 << 29)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5295  /* Sets the subcarrier DDA to reset frequency every other field */
585fb111348f7cd Jesse Barnes                  2008-07-29   5296  # define TV_SC_RESET_EVERY_2		(0 << 24)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5297  /* Sets the subcarrier DDA to reset frequency every fourth field */
585fb111348f7cd Jesse Barnes                  2008-07-29   5298  # define TV_SC_RESET_EVERY_4		(1 << 24)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5299  /* Sets the subcarrier DDA to reset frequency every eighth field */
585fb111348f7cd Jesse Barnes                  2008-07-29   5300  # define TV_SC_RESET_EVERY_8		(2 << 24)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5301  /* Sets the subcarrier DDA to never reset the frequency */
585fb111348f7cd Jesse Barnes                  2008-07-29   5302  # define TV_SC_RESET_NEVER		(3 << 24)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5303  /* Sets the peak amplitude of the colorburst.*/
585fb111348f7cd Jesse Barnes                  2008-07-29   5304  # define TV_BURST_LEVEL_MASK		0x00ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5305  # define TV_BURST_LEVEL_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5306  /* Sets the increment of the first subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5307  # define TV_SCDDA1_INC_MASK		0x00000fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5308  # define TV_SCDDA1_INC_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5309  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5310  #define TV_SC_CTL_2		_MMIO(0x68064)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5311  /* Sets the rollover for the second subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5312  # define TV_SCDDA2_SIZE_MASK		0x7fff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5313  # define TV_SCDDA2_SIZE_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5314  /* Sets the increent of the second subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5315  # define TV_SCDDA2_INC_MASK		0x00007fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5316  # define TV_SCDDA2_INC_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5317  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5318  #define TV_SC_CTL_3		_MMIO(0x68068)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5319  /* Sets the rollover for the third subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5320  # define TV_SCDDA3_SIZE_MASK		0x7fff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5321  # define TV_SCDDA3_SIZE_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5322  /* Sets the increent of the third subcarrier phase generation DDA */
585fb111348f7cd Jesse Barnes                  2008-07-29   5323  # define TV_SCDDA3_INC_MASK		0x00007fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5324  # define TV_SCDDA3_INC_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5325  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5326  #define TV_WIN_POS		_MMIO(0x68070)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5327  /* X coordinate of the display from the start of horizontal active */
585fb111348f7cd Jesse Barnes                  2008-07-29   5328  # define TV_XPOS_MASK			0x1fff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5329  # define TV_XPOS_SHIFT			16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5330  /* Y coordinate of the display from the start of vertical active (NBR) */
585fb111348f7cd Jesse Barnes                  2008-07-29   5331  # define TV_YPOS_MASK			0x00000fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5332  # define TV_YPOS_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5333  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5334  #define TV_WIN_SIZE		_MMIO(0x68074)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5335  /* Horizontal size of the display window, measured in pixels*/
585fb111348f7cd Jesse Barnes                  2008-07-29   5336  # define TV_XSIZE_MASK			0x1fff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5337  # define TV_XSIZE_SHIFT			16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5338  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5339   * Vertical size of the display window, measured in pixels.
585fb111348f7cd Jesse Barnes                  2008-07-29   5340   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5341   * Must be even for interlaced modes.
585fb111348f7cd Jesse Barnes                  2008-07-29   5342   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5343  # define TV_YSIZE_MASK			0x00000fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5344  # define TV_YSIZE_SHIFT			0
585fb111348f7cd Jesse Barnes                  2008-07-29   5345  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5346  #define TV_FILTER_CTL_1		_MMIO(0x68080)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5347  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5348   * Enables automatic scaling calculation.
585fb111348f7cd Jesse Barnes                  2008-07-29   5349   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5350   * If set, the rest of the registers are ignored, and the calculated values can
585fb111348f7cd Jesse Barnes                  2008-07-29   5351   * be read back from the register.
585fb111348f7cd Jesse Barnes                  2008-07-29   5352   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5353  # define TV_AUTO_SCALE			(1 << 31)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5354  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5355   * Disables the vertical filter.
585fb111348f7cd Jesse Barnes                  2008-07-29   5356   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5357   * This is required on modes more than 1024 pixels wide */
585fb111348f7cd Jesse Barnes                  2008-07-29   5358  # define TV_V_FILTER_BYPASS		(1 << 29)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5359  /* Enables adaptive vertical filtering */
585fb111348f7cd Jesse Barnes                  2008-07-29   5360  # define TV_VADAPT			(1 << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   5361  # define TV_VADAPT_MODE_MASK		(3 << 26)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5362  /* Selects the least adaptive vertical filtering mode */
585fb111348f7cd Jesse Barnes                  2008-07-29   5363  # define TV_VADAPT_MODE_LEAST		(0 << 26)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5364  /* Selects the moderately adaptive vertical filtering mode */
585fb111348f7cd Jesse Barnes                  2008-07-29   5365  # define TV_VADAPT_MODE_MODERATE	(1 << 26)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5366  /* Selects the most adaptive vertical filtering mode */
585fb111348f7cd Jesse Barnes                  2008-07-29   5367  # define TV_VADAPT_MODE_MOST		(3 << 26)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5368  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5369   * Sets the horizontal scaling factor.
585fb111348f7cd Jesse Barnes                  2008-07-29   5370   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5371   * This should be the fractional part of the horizontal scaling factor divided
585fb111348f7cd Jesse Barnes                  2008-07-29   5372   * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
585fb111348f7cd Jesse Barnes                  2008-07-29   5373   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5374   * (src width - 1) / ((oversample * dest width) - 1)
585fb111348f7cd Jesse Barnes                  2008-07-29   5375   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5376  # define TV_HSCALE_FRAC_MASK		0x00003fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5377  # define TV_HSCALE_FRAC_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5378  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5379  #define TV_FILTER_CTL_2		_MMIO(0x68084)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5380  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5381   * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
585fb111348f7cd Jesse Barnes                  2008-07-29   5382   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5383   * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
585fb111348f7cd Jesse Barnes                  2008-07-29   5384   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5385  # define TV_VSCALE_INT_MASK		0x00038000
585fb111348f7cd Jesse Barnes                  2008-07-29   5386  # define TV_VSCALE_INT_SHIFT		15
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5387  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5388   * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
585fb111348f7cd Jesse Barnes                  2008-07-29   5389   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5390   * \sa TV_VSCALE_INT_MASK
585fb111348f7cd Jesse Barnes                  2008-07-29   5391   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5392  # define TV_VSCALE_FRAC_MASK		0x00007fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5393  # define TV_VSCALE_FRAC_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5394  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5395  #define TV_FILTER_CTL_3		_MMIO(0x68088)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5396  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5397   * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
585fb111348f7cd Jesse Barnes                  2008-07-29   5398   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5399   * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
585fb111348f7cd Jesse Barnes                  2008-07-29   5400   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5401   * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
585fb111348f7cd Jesse Barnes                  2008-07-29   5402   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5403  # define TV_VSCALE_IP_INT_MASK		0x00038000
585fb111348f7cd Jesse Barnes                  2008-07-29   5404  # define TV_VSCALE_IP_INT_SHIFT		15
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5405  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5406   * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
585fb111348f7cd Jesse Barnes                  2008-07-29   5407   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5408   * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
585fb111348f7cd Jesse Barnes                  2008-07-29   5409   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5410   * \sa TV_VSCALE_IP_INT_MASK
585fb111348f7cd Jesse Barnes                  2008-07-29   5411   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5412  # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
585fb111348f7cd Jesse Barnes                  2008-07-29   5413  # define TV_VSCALE_IP_FRAC_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5414  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5415  #define TV_CC_CONTROL		_MMIO(0x68090)
585fb111348f7cd Jesse Barnes                  2008-07-29   5416  # define TV_CC_ENABLE			(1 << 31)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5417  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   5418   * Specifies which field to send the CC data in.
585fb111348f7cd Jesse Barnes                  2008-07-29   5419   *
585fb111348f7cd Jesse Barnes                  2008-07-29   5420   * CC data is usually sent in field 0.
585fb111348f7cd Jesse Barnes                  2008-07-29   5421   */
585fb111348f7cd Jesse Barnes                  2008-07-29   5422  # define TV_CC_FID_MASK			(1 << 27)
585fb111348f7cd Jesse Barnes                  2008-07-29   5423  # define TV_CC_FID_SHIFT		27
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5424  /* Sets the horizontal position of the CC data.  Usually 135. */
585fb111348f7cd Jesse Barnes                  2008-07-29   5425  # define TV_CC_HOFF_MASK		0x03ff0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5426  # define TV_CC_HOFF_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5427  /* Sets the vertical position of the CC data.  Usually 21 */
585fb111348f7cd Jesse Barnes                  2008-07-29   5428  # define TV_CC_LINE_MASK		0x0000003f
585fb111348f7cd Jesse Barnes                  2008-07-29   5429  # define TV_CC_LINE_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5430  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5431  #define TV_CC_DATA		_MMIO(0x68094)
585fb111348f7cd Jesse Barnes                  2008-07-29   5432  # define TV_CC_RDY			(1 << 31)
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5433  /* Second word of CC data to be transmitted. */
585fb111348f7cd Jesse Barnes                  2008-07-29   5434  # define TV_CC_DATA_2_MASK		0x007f0000
585fb111348f7cd Jesse Barnes                  2008-07-29   5435  # define TV_CC_DATA_2_SHIFT		16
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5436  /* First word of CC data to be transmitted. */
585fb111348f7cd Jesse Barnes                  2008-07-29   5437  # define TV_CC_DATA_1_MASK		0x0000007f
585fb111348f7cd Jesse Barnes                  2008-07-29   5438  # define TV_CC_DATA_1_SHIFT		0
585fb111348f7cd Jesse Barnes                  2008-07-29   5439  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5440  #define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5441  #define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5442  #define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5443  #define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
585fb111348f7cd Jesse Barnes                  2008-07-29   5444  
040d87f15a01292 Keith Packard                 2009-05-30   5445  /* Display Port */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5446  #define DP_A			_MMIO(0x64000) /* eDP */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5447  #define DP_B			_MMIO(0x64100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5448  #define DP_C			_MMIO(0x64200)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5449  #define DP_D			_MMIO(0x64300)
040d87f15a01292 Keith Packard                 2009-05-30   5450  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5451  #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5452  #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5453  #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
e66eb81de2ff822 Ville Syrjälä                 2015-09-18   5454  
040d87f15a01292 Keith Packard                 2009-05-30   5455  #define   DP_PORT_EN			(1 << 31)
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5456  #define   DP_PIPE_SEL_SHIFT		30
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5457  #define   DP_PIPE_SEL_MASK		(1 << 30)
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5458  #define   DP_PIPE_SEL(pipe)		((pipe) << 30)
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5459  #define   DP_PIPE_SEL_SHIFT_IVB		29
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5460  #define   DP_PIPE_SEL_MASK_IVB		(3 << 29)
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5461  #define   DP_PIPE_SEL_IVB(pipe)		((pipe) << 29)
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5462  #define   DP_PIPE_SEL_SHIFT_CHV		16
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5463  #define   DP_PIPE_SEL_MASK_CHV		(3 << 16)
59b74c497ae4e9d Ville Syrjälä                 2018-05-18   5464  #define   DP_PIPE_SEL_CHV(pipe)		((pipe) << 16)
47a05eca7299103 Jesse Barnes                  2011-02-07   5465  
040d87f15a01292 Keith Packard                 2009-05-30   5466  /* Link training mode - select a suitable mode for each stage */
040d87f15a01292 Keith Packard                 2009-05-30   5467  #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
040d87f15a01292 Keith Packard                 2009-05-30   5468  #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
040d87f15a01292 Keith Packard                 2009-05-30   5469  #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
040d87f15a01292 Keith Packard                 2009-05-30   5470  #define   DP_LINK_TRAIN_OFF		(3 << 28)
040d87f15a01292 Keith Packard                 2009-05-30   5471  #define   DP_LINK_TRAIN_MASK		(3 << 28)
040d87f15a01292 Keith Packard                 2009-05-30   5472  #define   DP_LINK_TRAIN_SHIFT		28
040d87f15a01292 Keith Packard                 2009-05-30   5473  
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5474  /* CPT Link training mode */
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5475  #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5476  #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5477  #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5478  #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5479  #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5480  #define   DP_LINK_TRAIN_SHIFT_CPT	8
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   5481  
040d87f15a01292 Keith Packard                 2009-05-30   5482  /* Signal voltages. These are mostly controlled by the other end */
040d87f15a01292 Keith Packard                 2009-05-30   5483  #define   DP_VOLTAGE_0_4		(0 << 25)
040d87f15a01292 Keith Packard                 2009-05-30   5484  #define   DP_VOLTAGE_0_6		(1 << 25)
040d87f15a01292 Keith Packard                 2009-05-30   5485  #define   DP_VOLTAGE_0_8		(2 << 25)
040d87f15a01292 Keith Packard                 2009-05-30   5486  #define   DP_VOLTAGE_1_2		(3 << 25)
040d87f15a01292 Keith Packard                 2009-05-30   5487  #define   DP_VOLTAGE_MASK		(7 << 25)
040d87f15a01292 Keith Packard                 2009-05-30   5488  #define   DP_VOLTAGE_SHIFT		25
040d87f15a01292 Keith Packard                 2009-05-30   5489  
040d87f15a01292 Keith Packard                 2009-05-30   5490  /* Signal pre-emphasis levels, like voltages, the other end tells us what
040d87f15a01292 Keith Packard                 2009-05-30   5491   * they want
040d87f15a01292 Keith Packard                 2009-05-30   5492   */
040d87f15a01292 Keith Packard                 2009-05-30   5493  #define   DP_PRE_EMPHASIS_0		(0 << 22)
040d87f15a01292 Keith Packard                 2009-05-30   5494  #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
040d87f15a01292 Keith Packard                 2009-05-30   5495  #define   DP_PRE_EMPHASIS_6		(2 << 22)
040d87f15a01292 Keith Packard                 2009-05-30   5496  #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
040d87f15a01292 Keith Packard                 2009-05-30   5497  #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
040d87f15a01292 Keith Packard                 2009-05-30   5498  #define   DP_PRE_EMPHASIS_SHIFT		22
040d87f15a01292 Keith Packard                 2009-05-30   5499  
040d87f15a01292 Keith Packard                 2009-05-30   5500  /* How many wires to use. I guess 3 was too hard */
17aa6be9579eb20 Daniel Vetter                 2013-04-30   5501  #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
040d87f15a01292 Keith Packard                 2009-05-30   5502  #define   DP_PORT_WIDTH_MASK		(7 << 19)
90a6b7b052b1aa1 Ville Syrjälä                 2015-07-06   5503  #define   DP_PORT_WIDTH_SHIFT		19
040d87f15a01292 Keith Packard                 2009-05-30   5504  
040d87f15a01292 Keith Packard                 2009-05-30   5505  /* Mystic DPCD version 1.1 special mode */
040d87f15a01292 Keith Packard                 2009-05-30   5506  #define   DP_ENHANCED_FRAMING		(1 << 18)
040d87f15a01292 Keith Packard                 2009-05-30   5507  
32f9d658aee5be0 Zhenyu Wang                   2009-07-24   5508  /* eDP */
32f9d658aee5be0 Zhenyu Wang                   2009-07-24   5509  #define   DP_PLL_FREQ_270MHZ		(0 << 16)
b377e0df1118e63 Ville Syrjälä                 2015-10-29   5510  #define   DP_PLL_FREQ_162MHZ		(1 << 16)
32f9d658aee5be0 Zhenyu Wang                   2009-07-24   5511  #define   DP_PLL_FREQ_MASK		(3 << 16)
32f9d658aee5be0 Zhenyu Wang                   2009-07-24   5512  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5513  /* locked once port is enabled */
040d87f15a01292 Keith Packard                 2009-05-30   5514  #define   DP_PORT_REVERSAL		(1 << 15)
040d87f15a01292 Keith Packard                 2009-05-30   5515  
32f9d658aee5be0 Zhenyu Wang                   2009-07-24   5516  /* eDP */
32f9d658aee5be0 Zhenyu Wang                   2009-07-24   5517  #define   DP_PLL_ENABLE			(1 << 14)
32f9d658aee5be0 Zhenyu Wang                   2009-07-24   5518  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5519  /* sends the clock on lane 15 of the PEG for debug */
040d87f15a01292 Keith Packard                 2009-05-30   5520  #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
040d87f15a01292 Keith Packard                 2009-05-30   5521  
040d87f15a01292 Keith Packard                 2009-05-30   5522  #define   DP_SCRAMBLING_DISABLE		(1 << 12)
f2b115e69d46344 Adam Jackson                  2009-12-03   5523  #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
040d87f15a01292 Keith Packard                 2009-05-30   5524  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5525  /* limit RGB values to avoid confusing TVs */
040d87f15a01292 Keith Packard                 2009-05-30   5526  #define   DP_COLOR_RANGE_16_235		(1 << 8)
040d87f15a01292 Keith Packard                 2009-05-30   5527  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5528  /* Turn on the audio link */
040d87f15a01292 Keith Packard                 2009-05-30   5529  #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
040d87f15a01292 Keith Packard                 2009-05-30   5530  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5531  /* vs and hs sync polarity */
040d87f15a01292 Keith Packard                 2009-05-30   5532  #define   DP_SYNC_VS_HIGH		(1 << 4)
040d87f15a01292 Keith Packard                 2009-05-30   5533  #define   DP_SYNC_HS_HIGH		(1 << 3)
040d87f15a01292 Keith Packard                 2009-05-30   5534  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5535  /* A fantasy */
040d87f15a01292 Keith Packard                 2009-05-30   5536  #define   DP_DETECTED			(1 << 2)
040d87f15a01292 Keith Packard                 2009-05-30   5537  
646b4269e4d0513 Ville Syrjälä                 2014-04-25   5538  /* The aux channel provides a way to talk to the
040d87f15a01292 Keith Packard                 2009-05-30   5539   * signal sink for DDC etc. Max packet size supported
040d87f15a01292 Keith Packard                 2009-05-30   5540   * is 20 bytes in each direction, hence the 5 fixed
040d87f15a01292 Keith Packard                 2009-05-30   5541   * data registers
040d87f15a01292 Keith Packard                 2009-05-30   5542   */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5543  #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5544  #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5545  #define _DPA_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64018)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5546  #define _DPA_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6401c)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5547  #define _DPA_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64020)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5548  #define _DPA_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64024)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5549  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5550  #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5551  #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5552  #define _DPB_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64118)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5553  #define _DPB_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6411c)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5554  #define _DPB_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64120)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5555  #define _DPB_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64124)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5556  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5557  #define _DPC_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64210)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5558  #define _DPC_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64214)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5559  #define _DPC_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64218)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5560  #define _DPC_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6421c)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5561  #define _DPC_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64220)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5562  #define _DPC_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64224)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5563  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5564  #define _DPD_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64310)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5565  #define _DPD_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64314)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5566  #define _DPD_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64318)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5567  #define _DPD_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6431c)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5568  #define _DPD_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64320)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5569  #define _DPD_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64324)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5570  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5571  #define _DPE_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64410)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5572  #define _DPE_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64414)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5573  #define _DPE_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64418)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5574  #define _DPE_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6441c)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5575  #define _DPE_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64420)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5576  #define _DPE_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64424)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5577  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5578  #define _DPF_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64510)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5579  #define _DPF_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64514)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5580  #define _DPF_AUX_CH_DATA2	(DISPLAY_MMIO_BASE(dev_priv) + 0x64518)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5581  #define _DPF_AUX_CH_DATA3	(DISPLAY_MMIO_BASE(dev_priv) + 0x6451c)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5582  #define _DPF_AUX_CH_DATA4	(DISPLAY_MMIO_BASE(dev_priv) + 0x64520)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5583  #define _DPF_AUX_CH_DATA5	(DISPLAY_MMIO_BASE(dev_priv) + 0x64524)
a324fcaca314caf Rodrigo Vivi                  2018-01-29   5584  
bdabdb635010a3b Ville Syrjälä                 2018-02-22   5585  #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
bdabdb635010a3b Ville Syrjälä                 2018-02-22   5586  #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
040d87f15a01292 Keith Packard                 2009-05-30   5587  
040d87f15a01292 Keith Packard                 2009-05-30   5588  #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
040d87f15a01292 Keith Packard                 2009-05-30   5589  #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
040d87f15a01292 Keith Packard                 2009-05-30   5590  #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
040d87f15a01292 Keith Packard                 2009-05-30   5591  #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
040d87f15a01292 Keith Packard                 2009-05-30   5592  #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
040d87f15a01292 Keith Packard                 2009-05-30   5593  #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
040d87f15a01292 Keith Packard                 2009-05-30   5594  #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
6fa228ba96f8c35 James Ausmus                  2017-10-12   5595  #define   DP_AUX_CH_CTL_TIME_OUT_MAX	    (3 << 26) /* Varies per platform */
040d87f15a01292 Keith Packard                 2009-05-30   5596  #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
040d87f15a01292 Keith Packard                 2009-05-30   5597  #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
040d87f15a01292 Keith Packard                 2009-05-30   5598  #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
040d87f15a01292 Keith Packard                 2009-05-30   5599  #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
040d87f15a01292 Keith Packard                 2009-05-30   5600  #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
040d87f15a01292 Keith Packard                 2009-05-30   5601  #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
040d87f15a01292 Keith Packard                 2009-05-30   5602  #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
040d87f15a01292 Keith Packard                 2009-05-30   5603  #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
040d87f15a01292 Keith Packard                 2009-05-30   5604  #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
040d87f15a01292 Keith Packard                 2009-05-30   5605  #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
040d87f15a01292 Keith Packard                 2009-05-30   5606  #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
040d87f15a01292 Keith Packard                 2009-05-30   5607  #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
040d87f15a01292 Keith Packard                 2009-05-30   5608  #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
e3d998451090800 Sonika Jindal                 2015-01-22   5609  #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
e3d998451090800 Sonika Jindal                 2015-01-22   5610  #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
e3d998451090800 Sonika Jindal                 2015-01-22   5611  #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
6f211ed4343832c Anusha Srivatsa               2018-07-26   5612  #define   DP_AUX_CH_CTL_TBT_IO			(1 << 11)
395b2913e36ffb6 Ville Syrjälä                 2015-09-18   5613  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
e3d998451090800 Sonika Jindal                 2015-01-22   5614  #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
b9ca5fadb3842a7 Damien Lespiau                2014-01-20   5615  #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
040d87f15a01292 Keith Packard                 2009-05-30   5616  
040d87f15a01292 Keith Packard                 2009-05-30   5617  /*
040d87f15a01292 Keith Packard                 2009-05-30   5618   * Computing GMCH M and N values for the Display Port link
040d87f15a01292 Keith Packard                 2009-05-30   5619   *
040d87f15a01292 Keith Packard                 2009-05-30   5620   * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
040d87f15a01292 Keith Packard                 2009-05-30   5621   *
040d87f15a01292 Keith Packard                 2009-05-30   5622   * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
040d87f15a01292 Keith Packard                 2009-05-30   5623   *
040d87f15a01292 Keith Packard                 2009-05-30   5624   * The GMCH value is used internally
040d87f15a01292 Keith Packard                 2009-05-30   5625   *
040d87f15a01292 Keith Packard                 2009-05-30   5626   * bytes_per_pixel is the number of bytes coming out of the plane,
040d87f15a01292 Keith Packard                 2009-05-30   5627   * which is after the LUTs, so we want the bytes for our color format.
040d87f15a01292 Keith Packard                 2009-05-30   5628   * For our current usage, this is always 3, one byte for R, G and B.
040d87f15a01292 Keith Packard                 2009-05-30   5629   */
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5630  #define _PIPEA_DATA_M_G4X	0x70050
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5631  #define _PIPEB_DATA_M_G4X	0x71050
040d87f15a01292 Keith Packard                 2009-05-30   5632  
040d87f15a01292 Keith Packard                 2009-05-30   5633  /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
a65851af5938714 Ville Syrjälä                 2013-04-23   5634  #define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
72419203cab9acf Daniel Vetter                 2013-04-04   5635  #define  TU_SIZE_SHIFT		25
a65851af5938714 Ville Syrjälä                 2013-04-23   5636  #define  TU_SIZE_MASK           (0x3f << 25)
040d87f15a01292 Keith Packard                 2009-05-30   5637  
a65851af5938714 Ville Syrjälä                 2013-04-23   5638  #define  DATA_LINK_M_N_MASK	(0xffffff)
a65851af5938714 Ville Syrjälä                 2013-04-23   5639  #define  DATA_LINK_N_MAX	(0x800000)
040d87f15a01292 Keith Packard                 2009-05-30   5640  
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5641  #define _PIPEA_DATA_N_G4X	0x70054
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5642  #define _PIPEB_DATA_N_G4X	0x71054
040d87f15a01292 Keith Packard                 2009-05-30   5643  #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
040d87f15a01292 Keith Packard                 2009-05-30   5644  
040d87f15a01292 Keith Packard                 2009-05-30   5645  /*
040d87f15a01292 Keith Packard                 2009-05-30   5646   * Computing Link M and N values for the Display Port link
040d87f15a01292 Keith Packard                 2009-05-30   5647   *
040d87f15a01292 Keith Packard                 2009-05-30   5648   * Link M / N = pixel_clock / ls_clk
040d87f15a01292 Keith Packard                 2009-05-30   5649   *
040d87f15a01292 Keith Packard                 2009-05-30   5650   * (the DP spec calls pixel_clock the 'strm_clk')
040d87f15a01292 Keith Packard                 2009-05-30   5651   *
040d87f15a01292 Keith Packard                 2009-05-30   5652   * The Link value is transmitted in the Main Stream
040d87f15a01292 Keith Packard                 2009-05-30   5653   * Attributes and VB-ID.
040d87f15a01292 Keith Packard                 2009-05-30   5654   */
040d87f15a01292 Keith Packard                 2009-05-30   5655  
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5656  #define _PIPEA_LINK_M_G4X	0x70060
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5657  #define _PIPEB_LINK_M_G4X	0x71060
040d87f15a01292 Keith Packard                 2009-05-30   5658  #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
040d87f15a01292 Keith Packard                 2009-05-30   5659  
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5660  #define _PIPEA_LINK_N_G4X	0x70064
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   5661  #define _PIPEB_LINK_N_G4X	0x71064
040d87f15a01292 Keith Packard                 2009-05-30   5662  #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
040d87f15a01292 Keith Packard                 2009-05-30   5663  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5664  #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5665  #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5666  #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5667  #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   5668  
585fb111348f7cd Jesse Barnes                  2008-07-29   5669  /* Display & cursor control */
585fb111348f7cd Jesse Barnes                  2008-07-29   5670  
585fb111348f7cd Jesse Barnes                  2008-07-29   5671  /* Pipe A */
a57c774ab2b849b Antti Koskipaa                2014-02-04   5672  #define _PIPEADSL		0x70000
837ba00f20aa470 Paulo Zanoni                  2012-05-04   5673  #define   DSL_LINEMASK_GEN2	0x00000fff
837ba00f20aa470 Paulo Zanoni                  2012-05-04   5674  #define   DSL_LINEMASK_GEN3	0x00001fff
a57c774ab2b849b Antti Koskipaa                2014-02-04   5675  #define _PIPEACONF		0x70008
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   5676  #define   PIPECONF_ENABLE	(1 << 31)
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   5677  #define   PIPECONF_DISABLE	0
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   5678  #define   PIPECONF_DOUBLE_WIDE	(1 << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   5679  #define   I965_PIPECONF_ACTIVE	(1 << 30)
b6ec10b36566c3e Jani Nikula                   2013-08-27   5680  #define   PIPECONF_DSI_PLL_LOCKED	(1 << 29) /* vlv & pipe A only */
f47166d2b0001fc Chris Wilson                  2012-03-22   5681  #define   PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   5682  #define   PIPECONF_SINGLE_WIDE	0
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   5683  #define   PIPECONF_PIPE_UNLOCKED 0
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   5684  #define   PIPECONF_PIPE_LOCKED	(1 << 25)
585fb111348f7cd Jesse Barnes                  2008-07-29   5685  #define   PIPECONF_FORCE_BORDER	(1 << 25)
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5686  #define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5687  #define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5688  #define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5689  #define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5690  #define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5691  #define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5692  #define   PIPECONF_GAMMA_MODE(x)	((x) << 24) /* pass in GAMMA_MODE_MODE_* */
9d5441de28e2b1e Ville Syrjälä                 2019-02-07   5693  #define   PIPECONF_GAMMA_MODE_SHIFT	24
d442ae181ba8608 Daniel Vetter                 2012-01-28   5694  #define   PIPECONF_INTERLACE_MASK	(7 << 21)
ee2b0b382a7e6cb Paulo Zanoni                  2012-10-05   5695  #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
d442ae181ba8608 Daniel Vetter                 2012-01-28   5696  /* Note that pre-gen3 does not support interlaced display directly. Panel
d442ae181ba8608 Daniel Vetter                 2012-01-28   5697   * fitting must be disabled on pre-ilk for interlaced. */
585fb111348f7cd Jesse Barnes                  2008-07-29   5698  #define   PIPECONF_PROGRESSIVE			(0 << 21)
d442ae181ba8608 Daniel Vetter                 2012-01-28   5699  #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
d442ae181ba8608 Daniel Vetter                 2012-01-28   5700  #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
585fb111348f7cd Jesse Barnes                  2008-07-29   5701  #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
d442ae181ba8608 Daniel Vetter                 2012-01-28   5702  #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
d442ae181ba8608 Daniel Vetter                 2012-01-28   5703  /* Ironlake and later have a complete new set of values for interlaced. PFIT
d442ae181ba8608 Daniel Vetter                 2012-01-28   5704   * means panel fitter required, PF means progressive fetch, DBL means power
d442ae181ba8608 Daniel Vetter                 2012-01-28   5705   * saving pixel doubling. */
d442ae181ba8608 Daniel Vetter                 2012-01-28   5706  #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
d442ae181ba8608 Daniel Vetter                 2012-01-28   5707  #define   PIPECONF_INTERLACED_ILK		(3 << 21)
d442ae181ba8608 Daniel Vetter                 2012-01-28   5708  #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
d442ae181ba8608 Daniel Vetter                 2012-01-28   5709  #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
1bd1bd806037af0 Daniel Vetter                 2013-04-29   5710  #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
439d7ac0879f9fd Pradeep Bhat                  2014-04-05   5711  #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
652c393a3368af8 Jesse Barnes                  2009-08-17   5712  #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
6fa7aec1db07f43 Vandana Kannan                2015-02-13   5713  #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
3685a8f38f2c54b Ville Syrjälä                 2013-01-17   5714  #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
dfd07d72cf70cc8 Daniel Vetter                 2012-12-17   5715  #define   PIPECONF_BPC_MASK	(0x7 << 5)
dfd07d72cf70cc8 Daniel Vetter                 2012-12-17   5716  #define   PIPECONF_8BPC		(0 << 5)
dfd07d72cf70cc8 Daniel Vetter                 2012-12-17   5717  #define   PIPECONF_10BPC	(1 << 5)
dfd07d72cf70cc8 Daniel Vetter                 2012-12-17   5718  #define   PIPECONF_6BPC		(2 << 5)
dfd07d72cf70cc8 Daniel Vetter                 2012-12-17   5719  #define   PIPECONF_12BPC	(3 << 5)
4f0d1aff791db89 Jesse Barnes                  2010-09-07   5720  #define   PIPECONF_DITHER_EN	(1 << 4)
4f0d1aff791db89 Jesse Barnes                  2010-09-07   5721  #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4f0d1aff791db89 Jesse Barnes                  2010-09-07   5722  #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
4f0d1aff791db89 Jesse Barnes                  2010-09-07   5723  #define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
4f0d1aff791db89 Jesse Barnes                  2010-09-07   5724  #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
4f0d1aff791db89 Jesse Barnes                  2010-09-07   5725  #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
a57c774ab2b849b Antti Koskipaa                2014-02-04   5726  #define _PIPEASTAT		0x70024
585fb111348f7cd Jesse Barnes                  2008-07-29   5727  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
579a9b0e72e954d Imre Deak                     2014-02-04   5728  #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   5729  #define   PIPE_CRC_ERROR_ENABLE			(1UL << 29)
585fb111348f7cd Jesse Barnes                  2008-07-29   5730  #define   PIPE_CRC_DONE_ENABLE			(1UL << 28)
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5731  #define   PERF_COUNTER2_INTERRUPT_EN		(1UL << 27)
585fb111348f7cd Jesse Barnes                  2008-07-29   5732  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL << 27)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5733  #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL << 26)
585fb111348f7cd Jesse Barnes                  2008-07-29   5734  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL << 26)
585fb111348f7cd Jesse Barnes                  2008-07-29   5735  #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL << 25)
585fb111348f7cd Jesse Barnes                  2008-07-29   5736  #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL << 24)
585fb111348f7cd Jesse Barnes                  2008-07-29   5737  #define   PIPE_DPST_EVENT_ENABLE		(1UL << 23)
c70af1e4b60a185 Ville Syrjälä                 2013-01-16   5738  #define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL << 22)
585fb111348f7cd Jesse Barnes                  2008-07-29   5739  #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL << 22)
585fb111348f7cd Jesse Barnes                  2008-07-29   5740  #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL << 21)
585fb111348f7cd Jesse Barnes                  2008-07-29   5741  #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL << 20)
10c59c511101bb0 Imre Deak                     2014-02-10   5742  #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL << 19)
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5743  #define   PERF_COUNTER_INTERRUPT_EN		(1UL << 19)
585fb111348f7cd Jesse Barnes                  2008-07-29   5744  #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL << 18) /* pre-965 */
585fb111348f7cd Jesse Barnes                  2008-07-29   5745  #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL << 18) /* 965 or later */
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5746  #define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL << 17)
585fb111348f7cd Jesse Barnes                  2008-07-29   5747  #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL << 17)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5748  #define   PIPEA_HBLANK_INT_EN_VLV		(1UL << 16)
585fb111348f7cd Jesse Barnes                  2008-07-29   5749  #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL << 16)
579a9b0e72e954d Imre Deak                     2014-02-04   5750  #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV	(1UL << 15)
579a9b0e72e954d Imre Deak                     2014-02-04   5751  #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL << 14)
585fb111348f7cd Jesse Barnes                  2008-07-29   5752  #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL << 13)
585fb111348f7cd Jesse Barnes                  2008-07-29   5753  #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL << 12)
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5754  #define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL << 11)
585fb111348f7cd Jesse Barnes                  2008-07-29   5755  #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL << 11)
579a9b0e72e954d Imre Deak                     2014-02-04   5756  #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   5757  #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL << 10)
585fb111348f7cd Jesse Barnes                  2008-07-29   5758  #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL << 9)
585fb111348f7cd Jesse Barnes                  2008-07-29   5759  #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL << 8)
585fb111348f7cd Jesse Barnes                  2008-07-29   5760  #define   PIPE_DPST_EVENT_STATUS		(1UL << 7)
10c59c511101bb0 Imre Deak                     2014-02-10   5761  #define   PIPE_A_PSR_STATUS_VLV			(1UL << 6)
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5762  #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL << 6)
585fb111348f7cd Jesse Barnes                  2008-07-29   5763  #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL << 5)
585fb111348f7cd Jesse Barnes                  2008-07-29   5764  #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL << 4)
10c59c511101bb0 Imre Deak                     2014-02-10   5765  #define   PIPE_B_PSR_STATUS_VLV			(1UL << 3)
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5766  #define   PERF_COUNTER_INTERRUPT_STATUS		(1UL << 3)
585fb111348f7cd Jesse Barnes                  2008-07-29   5767  #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL << 2) /* pre-965 */
585fb111348f7cd Jesse Barnes                  2008-07-29   5768  #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL << 2) /* 965 or later */
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5769  #define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL << 1)
585fb111348f7cd Jesse Barnes                  2008-07-29   5770  #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL << 1)
8cc96e7c732b64b Ville Syrjälä                 2014-04-09   5771  #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   5772  #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
585fb111348f7cd Jesse Barnes                  2008-07-29   5773  
755e901964a979e Imre Deak                     2014-02-10   5774  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
755e901964a979e Imre Deak                     2014-02-10   5775  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
755e901964a979e Imre Deak                     2014-02-10   5776  
a57c774ab2b849b Antti Koskipaa                2014-02-04   5777  #define PIPE_A_OFFSET		0x70000
a57c774ab2b849b Antti Koskipaa                2014-02-04   5778  #define PIPE_B_OFFSET		0x71000
a57c774ab2b849b Antti Koskipaa                2014-02-04   5779  #define PIPE_C_OFFSET		0x72000
f1f1d4fa5869c8b Lucas De Marchi               2019-07-11   5780  #define PIPE_D_OFFSET		0x73000
84fd4f4e18885fc Rafael Barbalho               2014-04-28   5781  #define CHV_PIPE_C_OFFSET	0x74000
a57c774ab2b849b Antti Koskipaa                2014-02-04   5782  /*
a57c774ab2b849b Antti Koskipaa                2014-02-04   5783   * There's actually no pipe EDP. Some pipe registers have
a57c774ab2b849b Antti Koskipaa                2014-02-04   5784   * simply shifted from the pipe to the transcoder, while
a57c774ab2b849b Antti Koskipaa                2014-02-04   5785   * keeping their original offset. Thus we need PIPE_EDP_OFFSET
a57c774ab2b849b Antti Koskipaa                2014-02-04   5786   * to access such registers in transcoder EDP.
a57c774ab2b849b Antti Koskipaa                2014-02-04   5787   */
a57c774ab2b849b Antti Koskipaa                2014-02-04   5788  #define PIPE_EDP_OFFSET	0x7f000
a57c774ab2b849b Antti Koskipaa                2014-02-04   5789  
372610f3c81491d Madhav Chauhan                2018-10-15   5790  /* ICL DSI 0 and 1 */
372610f3c81491d Madhav Chauhan                2018-10-15   5791  #define PIPE_DSI0_OFFSET	0x7b000
372610f3c81491d Madhav Chauhan                2018-10-15   5792  #define PIPE_DSI1_OFFSET	0x7b800
372610f3c81491d Madhav Chauhan                2018-10-15   5793  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5794  #define PIPECONF(pipe)		_MMIO_PIPE2(pipe, _PIPEACONF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5795  #define PIPEDSL(pipe)		_MMIO_PIPE2(pipe, _PIPEADSL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5796  #define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5797  #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5798  #define PIPESTAT(pipe)		_MMIO_PIPE2(pipe, _PIPEASTAT)
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   5799  
e262568eb58fe79 Ville Syrjälä                 2019-04-01   5800  #define  _PIPEAGCMAX           0x70010
e262568eb58fe79 Ville Syrjälä                 2019-04-01   5801  #define  _PIPEBGCMAX           0x71010
e262568eb58fe79 Ville Syrjälä                 2019-04-01   5802  #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
e262568eb58fe79 Ville Syrjälä                 2019-04-01   5803  
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5804  #define _PIPE_MISC_A			0x70030
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5805  #define _PIPE_MISC_B			0x71030
b22ca995ba1cbe7 Shashank Sharma               2017-07-24   5806  #define   PIPEMISC_YUV420_ENABLE	(1 << 27)
b22ca995ba1cbe7 Shashank Sharma               2017-07-24   5807  #define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
09b25812db10fcb Ville Syrjälä                 2019-04-12   5808  #define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
b22ca995ba1cbe7 Shashank Sharma               2017-07-24   5809  #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5810  #define   PIPEMISC_DITHER_BPC_MASK	(7 << 5)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5811  #define   PIPEMISC_DITHER_8_BPC		(0 << 5)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5812  #define   PIPEMISC_DITHER_10_BPC	(1 << 5)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5813  #define   PIPEMISC_DITHER_6_BPC		(2 << 5)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5814  #define   PIPEMISC_DITHER_12_BPC	(3 << 5)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5815  #define   PIPEMISC_DITHER_ENABLE	(1 << 4)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5816  #define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5817  #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5818  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
756f85cffef2bc8 Paulo Zanoni                  2013-11-02   5819  
c0550305fcbd82c Matt Roper                    2019-01-30   5820  /* Skylake+ pipe bottom (background) color */
c0550305fcbd82c Matt Roper                    2019-01-30   5821  #define _SKL_BOTTOM_COLOR_A		0x70034
c0550305fcbd82c Matt Roper                    2019-01-30   5822  #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
c0550305fcbd82c Matt Roper                    2019-01-30   5823  #define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
c0550305fcbd82c Matt Roper                    2019-01-30   5824  #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
c0550305fcbd82c Matt Roper                    2019-01-30   5825  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5826  #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
7983117f0ba2cec Jesse Barnes                  2012-06-20   5827  #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5828  #define   PIPEB_HLINE_INT_EN			(1 << 28)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5829  #define   PIPEB_VBLANK_INT_EN			(1 << 27)
579a9b0e72e954d Imre Deak                     2014-02-04   5830  #define   SPRITED_FLIP_DONE_INT_EN		(1 << 26)
579a9b0e72e954d Imre Deak                     2014-02-04   5831  #define   SPRITEC_FLIP_DONE_INT_EN		(1 << 25)
579a9b0e72e954d Imre Deak                     2014-02-04   5832  #define   PLANEB_FLIP_DONE_INT_EN		(1 << 24)
f3c67fdd6112a6a Ville Syrjälä                 2014-04-09   5833  #define   PIPE_PSR_INT_EN			(1 << 22)
7983117f0ba2cec Jesse Barnes                  2012-06-20   5834  #define   PIPEA_LINE_COMPARE_INT_EN		(1 << 21)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5835  #define   PIPEA_HLINE_INT_EN			(1 << 20)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5836  #define   PIPEA_VBLANK_INT_EN			(1 << 19)
579a9b0e72e954d Imre Deak                     2014-02-04   5837  #define   SPRITEB_FLIP_DONE_INT_EN		(1 << 18)
579a9b0e72e954d Imre Deak                     2014-02-04   5838  #define   SPRITEA_FLIP_DONE_INT_EN		(1 << 17)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5839  #define   PLANEA_FLIPDONE_INT_EN		(1 << 16)
f3c67fdd6112a6a Ville Syrjälä                 2014-04-09   5840  #define   PIPEC_LINE_COMPARE_INT_EN		(1 << 13)
f3c67fdd6112a6a Ville Syrjälä                 2014-04-09   5841  #define   PIPEC_HLINE_INT_EN			(1 << 12)
f3c67fdd6112a6a Ville Syrjälä                 2014-04-09   5842  #define   PIPEC_VBLANK_INT_EN			(1 << 11)
f3c67fdd6112a6a Ville Syrjälä                 2014-04-09   5843  #define   SPRITEF_FLIPDONE_INT_EN		(1 << 10)
f3c67fdd6112a6a Ville Syrjälä                 2014-04-09   5844  #define   SPRITEE_FLIPDONE_INT_EN		(1 << 9)
f3c67fdd6112a6a Ville Syrjälä                 2014-04-09   5845  #define   PLANEC_FLIPDONE_INT_EN		(1 << 8)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5846  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5847  #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5848  #define   SPRITEF_INVALID_GTT_INT_EN		(1 << 27)
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5849  #define   SPRITEE_INVALID_GTT_INT_EN		(1 << 26)
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5850  #define   PLANEC_INVALID_GTT_INT_EN		(1 << 25)
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5851  #define   CURSORC_INVALID_GTT_INT_EN		(1 << 24)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5852  #define   CURSORB_INVALID_GTT_INT_EN		(1 << 23)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5853  #define   CURSORA_INVALID_GTT_INT_EN		(1 << 22)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5854  #define   SPRITED_INVALID_GTT_INT_EN		(1 << 21)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5855  #define   SPRITEC_INVALID_GTT_INT_EN		(1 << 20)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5856  #define   PLANEB_INVALID_GTT_INT_EN		(1 << 19)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5857  #define   SPRITEB_INVALID_GTT_INT_EN		(1 << 18)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5858  #define   SPRITEA_INVALID_GTT_INT_EN		(1 << 17)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5859  #define   PLANEA_INVALID_GTT_INT_EN		(1 << 16)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5860  #define   DPINVGTT_EN_MASK			0xff0000
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5861  #define   DPINVGTT_EN_MASK_CHV			0xfff0000
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5862  #define   SPRITEF_INVALID_GTT_STATUS		(1 << 11)
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5863  #define   SPRITEE_INVALID_GTT_STATUS		(1 << 10)
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5864  #define   PLANEC_INVALID_GTT_STATUS		(1 << 9)
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5865  #define   CURSORC_INVALID_GTT_STATUS		(1 << 8)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5866  #define   CURSORB_INVALID_GTT_STATUS		(1 << 7)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5867  #define   CURSORA_INVALID_GTT_STATUS		(1 << 6)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5868  #define   SPRITED_INVALID_GTT_STATUS		(1 << 5)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5869  #define   SPRITEC_INVALID_GTT_STATUS		(1 << 4)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5870  #define   PLANEB_INVALID_GTT_STATUS		(1 << 3)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5871  #define   SPRITEB_INVALID_GTT_STATUS		(1 << 2)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5872  #define   SPRITEA_INVALID_GTT_STATUS		(1 << 1)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5873  #define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5874  #define   DPINVGTT_STATUS_MASK			0xff
bf67a6fd5ef8ef7 Ville Syrjälä                 2014-05-02   5875  #define   DPINVGTT_STATUS_MASK_CHV		0xfff
c46ce4d7e69d129 Jesse Barnes                  2012-03-28   5876  
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5877  #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
585fb111348f7cd Jesse Barnes                  2008-07-29   5878  #define   DSPARB_CSTART_MASK	(0x7f << 7)
585fb111348f7cd Jesse Barnes                  2008-07-29   5879  #define   DSPARB_CSTART_SHIFT	7
585fb111348f7cd Jesse Barnes                  2008-07-29   5880  #define   DSPARB_BSTART_MASK	(0x7f)
585fb111348f7cd Jesse Barnes                  2008-07-29   5881  #define   DSPARB_BSTART_SHIFT	0
7662c8bd6545c12 Shaohua Li                    2009-06-26   5882  #define   DSPARB_BEND_SHIFT	9 /* on 855 */
7662c8bd6545c12 Shaohua Li                    2009-06-26   5883  #define   DSPARB_AEND_SHIFT	0
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5884  #define   DSPARB_SPRITEA_SHIFT_VLV	0
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5885  #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5886  #define   DSPARB_SPRITEB_SHIFT_VLV	8
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5887  #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5888  #define   DSPARB_SPRITEC_SHIFT_VLV	16
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5889  #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5890  #define   DSPARB_SPRITED_SHIFT_VLV	24
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5891  #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5892  #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5893  #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5894  #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5895  #define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5896  #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5897  #define   DSPARB_SPRITEC_HI_SHIFT_VLV	8
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5898  #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5899  #define   DSPARB_SPRITED_HI_SHIFT_VLV	12
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5900  #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5901  #define   DSPARB_SPRITEE_HI_SHIFT_VLV	16
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5902  #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5903  #define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5904  #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5905  #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5906  #define   DSPARB_SPRITEE_SHIFT_VLV	0
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5907  #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5908  #define   DSPARB_SPRITEF_SHIFT_VLV	8
54f1b6e15db8772 Ville Syrjälä                 2015-06-24   5909  #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
b500472026e40ef Ville Syrjälä                 2015-03-05   5910  
0a56067469bde66 Ville Syrjälä                 2014-06-11   5911  /* pnv/gen4/g4x/vlv/chv */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5912  #define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   5913  #define   DSPFW_SR_SHIFT		23
d4294342fd4b94a Zhao Yakui                    2010-03-22   5914  #define   DSPFW_SR_MASK			(0x1ff << 23)
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   5915  #define   DSPFW_CURSORB_SHIFT		16
d4294342fd4b94a Zhao Yakui                    2010-03-22   5916  #define   DSPFW_CURSORB_MASK		(0x3f << 16)
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   5917  #define   DSPFW_PLANEB_SHIFT		8
d4294342fd4b94a Zhao Yakui                    2010-03-22   5918  #define   DSPFW_PLANEB_MASK		(0x7f << 8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5919  #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5920  #define   DSPFW_PLANEA_SHIFT		0
0a56067469bde66 Ville Syrjälä                 2014-06-11   5921  #define   DSPFW_PLANEA_MASK		(0x7f << 0)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5922  #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5923  #define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5924  #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5925  #define   DSPFW_FBC_SR_SHIFT		28
0a56067469bde66 Ville Syrjälä                 2014-06-11   5926  #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5927  #define   DSPFW_FBC_HPLL_SR_SHIFT	24
0a56067469bde66 Ville Syrjälä                 2014-06-11   5928  #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5929  #define   DSPFW_SPRITEB_SHIFT		(16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5930  #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5931  #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
21bd770b9c90ee6 Zhao Yakui                    2010-01-13   5932  #define   DSPFW_CURSORA_SHIFT		8
0a56067469bde66 Ville Syrjälä                 2014-06-11   5933  #define   DSPFW_CURSORA_MASK		(0x3f << 8)
f4998963f2fbd4a Ville Syrjälä                 2015-03-10   5934  #define   DSPFW_PLANEC_OLD_SHIFT	0
f4998963f2fbd4a Ville Syrjälä                 2015-03-10   5935  #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5936  #define   DSPFW_SPRITEA_SHIFT		0
0a56067469bde66 Ville Syrjälä                 2014-06-11   5937  #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5938  #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   5939  #define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   5940  #define   DSPFW_HPLL_SR_EN		(1 << 31)
f2b115e69d46344 Adam Jackson                  2009-12-03   5941  #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5942  #define   DSPFW_CURSOR_SR_SHIFT		24
d4294342fd4b94a Zhao Yakui                    2010-03-22   5943  #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
d4294342fd4b94a Zhao Yakui                    2010-03-22   5944  #define   DSPFW_HPLL_CURSOR_SHIFT	16
d4294342fd4b94a Zhao Yakui                    2010-03-22   5945  #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5946  #define   DSPFW_HPLL_SR_SHIFT		0
0a56067469bde66 Ville Syrjälä                 2014-06-11   5947  #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5948  
0a56067469bde66 Ville Syrjälä                 2014-06-11   5949  /* vlv/chv */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5950  #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5951  #define   DSPFW_SPRITEB_WM1_SHIFT	16
0a56067469bde66 Ville Syrjälä                 2014-06-11   5952  #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5953  #define   DSPFW_CURSORA_WM1_SHIFT	8
0a56067469bde66 Ville Syrjälä                 2014-06-11   5954  #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5955  #define   DSPFW_SPRITEA_WM1_SHIFT	0
0a56067469bde66 Ville Syrjälä                 2014-06-11   5956  #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5957  #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5958  #define   DSPFW_PLANEB_WM1_SHIFT	24
0a56067469bde66 Ville Syrjälä                 2014-06-11   5959  #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5960  #define   DSPFW_PLANEA_WM1_SHIFT	16
0a56067469bde66 Ville Syrjälä                 2014-06-11   5961  #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5962  #define   DSPFW_CURSORB_WM1_SHIFT	8
0a56067469bde66 Ville Syrjälä                 2014-06-11   5963  #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5964  #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
0a56067469bde66 Ville Syrjälä                 2014-06-11   5965  #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5966  #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5967  #define   DSPFW_SR_WM1_SHIFT		0
0a56067469bde66 Ville Syrjälä                 2014-06-11   5968  #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5969  #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5970  #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5971  #define   DSPFW_SPRITED_WM1_SHIFT	24
0a56067469bde66 Ville Syrjälä                 2014-06-11   5972  #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5973  #define   DSPFW_SPRITED_SHIFT		16
15665979ca601f4 Ville Syrjälä                 2015-03-10   5974  #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5975  #define   DSPFW_SPRITEC_WM1_SHIFT	8
0a56067469bde66 Ville Syrjälä                 2014-06-11   5976  #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5977  #define   DSPFW_SPRITEC_SHIFT		0
15665979ca601f4 Ville Syrjälä                 2015-03-10   5978  #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5979  #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5980  #define   DSPFW_SPRITEF_WM1_SHIFT	24
0a56067469bde66 Ville Syrjälä                 2014-06-11   5981  #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5982  #define   DSPFW_SPRITEF_SHIFT		16
15665979ca601f4 Ville Syrjälä                 2015-03-10   5983  #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5984  #define   DSPFW_SPRITEE_WM1_SHIFT	8
0a56067469bde66 Ville Syrjälä                 2014-06-11   5985  #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5986  #define   DSPFW_SPRITEE_SHIFT		0
15665979ca601f4 Ville Syrjälä                 2015-03-10   5987  #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5988  #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
0a56067469bde66 Ville Syrjälä                 2014-06-11   5989  #define   DSPFW_PLANEC_WM1_SHIFT	24
0a56067469bde66 Ville Syrjälä                 2014-06-11   5990  #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5991  #define   DSPFW_PLANEC_SHIFT		16
15665979ca601f4 Ville Syrjälä                 2015-03-10   5992  #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5993  #define   DSPFW_CURSORC_WM1_SHIFT	8
0a56067469bde66 Ville Syrjälä                 2014-06-11   5994  #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5995  #define   DSPFW_CURSORC_SHIFT		0
0a56067469bde66 Ville Syrjälä                 2014-06-11   5996  #define   DSPFW_CURSORC_MASK		(0x3f << 0)
0a56067469bde66 Ville Syrjälä                 2014-06-11   5997  
0a56067469bde66 Ville Syrjälä                 2014-06-11   5998  /* vlv/chv high order bits */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   5999  #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6000  #define   DSPFW_SR_HI_SHIFT		24
ae80152ddad252f Ville Syrjälä                 2015-03-05   6001  #define   DSPFW_SR_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
0a56067469bde66 Ville Syrjälä                 2014-06-11   6002  #define   DSPFW_SPRITEF_HI_SHIFT	23
0a56067469bde66 Ville Syrjälä                 2014-06-11   6003  #define   DSPFW_SPRITEF_HI_MASK		(1 << 23)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6004  #define   DSPFW_SPRITEE_HI_SHIFT	22
0a56067469bde66 Ville Syrjälä                 2014-06-11   6005  #define   DSPFW_SPRITEE_HI_MASK		(1 << 22)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6006  #define   DSPFW_PLANEC_HI_SHIFT		21
0a56067469bde66 Ville Syrjälä                 2014-06-11   6007  #define   DSPFW_PLANEC_HI_MASK		(1 << 21)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6008  #define   DSPFW_SPRITED_HI_SHIFT	20
0a56067469bde66 Ville Syrjälä                 2014-06-11   6009  #define   DSPFW_SPRITED_HI_MASK		(1 << 20)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6010  #define   DSPFW_SPRITEC_HI_SHIFT	16
0a56067469bde66 Ville Syrjälä                 2014-06-11   6011  #define   DSPFW_SPRITEC_HI_MASK		(1 << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6012  #define   DSPFW_PLANEB_HI_SHIFT		12
0a56067469bde66 Ville Syrjälä                 2014-06-11   6013  #define   DSPFW_PLANEB_HI_MASK		(1 << 12)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6014  #define   DSPFW_SPRITEB_HI_SHIFT	8
0a56067469bde66 Ville Syrjälä                 2014-06-11   6015  #define   DSPFW_SPRITEB_HI_MASK		(1 << 8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6016  #define   DSPFW_SPRITEA_HI_SHIFT	4
0a56067469bde66 Ville Syrjälä                 2014-06-11   6017  #define   DSPFW_SPRITEA_HI_MASK		(1 << 4)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6018  #define   DSPFW_PLANEA_HI_SHIFT		0
0a56067469bde66 Ville Syrjälä                 2014-06-11   6019  #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6020  #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6021  #define   DSPFW_SR_WM1_HI_SHIFT		24
ae80152ddad252f Ville Syrjälä                 2015-03-05   6022  #define   DSPFW_SR_WM1_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
0a56067469bde66 Ville Syrjälä                 2014-06-11   6023  #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
0a56067469bde66 Ville Syrjälä                 2014-06-11   6024  #define   DSPFW_SPRITEF_WM1_HI_MASK	(1 << 23)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6025  #define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
0a56067469bde66 Ville Syrjälä                 2014-06-11   6026  #define   DSPFW_SPRITEE_WM1_HI_MASK	(1 << 22)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6027  #define   DSPFW_PLANEC_WM1_HI_SHIFT	21
0a56067469bde66 Ville Syrjälä                 2014-06-11   6028  #define   DSPFW_PLANEC_WM1_HI_MASK	(1 << 21)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6029  #define   DSPFW_SPRITED_WM1_HI_SHIFT	20
0a56067469bde66 Ville Syrjälä                 2014-06-11   6030  #define   DSPFW_SPRITED_WM1_HI_MASK	(1 << 20)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6031  #define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
0a56067469bde66 Ville Syrjälä                 2014-06-11   6032  #define   DSPFW_SPRITEC_WM1_HI_MASK	(1 << 16)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6033  #define   DSPFW_PLANEB_WM1_HI_SHIFT	12
0a56067469bde66 Ville Syrjälä                 2014-06-11   6034  #define   DSPFW_PLANEB_WM1_HI_MASK	(1 << 12)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6035  #define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
0a56067469bde66 Ville Syrjälä                 2014-06-11   6036  #define   DSPFW_SPRITEB_WM1_HI_MASK	(1 << 8)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6037  #define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
0a56067469bde66 Ville Syrjälä                 2014-06-11   6038  #define   DSPFW_SPRITEA_WM1_HI_MASK	(1 << 4)
0a56067469bde66 Ville Syrjälä                 2014-06-11   6039  #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
0a56067469bde66 Ville Syrjälä                 2014-06-11   6040  #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
7662c8bd6545c12 Shaohua Li                    2009-06-26   6041  
12a3c0551137425 Gajanan Bhat                  2012-03-28   6042  /* drain latency register values*/
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6043  #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
1abc4dc7e2ca788 Ville Syrjälä                 2014-06-26   6044  #define DDL_CURSOR_SHIFT		24
01e184cc85d4516 Gajanan Bhat                  2014-08-07   6045  #define DDL_SPRITE_SHIFT(sprite)	(8 + 8 * (sprite))
1abc4dc7e2ca788 Ville Syrjälä                 2014-06-26   6046  #define DDL_PLANE_SHIFT			0
341c526f43fdd2d Ville Syrjälä                 2015-03-05   6047  #define DDL_PRECISION_HIGH		(1 << 7)
341c526f43fdd2d Ville Syrjälä                 2015-03-05   6048  #define DDL_PRECISION_LOW		(0 << 7)
0948c2651413d56 Gajanan Bhat                  2014-08-07   6049  #define DRAIN_LATENCY_MASK		0x7f
12a3c0551137425 Gajanan Bhat                  2012-03-28   6050  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6051  #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
c6beb13ef33ae94 Ville Syrjälä                 2015-03-05   6052  #define  CBR_PND_DEADLINE_DISABLE	(1 << 31)
aa17cdb4f836787 Jani Nikula                   2015-09-04   6053  #define  CBR_PWM_CLOCK_MUX_SELECT	(1 << 30)
c6beb13ef33ae94 Ville Syrjälä                 2015-03-05   6054  
c231775c2df845a Ville Syrjälä                 2016-03-15   6055  #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
dfa311f0d8e2bbd Ville Syrjälä                 2017-09-13   6056  #define  CBR_DPLLBMD_PIPE(pipe)		(1 << (7 + (pipe) * 11)) /* pipes B and C */
c231775c2df845a Ville Syrjälä                 2016-03-15   6057  
7662c8bd6545c12 Shaohua Li                    2009-06-26   6058  /* FIFO watermark sizes etc */
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   6059  #define G4X_FIFO_LINE_SIZE	64
7662c8bd6545c12 Shaohua Li                    2009-06-26   6060  #define I915_FIFO_LINE_SIZE	64
7662c8bd6545c12 Shaohua Li                    2009-06-26   6061  #define I830_FIFO_LINE_SIZE	32
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   6062  
ceb042468763db2 Jesse Barnes                  2012-03-28   6063  #define VALLEYVIEW_FIFO_SIZE	255
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   6064  #define G4X_FIFO_SIZE		127
1b07e04e9cd443f Zhao Yakui                    2010-06-12   6065  #define I965_FIFO_SIZE		512
1b07e04e9cd443f Zhao Yakui                    2010-06-12   6066  #define I945_FIFO_SIZE		127
7662c8bd6545c12 Shaohua Li                    2009-06-26   6067  #define I915_FIFO_SIZE		95
dff33cfcefa31c3 Jesse Barnes                  2009-07-14   6068  #define I855GM_FIFO_SIZE	127 /* In cachelines */
7662c8bd6545c12 Shaohua Li                    2009-06-26   6069  #define I830_FIFO_SIZE		95
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   6070  
ceb042468763db2 Jesse Barnes                  2012-03-28   6071  #define VALLEYVIEW_MAX_WM	0xff
0e442c60dd39ac6 Jesse Barnes                  2009-10-19   6072  #define G4X_MAX_WM		0x3f
7662c8bd6545c12 Shaohua Li                    2009-06-26   6073  #define I915_MAX_WM		0x3f
7662c8bd6545c12 Shaohua Li                    2009-06-26   6074  
f2b115e69d46344 Adam Jackson                  2009-12-03   6075  #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
f2b115e69d46344 Adam Jackson                  2009-12-03   6076  #define PINEVIEW_FIFO_LINE_SIZE	64
f2b115e69d46344 Adam Jackson                  2009-12-03   6077  #define PINEVIEW_MAX_WM		0x1ff
f2b115e69d46344 Adam Jackson                  2009-12-03   6078  #define PINEVIEW_DFT_WM		0x3f
f2b115e69d46344 Adam Jackson                  2009-12-03   6079  #define PINEVIEW_DFT_HPLLOFF_WM	0
f2b115e69d46344 Adam Jackson                  2009-12-03   6080  #define PINEVIEW_GUARD_WM		10
f2b115e69d46344 Adam Jackson                  2009-12-03   6081  #define PINEVIEW_CURSOR_FIFO		64
f2b115e69d46344 Adam Jackson                  2009-12-03   6082  #define PINEVIEW_CURSOR_MAX_WM	0x3f
f2b115e69d46344 Adam Jackson                  2009-12-03   6083  #define PINEVIEW_CURSOR_DFT_WM	0
f2b115e69d46344 Adam Jackson                  2009-12-03   6084  #define PINEVIEW_CURSOR_GUARD_WM	5
7662c8bd6545c12 Shaohua Li                    2009-06-26   6085  
ceb042468763db2 Jesse Barnes                  2012-03-28   6086  #define VALLEYVIEW_CURSOR_MAX_WM 64
4fe5e61180d8ea2 Zhao Yakui                    2010-06-12   6087  #define I965_CURSOR_FIFO	64
4fe5e61180d8ea2 Zhao Yakui                    2010-06-12   6088  #define I965_CURSOR_MAX_WM	32
4fe5e61180d8ea2 Zhao Yakui                    2010-06-12   6089  #define I965_CURSOR_DFT_WM	8
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6090  
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6091  /* Watermark register definitions for SKL */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6092  #define _CUR_WM_A_0		0x70140
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6093  #define _CUR_WM_B_0		0x71140
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6094  #define _PLANE_WM_1_A_0		0x70240
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6095  #define _PLANE_WM_1_B_0		0x71240
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6096  #define _PLANE_WM_2_A_0		0x70340
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6097  #define _PLANE_WM_2_B_0		0x71340
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6098  #define _PLANE_WM_TRANS_1_A_0	0x70268
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6099  #define _PLANE_WM_TRANS_1_B_0	0x71268
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6100  #define _PLANE_WM_TRANS_2_A_0	0x70368
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6101  #define _PLANE_WM_TRANS_2_B_0	0x71368
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6102  #define _CUR_WM_TRANS_A_0	0x70168
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6103  #define _CUR_WM_TRANS_B_0	0x71168
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6104  #define   PLANE_WM_EN		(1 << 31)
2ed8e1f560e517b Ville Syrjälä                 2019-02-13   6105  #define   PLANE_WM_IGNORE_LINES	(1 << 30)
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6106  #define   PLANE_WM_LINES_SHIFT	14
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6107  #define   PLANE_WM_LINES_MASK	0x1f
c7e716b8617e5f4 Ville Syrjälä                 2019-02-05   6108  #define   PLANE_WM_BLOCKS_MASK	0x7ff /* skl+: 10 bits, icl+ 11 bits */
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6109  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6110  #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6111  #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6112  #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6113  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6114  #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6115  #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6116  #define _PLANE_WM_BASE(pipe, plane)	\
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6117  			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6118  #define PLANE_WM(pipe, plane, level)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6119  			_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6120  #define _PLANE_WM_TRANS_1(pipe)	\
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6121  			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6122  #define _PLANE_WM_TRANS_2(pipe)	\
086f8e84a085a43 Ville Syrjälä                 2015-11-04   6123  			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6124  #define PLANE_WM_TRANS(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6125  	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
fae1267df8a1414 Pradeep Bhat                  2014-11-04   6126  
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6127  /* define the Watermark register on Ironlake */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6128  #define WM0_PIPEA_ILK		_MMIO(0x45100)
1996d624403483a Ville Syrjälä                 2013-10-09   6129  #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6130  #define  WM0_PIPE_PLANE_SHIFT	16
1996d624403483a Ville Syrjälä                 2013-10-09   6131  #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6132  #define  WM0_PIPE_SPRITE_SHIFT	8
1996d624403483a Ville Syrjälä                 2013-10-09   6133  #define  WM0_PIPE_CURSOR_MASK	(0xff)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6134  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6135  #define WM0_PIPEB_ILK		_MMIO(0x45104)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6136  #define WM0_PIPEC_IVB		_MMIO(0x45200)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6137  #define WM1_LP_ILK		_MMIO(0x45108)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6138  #define  WM1_LP_SR_EN		(1 << 31)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6139  #define  WM1_LP_LATENCY_SHIFT	24
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6140  #define  WM1_LP_LATENCY_MASK	(0x7f << 24)
4ed765f966c8279 Chris Wilson                  2010-09-11   6141  #define  WM1_LP_FBC_MASK	(0xf << 20)
4ed765f966c8279 Chris Wilson                  2010-09-11   6142  #define  WM1_LP_FBC_SHIFT	20
416f4727abf9e5e Ville Syrjälä                 2013-11-02   6143  #define  WM1_LP_FBC_SHIFT_BDW	19
1996d624403483a Ville Syrjälä                 2013-10-09   6144  #define  WM1_LP_SR_MASK		(0x7ff << 8)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6145  #define  WM1_LP_SR_SHIFT	8
1996d624403483a Ville Syrjälä                 2013-10-09   6146  #define  WM1_LP_CURSOR_MASK	(0xff)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6147  #define WM2_LP_ILK		_MMIO(0x4510c)
dd8849c8f59ec1c Jesse Barnes                  2010-09-09   6148  #define  WM2_LP_EN		(1 << 31)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6149  #define WM3_LP_ILK		_MMIO(0x45110)
dd8849c8f59ec1c Jesse Barnes                  2010-09-09   6150  #define  WM3_LP_EN		(1 << 31)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6151  #define WM1S_LP_ILK		_MMIO(0x45120)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6152  #define WM2S_LP_IVB		_MMIO(0x45124)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6153  #define WM3S_LP_IVB		_MMIO(0x45128)
dd8849c8f59ec1c Jesse Barnes                  2010-09-09   6154  #define  WM1S_LP_EN		(1 << 31)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6155  
cca32e9ad372172 Paulo Zanoni                  2013-05-31   6156  #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
cca32e9ad372172 Paulo Zanoni                  2013-05-31   6157  	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
cca32e9ad372172 Paulo Zanoni                  2013-05-31   6158  	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
cca32e9ad372172 Paulo Zanoni                  2013-05-31   6159  
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6160  /* Memory latency timer register */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6161  #define MLTR_ILK		_MMIO(0x11222)
b79d4990226defc Jesse Barnes                  2010-12-21   6162  #define  MLTR_WM1_SHIFT		0
b79d4990226defc Jesse Barnes                  2010-12-21   6163  #define  MLTR_WM2_SHIFT		8
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6164  /* the unit of memory self-refresh latency time is 0.5us */
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6165  #define  ILK_SRLT_MASK		0x3f
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   6166  
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6167  
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6168  /* the address where we get all kinds of latency value */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6169  #define SSKPD			_MMIO(0x5d10)
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6170  #define SSKPD_WM_MASK		0x3f
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6171  #define SSKPD_WM0_SHIFT		0
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6172  #define SSKPD_WM1_SHIFT		8
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6173  #define SSKPD_WM2_SHIFT		16
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6174  #define SSKPD_WM3_SHIFT		24
1398261a2e84c53 Yuanhan Liu                   2010-12-15   6175  
585fb111348f7cd Jesse Barnes                  2008-07-29   6176  /*
585fb111348f7cd Jesse Barnes                  2008-07-29   6177   * The two pipe frame counter registers are not synchronized, so
585fb111348f7cd Jesse Barnes                  2008-07-29   6178   * reading a stable value is somewhat tricky. The following code
585fb111348f7cd Jesse Barnes                  2008-07-29   6179   * should work:
585fb111348f7cd Jesse Barnes                  2008-07-29   6180   *
585fb111348f7cd Jesse Barnes                  2008-07-29   6181   *  do {
585fb111348f7cd Jesse Barnes                  2008-07-29   6182   *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
585fb111348f7cd Jesse Barnes                  2008-07-29   6183   *             PIPE_FRAME_HIGH_SHIFT;
585fb111348f7cd Jesse Barnes                  2008-07-29   6184   *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
585fb111348f7cd Jesse Barnes                  2008-07-29   6185   *             PIPE_FRAME_LOW_SHIFT);
585fb111348f7cd Jesse Barnes                  2008-07-29   6186   *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
585fb111348f7cd Jesse Barnes                  2008-07-29   6187   *             PIPE_FRAME_HIGH_SHIFT);
585fb111348f7cd Jesse Barnes                  2008-07-29   6188   *  } while (high1 != high2);
585fb111348f7cd Jesse Barnes                  2008-07-29   6189   *  frame = (high1 << 8) | low1;
585fb111348f7cd Jesse Barnes                  2008-07-29   6190   */
25a2e2d0f35e329 Ville Syrjälä                 2013-10-11   6191  #define _PIPEAFRAMEHIGH          0x70040
585fb111348f7cd Jesse Barnes                  2008-07-29   6192  #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
585fb111348f7cd Jesse Barnes                  2008-07-29   6193  #define   PIPE_FRAME_HIGH_SHIFT   0
25a2e2d0f35e329 Ville Syrjälä                 2013-10-11   6194  #define _PIPEAFRAMEPIXEL         0x70044
585fb111348f7cd Jesse Barnes                  2008-07-29   6195  #define   PIPE_FRAME_LOW_MASK     0xff000000
585fb111348f7cd Jesse Barnes                  2008-07-29   6196  #define   PIPE_FRAME_LOW_SHIFT    24
585fb111348f7cd Jesse Barnes                  2008-07-29   6197  #define   PIPE_PIXEL_MASK         0x00ffffff
585fb111348f7cd Jesse Barnes                  2008-07-29   6198  #define   PIPE_PIXEL_SHIFT        0
9880b7a527ffbb5 Jesse Barnes                  2009-02-06   6199  /* GM45+ just has to be different */
fd8f507c0de97c3 Ville Syrjälä                 2015-09-18   6200  #define _PIPEA_FRMCOUNT_G4X	0x70040
fd8f507c0de97c3 Ville Syrjälä                 2015-09-18   6201  #define _PIPEA_FLIPCOUNT_G4X	0x70044
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6202  #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6203  #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
585fb111348f7cd Jesse Barnes                  2008-07-29   6204  
585fb111348f7cd Jesse Barnes                  2008-07-29   6205  /* Cursor A & B regs */
5efb3e283853683 Ville Syrjälä                 2014-04-09   6206  #define _CURACNTR		0x70080
14b60391587ab9b Jesse Barnes                  2009-05-20   6207  /* Old style CUR*CNTR flags (desktop 8xx) */
14b60391587ab9b Jesse Barnes                  2009-05-20   6208  #define   CURSOR_ENABLE		0x80000000
14b60391587ab9b Jesse Barnes                  2009-05-20   6209  #define   CURSOR_GAMMA_ENABLE	0x40000000
dc41c154ffc30af Ville Syrjälä                 2014-08-13   6210  #define   CURSOR_STRIDE_SHIFT	28
dc41c154ffc30af Ville Syrjälä                 2014-08-13   6211  #define   CURSOR_STRIDE(x)	((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
14b60391587ab9b Jesse Barnes                  2009-05-20   6212  #define   CURSOR_FORMAT_SHIFT	24
14b60391587ab9b Jesse Barnes                  2009-05-20   6213  #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
14b60391587ab9b Jesse Barnes                  2009-05-20   6214  #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
14b60391587ab9b Jesse Barnes                  2009-05-20   6215  #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
14b60391587ab9b Jesse Barnes                  2009-05-20   6216  #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
14b60391587ab9b Jesse Barnes                  2009-05-20   6217  #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
14b60391587ab9b Jesse Barnes                  2009-05-20   6218  #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
14b60391587ab9b Jesse Barnes                  2009-05-20   6219  /* New style CUR*CNTR flags */
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6220  #define   MCURSOR_MODE		0x27
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6221  #define   MCURSOR_MODE_DISABLE   0x00
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6222  #define   MCURSOR_MODE_128_32B_AX 0x02
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6223  #define   MCURSOR_MODE_256_32B_AX 0x03
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6224  #define   MCURSOR_MODE_64_32B_AX 0x07
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6225  #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6226  #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6227  #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
eade6c894498c12 Ville Syrjälä                 2018-01-30   6228  #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
eade6c894498c12 Ville Syrjälä                 2018-01-30   6229  #define   MCURSOR_PIPE_SELECT_SHIFT	28
d509e28b70e45ea Ville Syrjälä                 2017-03-27   6230  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
585fb111348f7cd Jesse Barnes                  2008-07-29   6231  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
8271b2ef71aaaba Ville Syrjälä                 2019-02-07   6232  #define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6233  #define   MCURSOR_ROTATE_180	(1 << 15)
b99b9ec1d374fd0 Ville Syrjälä                 2018-01-31   6234  #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
5efb3e283853683 Ville Syrjälä                 2014-04-09   6235  #define _CURABASE		0x70084
5efb3e283853683 Ville Syrjälä                 2014-04-09   6236  #define _CURAPOS		0x70088
585fb111348f7cd Jesse Barnes                  2008-07-29   6237  #define   CURSOR_POS_MASK       0x007FF
585fb111348f7cd Jesse Barnes                  2008-07-29   6238  #define   CURSOR_POS_SIGN       0x8000
585fb111348f7cd Jesse Barnes                  2008-07-29   6239  #define   CURSOR_X_SHIFT        0
585fb111348f7cd Jesse Barnes                  2008-07-29   6240  #define   CURSOR_Y_SHIFT        16
024faac7d59b97b Ville Syrjälä                 2017-03-27   6241  #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
024faac7d59b97b Ville Syrjälä                 2017-03-27   6242  #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
024faac7d59b97b Ville Syrjälä                 2017-03-27   6243  #define   CUR_FBC_CTL_EN	(1 << 31)
a8ada068a5025d7 Rodrigo Vivi                  2018-03-12   6244  #define _CURASURFLIVE		0x700ac /* g4x+ */
5efb3e283853683 Ville Syrjälä                 2014-04-09   6245  #define _CURBCNTR		0x700c0
5efb3e283853683 Ville Syrjälä                 2014-04-09   6246  #define _CURBBASE		0x700c4
5efb3e283853683 Ville Syrjälä                 2014-04-09   6247  #define _CURBPOS		0x700c8
585fb111348f7cd Jesse Barnes                  2008-07-29   6248  
65a21cd65316145 Jesse Barnes                  2011-10-12   6249  #define _CURBCNTR_IVB		0x71080
65a21cd65316145 Jesse Barnes                  2011-10-12   6250  #define _CURBBASE_IVB		0x71084
65a21cd65316145 Jesse Barnes                  2011-10-12   6251  #define _CURBPOS_IVB		0x71088
65a21cd65316145 Jesse Barnes                  2011-10-12   6252  
5efb3e283853683 Ville Syrjälä                 2014-04-09   6253  #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
5efb3e283853683 Ville Syrjälä                 2014-04-09   6254  #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
5efb3e283853683 Ville Syrjälä                 2014-04-09   6255  #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
024faac7d59b97b Ville Syrjälä                 2017-03-27   6256  #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
a8ada068a5025d7 Rodrigo Vivi                  2018-03-12   6257  #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
c4a1d9e4dc5d531 Chris Wilson                  2010-11-21   6258  
5efb3e283853683 Ville Syrjälä                 2014-04-09   6259  #define CURSOR_A_OFFSET 0x70080
5efb3e283853683 Ville Syrjälä                 2014-04-09   6260  #define CURSOR_B_OFFSET 0x700c0
5efb3e283853683 Ville Syrjälä                 2014-04-09   6261  #define CHV_CURSOR_C_OFFSET 0x700e0
5efb3e283853683 Ville Syrjälä                 2014-04-09   6262  #define IVB_CURSOR_B_OFFSET 0x71080
5efb3e283853683 Ville Syrjälä                 2014-04-09   6263  #define IVB_CURSOR_C_OFFSET 0x72080
65a21cd65316145 Jesse Barnes                  2011-10-12   6264  
585fb111348f7cd Jesse Barnes                  2008-07-29   6265  /* Display A control */
a57c774ab2b849b Antti Koskipaa                2014-02-04   6266  #define _DSPACNTR				0x70180
585fb111348f7cd Jesse Barnes                  2008-07-29   6267  #define   DISPLAY_PLANE_ENABLE			(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   6268  #define   DISPLAY_PLANE_DISABLE			0
585fb111348f7cd Jesse Barnes                  2008-07-29   6269  #define   DISPPLANE_GAMMA_ENABLE		(1 << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   6270  #define   DISPPLANE_GAMMA_DISABLE		0
585fb111348f7cd Jesse Barnes                  2008-07-29   6271  #define   DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6272  #define   DISPPLANE_YUV422			(0x0 << 26)
585fb111348f7cd Jesse Barnes                  2008-07-29   6273  #define   DISPPLANE_8BPP			(0x2 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6274  #define   DISPPLANE_BGRA555			(0x3 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6275  #define   DISPPLANE_BGRX555			(0x4 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6276  #define   DISPPLANE_BGRX565			(0x5 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6277  #define   DISPPLANE_BGRX888			(0x6 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6278  #define   DISPPLANE_BGRA888			(0x7 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6279  #define   DISPPLANE_RGBX101010			(0x8 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6280  #define   DISPPLANE_RGBA101010			(0x9 << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6281  #define   DISPPLANE_BGRX101010			(0xa << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6282  #define   DISPPLANE_RGBX161616			(0xc << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6283  #define   DISPPLANE_RGBX888			(0xe << 26)
57779d06367a915 Ville Syrjälä                 2012-10-31   6284  #define   DISPPLANE_RGBA888			(0xf << 26)
585fb111348f7cd Jesse Barnes                  2008-07-29   6285  #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
585fb111348f7cd Jesse Barnes                  2008-07-29   6286  #define   DISPPLANE_STEREO_DISABLE		0
8271b2ef71aaaba Ville Syrjälä                 2019-02-07   6287  #define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
b24e71798871089 Jesse Barnes                  2011-01-04   6288  #define   DISPPLANE_SEL_PIPE_SHIFT		24
b24e71798871089 Jesse Barnes                  2011-01-04   6289  #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
d509e28b70e45ea Ville Syrjälä                 2017-03-27   6290  #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
585fb111348f7cd Jesse Barnes                  2008-07-29   6291  #define   DISPPLANE_SRC_KEY_ENABLE		(1 << 22)
585fb111348f7cd Jesse Barnes                  2008-07-29   6292  #define   DISPPLANE_SRC_KEY_DISABLE		0
585fb111348f7cd Jesse Barnes                  2008-07-29   6293  #define   DISPPLANE_LINE_DOUBLE			(1 << 20)
585fb111348f7cd Jesse Barnes                  2008-07-29   6294  #define   DISPPLANE_NO_LINE_DOUBLE		0
585fb111348f7cd Jesse Barnes                  2008-07-29   6295  #define   DISPPLANE_STEREO_POLARITY_FIRST	0
585fb111348f7cd Jesse Barnes                  2008-07-29   6296  #define   DISPPLANE_STEREO_POLARITY_SECOND	(1 << 18)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6297  #define   DISPPLANE_ALPHA_PREMULTIPLY		(1 << 16) /* CHV pipe B */
48404c1e53d4e15 Sonika Jindal                 2014-08-22   6298  #define   DISPPLANE_ROTATE_180			(1 << 15)
f2b115e69d46344 Adam Jackson                  2009-12-03   6299  #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1 << 14) /* Ironlake */
f544847fbaf0992 Jesse Barnes                  2009-04-14   6300  #define   DISPPLANE_TILED			(1 << 10)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6301  #define   DISPPLANE_MIRROR			(1 << 8) /* CHV pipe B */
a57c774ab2b849b Antti Koskipaa                2014-02-04   6302  #define _DSPAADDR				0x70184
a57c774ab2b849b Antti Koskipaa                2014-02-04   6303  #define _DSPASTRIDE				0x70188
a57c774ab2b849b Antti Koskipaa                2014-02-04   6304  #define _DSPAPOS				0x7018C /* reserved */
a57c774ab2b849b Antti Koskipaa                2014-02-04   6305  #define _DSPASIZE				0x70190
a57c774ab2b849b Antti Koskipaa                2014-02-04   6306  #define _DSPASURF				0x7019C /* 965+ only */
a57c774ab2b849b Antti Koskipaa                2014-02-04   6307  #define _DSPATILEOFF				0x701A4 /* 965+ only */
a57c774ab2b849b Antti Koskipaa                2014-02-04   6308  #define _DSPAOFFSET				0x701A4 /* HSW */
a57c774ab2b849b Antti Koskipaa                2014-02-04   6309  #define _DSPASURFLIVE				0x701AC
94e15723df81549 Ville Syrjälä                 2019-07-03   6310  #define _DSPAGAMC				0x701E0
a57c774ab2b849b Antti Koskipaa                2014-02-04   6311  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6312  #define DSPCNTR(plane)		_MMIO_PIPE2(plane, _DSPACNTR)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6313  #define DSPADDR(plane)		_MMIO_PIPE2(plane, _DSPAADDR)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6314  #define DSPSTRIDE(plane)	_MMIO_PIPE2(plane, _DSPASTRIDE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6315  #define DSPPOS(plane)		_MMIO_PIPE2(plane, _DSPAPOS)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6316  #define DSPSIZE(plane)		_MMIO_PIPE2(plane, _DSPASIZE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6317  #define DSPSURF(plane)		_MMIO_PIPE2(plane, _DSPASURF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6318  #define DSPTILEOFF(plane)	_MMIO_PIPE2(plane, _DSPATILEOFF)
e506a0c6381f180 Daniel Vetter                 2012-07-05   6319  #define DSPLINOFF(plane)	DSPADDR(plane)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6320  #define DSPOFFSET(plane)	_MMIO_PIPE2(plane, _DSPAOFFSET)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6321  #define DSPSURFLIVE(plane)	_MMIO_PIPE2(plane, _DSPASURFLIVE)
94e15723df81549 Ville Syrjälä                 2019-07-03   6322  #define DSPGAMC(plane, i)	_MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   6323  
c14b048521ed341 Ville Syrjälä                 2014-10-16   6324  /* CHV pipe B blender and primary plane */
c14b048521ed341 Ville Syrjälä                 2014-10-16   6325  #define _CHV_BLEND_A		0x60a00
c14b048521ed341 Ville Syrjälä                 2014-10-16   6326  #define   CHV_BLEND_LEGACY		(0 << 30)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6327  #define   CHV_BLEND_ANDROID		(1 << 30)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6328  #define   CHV_BLEND_MPO			(2 << 30)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6329  #define   CHV_BLEND_MASK		(3 << 30)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6330  #define _CHV_CANVAS_A		0x60a04
c14b048521ed341 Ville Syrjälä                 2014-10-16   6331  #define _PRIMPOS_A		0x60a08
c14b048521ed341 Ville Syrjälä                 2014-10-16   6332  #define _PRIMSIZE_A		0x60a0c
c14b048521ed341 Ville Syrjälä                 2014-10-16   6333  #define _PRIMCNSTALPHA_A	0x60a10
c14b048521ed341 Ville Syrjälä                 2014-10-16   6334  #define   PRIM_CONST_ALPHA_ENABLE	(1 << 31)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6335  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6336  #define CHV_BLEND(pipe)		_MMIO_TRANS2(pipe, _CHV_BLEND_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6337  #define CHV_CANVAS(pipe)	_MMIO_TRANS2(pipe, _CHV_CANVAS_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6338  #define PRIMPOS(plane)		_MMIO_TRANS2(plane, _PRIMPOS_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6339  #define PRIMSIZE(plane)		_MMIO_TRANS2(plane, _PRIMSIZE_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6340  #define PRIMCNSTALPHA(plane)	_MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6341  
446f254566ea891 Armin Reese                   2012-03-30   6342  /* Display/Sprite base address macros */
446f254566ea891 Armin Reese                   2012-03-30   6343  #define DISP_BASEADDR_MASK	(0xfffff000)
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   6344  #define I915_LO_DISPBASE(val)	((val) & ~DISP_BASEADDR_MASK)
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   6345  #define I915_HI_DISPBASE(val)	((val) & DISP_BASEADDR_MASK)
446f254566ea891 Armin Reese                   2012-03-30   6346  
85fa792beee3425 Ville Syrjälä                 2015-09-18   6347  /*
85fa792beee3425 Ville Syrjälä                 2015-09-18   6348   * VBIOS flags
85fa792beee3425 Ville Syrjälä                 2015-09-18   6349   * gen2:
85fa792beee3425 Ville Syrjälä                 2015-09-18   6350   * [00:06] alm,mgm
85fa792beee3425 Ville Syrjälä                 2015-09-18   6351   * [10:16] all
85fa792beee3425 Ville Syrjälä                 2015-09-18   6352   * [30:32] alm,mgm
85fa792beee3425 Ville Syrjälä                 2015-09-18   6353   * gen3+:
85fa792beee3425 Ville Syrjälä                 2015-09-18   6354   * [00:0f] all
85fa792beee3425 Ville Syrjälä                 2015-09-18   6355   * [10:1f] all
85fa792beee3425 Ville Syrjälä                 2015-09-18   6356   * [30:32] all
85fa792beee3425 Ville Syrjälä                 2015-09-18   6357   */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6358  #define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6359  #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6360  #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6361  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
585fb111348f7cd Jesse Barnes                  2008-07-29   6362  
585fb111348f7cd Jesse Barnes                  2008-07-29   6363  /* Pipe B */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6364  #define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6365  #define _PIPEBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6366  #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
25a2e2d0f35e329 Ville Syrjälä                 2013-10-11   6367  #define _PIPEBFRAMEHIGH		0x71040
25a2e2d0f35e329 Ville Syrjälä                 2013-10-11   6368  #define _PIPEBFRAMEPIXEL	0x71044
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6369  #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6370  #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
9880b7a527ffbb5 Jesse Barnes                  2009-02-06   6371  
585fb111348f7cd Jesse Barnes                  2008-07-29   6372  
585fb111348f7cd Jesse Barnes                  2008-07-29   6373  /* Display B control */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6374  #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
585fb111348f7cd Jesse Barnes                  2008-07-29   6375  #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
585fb111348f7cd Jesse Barnes                  2008-07-29   6376  #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
585fb111348f7cd Jesse Barnes                  2008-07-29   6377  #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
585fb111348f7cd Jesse Barnes                  2008-07-29   6378  #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6379  #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6380  #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6381  #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6382  #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6383  #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6384  #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6385  #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
ed5eb1b78a88302 Jani Nikula                   2018-12-31   6386  #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
585fb111348f7cd Jesse Barnes                  2008-07-29   6387  
372610f3c81491d Madhav Chauhan                2018-10-15   6388  /* ICL DSI 0 and 1 */
372610f3c81491d Madhav Chauhan                2018-10-15   6389  #define _PIPEDSI0CONF		0x7b008
372610f3c81491d Madhav Chauhan                2018-10-15   6390  #define _PIPEDSI1CONF		0x7b808
372610f3c81491d Madhav Chauhan                2018-10-15   6391  
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6392  /* Sprite A control */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6393  #define _DVSACNTR		0x72180
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6394  #define   DVS_ENABLE		(1 << 31)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6395  #define   DVS_GAMMA_ENABLE	(1 << 30)
c8624ede3ed3b9f Ville Syrjälä                 2018-02-14   6396  #define   DVS_YUV_RANGE_CORRECTION_DISABLE	(1 << 27)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6397  #define   DVS_PIXFORMAT_MASK	(3 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6398  #define   DVS_FORMAT_YUV422	(0 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6399  #define   DVS_FORMAT_RGBX101010	(1 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6400  #define   DVS_FORMAT_RGBX888	(2 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6401  #define   DVS_FORMAT_RGBX161616	(3 << 25)
86d3efce2c37d3f Ville Syrjälä                 2013-01-18   6402  #define   DVS_PIPE_CSC_ENABLE   (1 << 24)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6403  #define   DVS_SOURCE_KEY	(1 << 22)
ab2f9df10dd955f Jesse Barnes                  2012-02-27   6404  #define   DVS_RGB_ORDER_XBGR	(1 << 20)
b0f5c0badc5b54c Ville Syrjälä                 2018-02-14   6405  #define   DVS_YUV_FORMAT_BT709	(1 << 18)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6406  #define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6407  #define   DVS_YUV_ORDER_YUYV	(0 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6408  #define   DVS_YUV_ORDER_UYVY	(1 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6409  #define   DVS_YUV_ORDER_YVYU	(2 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6410  #define   DVS_YUV_ORDER_VYUY	(3 << 16)
76eebda727c76b5 Ville Syrjälä                 2014-08-05   6411  #define   DVS_ROTATE_180	(1 << 15)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6412  #define   DVS_DEST_KEY		(1 << 2)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6413  #define   DVS_TRICKLE_FEED_DISABLE (1 << 14)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6414  #define   DVS_TILED		(1 << 10)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6415  #define _DVSALINOFF		0x72184
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6416  #define _DVSASTRIDE		0x72188
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6417  #define _DVSAPOS		0x7218c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6418  #define _DVSASIZE		0x72190
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6419  #define _DVSAKEYVAL		0x72194
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6420  #define _DVSAKEYMSK		0x72198
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6421  #define _DVSASURF		0x7219c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6422  #define _DVSAKEYMAXVAL		0x721a0
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6423  #define _DVSATILEOFF		0x721a4
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6424  #define _DVSASURFLIVE		0x721ac
94e15723df81549 Ville Syrjälä                 2019-07-03   6425  #define _DVSAGAMC_G4X		0x721e0 /* g4x */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6426  #define _DVSASCALE		0x72204
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6427  #define   DVS_SCALE_ENABLE	(1 << 31)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6428  #define   DVS_FILTER_MASK	(3 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6429  #define   DVS_FILTER_MEDIUM	(0 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6430  #define   DVS_FILTER_ENHANCING	(1 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6431  #define   DVS_FILTER_SOFTENING	(2 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6432  #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6433  #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
94e15723df81549 Ville Syrjälä                 2019-07-03   6434  #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
94e15723df81549 Ville Syrjälä                 2019-07-03   6435  #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6436  
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6437  #define _DVSBCNTR		0x73180
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6438  #define _DVSBLINOFF		0x73184
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6439  #define _DVSBSTRIDE		0x73188
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6440  #define _DVSBPOS		0x7318c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6441  #define _DVSBSIZE		0x73190
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6442  #define _DVSBKEYVAL		0x73194
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6443  #define _DVSBKEYMSK		0x73198
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6444  #define _DVSBSURF		0x7319c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6445  #define _DVSBKEYMAXVAL		0x731a0
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6446  #define _DVSBTILEOFF		0x731a4
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6447  #define _DVSBSURFLIVE		0x731ac
94e15723df81549 Ville Syrjälä                 2019-07-03   6448  #define _DVSBGAMC_G4X		0x731e0 /* g4x */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6449  #define _DVSBSCALE		0x73204
94e15723df81549 Ville Syrjälä                 2019-07-03   6450  #define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
94e15723df81549 Ville Syrjälä                 2019-07-03   6451  #define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6452  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6453  #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6454  #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6455  #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6456  #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6457  #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6458  #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6459  #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6460  #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6461  #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6462  #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6463  #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6464  #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
94e15723df81549 Ville Syrjälä                 2019-07-03   6465  #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
94e15723df81549 Ville Syrjälä                 2019-07-03   6466  #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
94e15723df81549 Ville Syrjälä                 2019-07-03   6467  #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6468  
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6469  #define _SPRA_CTL		0x70280
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6470  #define   SPRITE_ENABLE			(1 << 31)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6471  #define   SPRITE_GAMMA_ENABLE		(1 << 30)
c8624ede3ed3b9f Ville Syrjälä                 2018-02-14   6472  #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6473  #define   SPRITE_PIXFORMAT_MASK		(7 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6474  #define   SPRITE_FORMAT_YUV422		(0 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6475  #define   SPRITE_FORMAT_RGBX101010	(1 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6476  #define   SPRITE_FORMAT_RGBX888		(2 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6477  #define   SPRITE_FORMAT_RGBX161616	(3 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6478  #define   SPRITE_FORMAT_YUV444		(4 << 25)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6479  #define   SPRITE_FORMAT_XR_BGR101010	(5 << 25) /* Extended range */
86d3efce2c37d3f Ville Syrjälä                 2013-01-18   6480  #define   SPRITE_PIPE_CSC_ENABLE	(1 << 24)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6481  #define   SPRITE_SOURCE_KEY		(1 << 22)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6482  #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6483  #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
b0f5c0badc5b54c Ville Syrjälä                 2018-02-14   6484  #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6485  #define   SPRITE_YUV_BYTE_ORDER_MASK	(3 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6486  #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6487  #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6488  #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6489  #define   SPRITE_YUV_ORDER_VYUY		(3 << 16)
76eebda727c76b5 Ville Syrjälä                 2014-08-05   6490  #define   SPRITE_ROTATE_180		(1 << 15)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6491  #define   SPRITE_TRICKLE_FEED_DISABLE	(1 << 14)
423ee8e99aa5ee7 Ville Syrjälä                 2019-07-03   6492  #define   SPRITE_INT_GAMMA_DISABLE	(1 << 13)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6493  #define   SPRITE_TILED			(1 << 10)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6494  #define   SPRITE_DEST_KEY		(1 << 2)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6495  #define _SPRA_LINOFF		0x70284
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6496  #define _SPRA_STRIDE		0x70288
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6497  #define _SPRA_POS		0x7028c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6498  #define _SPRA_SIZE		0x70290
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6499  #define _SPRA_KEYVAL		0x70294
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6500  #define _SPRA_KEYMSK		0x70298
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6501  #define _SPRA_SURF		0x7029c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6502  #define _SPRA_KEYMAX		0x702a0
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6503  #define _SPRA_TILEOFF		0x702a4
c54173a85d4931b Damien Lespiau                2012-10-26   6504  #define _SPRA_OFFSET		0x702a4
32ae46bf010f2fc Ville Syrjälä                 2012-11-01   6505  #define _SPRA_SURFLIVE		0x702ac
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6506  #define _SPRA_SCALE		0x70304
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6507  #define   SPRITE_SCALE_ENABLE	(1 << 31)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6508  #define   SPRITE_FILTER_MASK	(3 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6509  #define   SPRITE_FILTER_MEDIUM	(0 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6510  #define   SPRITE_FILTER_ENHANCING	(1 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6511  #define   SPRITE_FILTER_SOFTENING	(2 << 29)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6512  #define   SPRITE_VERTICAL_OFFSET_HALF	(1 << 28) /* must be enabled below */
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6513  #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1 << 27)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6514  #define _SPRA_GAMC		0x70400
94e15723df81549 Ville Syrjälä                 2019-07-03   6515  #define _SPRA_GAMC16		0x70440
94e15723df81549 Ville Syrjälä                 2019-07-03   6516  #define _SPRA_GAMC17		0x7044c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6517  
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6518  #define _SPRB_CTL		0x71280
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6519  #define _SPRB_LINOFF		0x71284
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6520  #define _SPRB_STRIDE		0x71288
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6521  #define _SPRB_POS		0x7128c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6522  #define _SPRB_SIZE		0x71290
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6523  #define _SPRB_KEYVAL		0x71294
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6524  #define _SPRB_KEYMSK		0x71298
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6525  #define _SPRB_SURF		0x7129c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6526  #define _SPRB_KEYMAX		0x712a0
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6527  #define _SPRB_TILEOFF		0x712a4
c54173a85d4931b Damien Lespiau                2012-10-26   6528  #define _SPRB_OFFSET		0x712a4
32ae46bf010f2fc Ville Syrjälä                 2012-11-01   6529  #define _SPRB_SURFLIVE		0x712ac
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6530  #define _SPRB_SCALE		0x71304
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6531  #define _SPRB_GAMC		0x71400
94e15723df81549 Ville Syrjälä                 2019-07-03   6532  #define _SPRB_GAMC16		0x71440
94e15723df81549 Ville Syrjälä                 2019-07-03   6533  #define _SPRB_GAMC17		0x7144c
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6534  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6535  #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6536  #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6537  #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6538  #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6539  #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6540  #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6541  #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6542  #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6543  #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6544  #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6545  #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6546  #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
94e15723df81549 Ville Syrjälä                 2019-07-03   6547  #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
94e15723df81549 Ville Syrjälä                 2019-07-03   6548  #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
94e15723df81549 Ville Syrjälä                 2019-07-03   6549  #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6550  #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
b840d907fcf6d5d Jesse Barnes                  2011-12-13   6551  
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6552  #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6553  #define   SP_ENABLE			(1 << 31)
4ea67bc700c0c08 Ville Syrjälä                 2013-11-18   6554  #define   SP_GAMMA_ENABLE		(1 << 30)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6555  #define   SP_PIXFORMAT_MASK		(0xf << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6556  #define   SP_FORMAT_YUV422		(0 << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6557  #define   SP_FORMAT_BGR565		(5 << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6558  #define   SP_FORMAT_BGRX8888		(6 << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6559  #define   SP_FORMAT_BGRA8888		(7 << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6560  #define   SP_FORMAT_RGBX1010102		(8 << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6561  #define   SP_FORMAT_RGBA1010102		(9 << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6562  #define   SP_FORMAT_RGBX8888		(0xe << 26)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6563  #define   SP_FORMAT_RGBA8888		(0xf << 26)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6564  #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6565  #define   SP_SOURCE_KEY			(1 << 22)
b0f5c0badc5b54c Ville Syrjälä                 2018-02-14   6566  #define   SP_YUV_FORMAT_BT709		(1 << 18)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6567  #define   SP_YUV_BYTE_ORDER_MASK	(3 << 16)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6568  #define   SP_YUV_ORDER_YUYV		(0 << 16)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6569  #define   SP_YUV_ORDER_UYVY		(1 << 16)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6570  #define   SP_YUV_ORDER_YVYU		(2 << 16)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6571  #define   SP_YUV_ORDER_VYUY		(3 << 16)
76eebda727c76b5 Ville Syrjälä                 2014-08-05   6572  #define   SP_ROTATE_180			(1 << 15)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6573  #define   SP_TILED			(1 << 10)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6574  #define   SP_MIRROR			(1 << 8) /* CHV pipe B */
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6575  #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6576  #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6577  #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6578  #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6579  #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6580  #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6581  #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6582  #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6583  #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6584  #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
c14b048521ed341 Ville Syrjälä                 2014-10-16   6585  #define   SP_CONST_ALPHA_ENABLE		(1 << 31)
5deae9191130db6 Ville Syrjälä                 2018-02-14   6586  #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
5deae9191130db6 Ville Syrjälä                 2018-02-14   6587  #define   SP_CONTRAST(x)		((x) << 18) /* u3.6 */
5deae9191130db6 Ville Syrjälä                 2018-02-14   6588  #define   SP_BRIGHTNESS(x)		((x) & 0xff) /* s8 */
5deae9191130db6 Ville Syrjälä                 2018-02-14   6589  #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
5deae9191130db6 Ville Syrjälä                 2018-02-14   6590  #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
5deae9191130db6 Ville Syrjälä                 2018-02-14   6591  #define   SP_SH_COS(x)			(x) /* u3.7 */
94e15723df81549 Ville Syrjälä                 2019-07-03   6592  #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6593  
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6594  #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6595  #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6596  #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6597  #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6598  #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6599  #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6600  #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6601  #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6602  #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6603  #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
921c3b677bf6340 Ville Syrjälä                 2013-06-25   6604  #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
5deae9191130db6 Ville Syrjälä                 2018-02-14   6605  #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
5deae9191130db6 Ville Syrjälä                 2018-02-14   6606  #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
94e15723df81549 Ville Syrjälä                 2019-07-03   6607  #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6608  
94e15723df81549 Ville Syrjälä                 2019-07-03   6609  #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
94e15723df81549 Ville Syrjälä                 2019-07-03   6610  	_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
83c04a62a187283 Ville Syrjälä                 2016-11-22   6611  #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
94e15723df81549 Ville Syrjälä                 2019-07-03   6612  	_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
83c04a62a187283 Ville Syrjälä                 2016-11-22   6613  
83c04a62a187283 Ville Syrjälä                 2016-11-22   6614  #define SPCNTR(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6615  #define SPLINOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6616  #define SPSTRIDE(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6617  #define SPPOS(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6618  #define SPSIZE(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6619  #define SPKEYMINVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6620  #define SPKEYMSK(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6621  #define SPSURF(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6622  #define SPKEYMAXVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6623  #define SPTILEOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6624  #define SPCONSTALPHA(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
5deae9191130db6 Ville Syrjälä                 2018-02-14   6625  #define SPCLRC0(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
5deae9191130db6 Ville Syrjälä                 2018-02-14   6626  #define SPCLRC1(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
94e15723df81549 Ville Syrjälä                 2019-07-03   6627  #define SPGAMC(pipe, plane_id, i)	_MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
7f1f3851feb0b2d Jesse Barnes                  2013-04-02   6628  
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6629  /*
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6630   * CHV pipe B sprite CSC
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6631   *
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6632   * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6633   * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6634   * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6635   */
83c04a62a187283 Ville Syrjälä                 2016-11-22   6636  #define _MMIO_CHV_SPCSC(plane_id, reg) \
83c04a62a187283 Ville Syrjälä                 2016-11-22   6637  	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
83c04a62a187283 Ville Syrjälä                 2016-11-22   6638  
83c04a62a187283 Ville Syrjälä                 2016-11-22   6639  #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6640  #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6641  #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6642  #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6643  #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6644  
83c04a62a187283 Ville Syrjälä                 2016-11-22   6645  #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6646  #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6647  #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6648  #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6649  #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6650  #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6651  #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6652  
83c04a62a187283 Ville Syrjälä                 2016-11-22   6653  #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6654  #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6655  #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6656  #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6657  #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6658  
83c04a62a187283 Ville Syrjälä                 2016-11-22   6659  #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6660  #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
83c04a62a187283 Ville Syrjälä                 2016-11-22   6661  #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6662  #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6663  #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
6ca2aeb27b4a845 Ville Syrjälä                 2014-10-20   6664  
70d21f0e914415c Damien Lespiau                2013-07-03   6665  /* Skylake plane registers */
70d21f0e914415c Damien Lespiau                2013-07-03   6666  
70d21f0e914415c Damien Lespiau                2013-07-03   6667  #define _PLANE_CTL_1_A				0x70180
70d21f0e914415c Damien Lespiau                2013-07-03   6668  #define _PLANE_CTL_2_A				0x70280
70d21f0e914415c Damien Lespiau                2013-07-03   6669  #define _PLANE_CTL_3_A				0x70380
70d21f0e914415c Damien Lespiau                2013-07-03   6670  #define   PLANE_CTL_ENABLE			(1 << 31)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6671  #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */
c8624ede3ed3b9f Ville Syrjälä                 2018-02-14   6672  #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
b597277643fef8f James Ausmus                  2018-01-30   6673  /*
b597277643fef8f James Ausmus                  2018-01-30   6674   * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
b597277643fef8f James Ausmus                  2018-01-30   6675   * expanded to include bit 23 as well. However, the shift-24 based values
b597277643fef8f James Ausmus                  2018-01-30   6676   * correctly map to the same formats in ICL, as long as bit 23 is set to 0
b597277643fef8f James Ausmus                  2018-01-30   6677   */
70d21f0e914415c Damien Lespiau                2013-07-03   6678  #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6679  #define   PLANE_CTL_FORMAT_YUV422		(0 << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6680  #define   PLANE_CTL_FORMAT_NV12			(1 << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6681  #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
e13122115525c21 Juha-Pekka Heikkila           2019-03-04   6682  #define   PLANE_CTL_FORMAT_P010			(3 << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6683  #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
e13122115525c21 Juha-Pekka Heikkila           2019-03-04   6684  #define   PLANE_CTL_FORMAT_P012			(5 << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6685  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
e13122115525c21 Juha-Pekka Heikkila           2019-03-04   6686  #define   PLANE_CTL_FORMAT_P016			(7 << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6687  #define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6688  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
70d21f0e914415c Damien Lespiau                2013-07-03   6689  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
b597277643fef8f James Ausmus                  2018-01-30   6690  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6691  #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
696fa001524a27f Swati Sharma                  2019-03-04   6692  #define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
696fa001524a27f Swati Sharma                  2019-03-04   6693  #define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
696fa001524a27f Swati Sharma                  2019-03-04   6694  #define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
696fa001524a27f Swati Sharma                  2019-03-04   6695  #define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
696fa001524a27f Swati Sharma                  2019-03-04   6696  #define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
696fa001524a27f Swati Sharma                  2019-03-04   6697  #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6698  #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6699  #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6700  #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
70d21f0e914415c Damien Lespiau                2013-07-03   6701  #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
70d21f0e914415c Damien Lespiau                2013-07-03   6702  #define   PLANE_CTL_ORDER_RGBX			(1 << 20)
1e364f9008a7cdf Maarten Lankhorst             2018-10-18   6703  #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
b0f5c0badc5b54c Ville Syrjälä                 2018-02-14   6704  #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
70d21f0e914415c Damien Lespiau                2013-07-03   6705  #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
70d21f0e914415c Damien Lespiau                2013-07-03   6706  #define   PLANE_CTL_YUV422_YUYV			(0 << 16)
70d21f0e914415c Damien Lespiau                2013-07-03   6707  #define   PLANE_CTL_YUV422_UYVY			(1 << 16)
70d21f0e914415c Damien Lespiau                2013-07-03   6708  #define   PLANE_CTL_YUV422_YVYU			(2 << 16)
70d21f0e914415c Damien Lespiau                2013-07-03   6709  #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
53867b46fa84437 Dhinakaran Pandiyan           2018-08-21   6710  #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
70d21f0e914415c Damien Lespiau                2013-07-03   6711  #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6712  #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
70d21f0e914415c Damien Lespiau                2013-07-03   6713  #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
70d21f0e914415c Damien Lespiau                2013-07-03   6714  #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
70d21f0e914415c Damien Lespiau                2013-07-03   6715  #define   PLANE_CTL_TILED_X			(1 << 10)
70d21f0e914415c Damien Lespiau                2013-07-03   6716  #define   PLANE_CTL_TILED_Y			(4 << 10)
70d21f0e914415c Damien Lespiau                2013-07-03   6717  #define   PLANE_CTL_TILED_YF			(5 << 10)
5f8e3f57acf9f28 Joonas Lahtinen               2017-12-15   6718  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6719  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
70d21f0e914415c Damien Lespiau                2013-07-03   6720  #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
70d21f0e914415c Damien Lespiau                2013-07-03   6721  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
70d21f0e914415c Damien Lespiau                2013-07-03   6722  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(3 << 4)
1447dde094c1ebe Sonika Jindal                 2014-10-04   6723  #define   PLANE_CTL_ROTATE_MASK			0x3
1447dde094c1ebe Sonika Jindal                 2014-10-04   6724  #define   PLANE_CTL_ROTATE_0			0x0
3b7a5119b5d2def Sonika Jindal                 2015-04-10   6725  #define   PLANE_CTL_ROTATE_90			0x1
1447dde094c1ebe Sonika Jindal                 2014-10-04   6726  #define   PLANE_CTL_ROTATE_180			0x2
3b7a5119b5d2def Sonika Jindal                 2015-04-10   6727  #define   PLANE_CTL_ROTATE_270			0x3
70d21f0e914415c Damien Lespiau                2013-07-03   6728  #define _PLANE_STRIDE_1_A			0x70188
70d21f0e914415c Damien Lespiau                2013-07-03   6729  #define _PLANE_STRIDE_2_A			0x70288
70d21f0e914415c Damien Lespiau                2013-07-03   6730  #define _PLANE_STRIDE_3_A			0x70388
70d21f0e914415c Damien Lespiau                2013-07-03   6731  #define _PLANE_POS_1_A				0x7018c
70d21f0e914415c Damien Lespiau                2013-07-03   6732  #define _PLANE_POS_2_A				0x7028c
70d21f0e914415c Damien Lespiau                2013-07-03   6733  #define _PLANE_POS_3_A				0x7038c
70d21f0e914415c Damien Lespiau                2013-07-03   6734  #define _PLANE_SIZE_1_A				0x70190
70d21f0e914415c Damien Lespiau                2013-07-03   6735  #define _PLANE_SIZE_2_A				0x70290
70d21f0e914415c Damien Lespiau                2013-07-03   6736  #define _PLANE_SIZE_3_A				0x70390
70d21f0e914415c Damien Lespiau                2013-07-03   6737  #define _PLANE_SURF_1_A				0x7019c
70d21f0e914415c Damien Lespiau                2013-07-03   6738  #define _PLANE_SURF_2_A				0x7029c
70d21f0e914415c Damien Lespiau                2013-07-03   6739  #define _PLANE_SURF_3_A				0x7039c
70d21f0e914415c Damien Lespiau                2013-07-03   6740  #define _PLANE_OFFSET_1_A			0x701a4
70d21f0e914415c Damien Lespiau                2013-07-03   6741  #define _PLANE_OFFSET_2_A			0x702a4
70d21f0e914415c Damien Lespiau                2013-07-03   6742  #define _PLANE_OFFSET_3_A			0x703a4
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6743  #define _PLANE_KEYVAL_1_A			0x70194
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6744  #define _PLANE_KEYVAL_2_A			0x70294
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6745  #define _PLANE_KEYMSK_1_A			0x70198
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6746  #define _PLANE_KEYMSK_2_A			0x70298
b20815255693733 Maarten Lankhorst             2018-08-15   6747  #define  PLANE_KEYMSK_ALPHA_ENABLE		(1 << 31)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6748  #define _PLANE_KEYMAX_1_A			0x701a0
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6749  #define _PLANE_KEYMAX_2_A			0x702a0
7b012bd62db9513 Ville Syrjälä                 2018-11-07   6750  #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6751  #define _PLANE_AUX_DIST_1_A			0x701c0
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6752  #define _PLANE_AUX_DIST_2_A			0x702c0
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6753  #define _PLANE_AUX_OFFSET_1_A			0x701c4
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6754  #define _PLANE_AUX_OFFSET_2_A			0x702c4
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6755  #define _PLANE_CUS_CTL_1_A			0x701c8
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6756  #define _PLANE_CUS_CTL_2_A			0x702c8
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6757  #define  PLANE_CUS_ENABLE			(1 << 31)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6758  #define  PLANE_CUS_PLANE_6			(0 << 30)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6759  #define  PLANE_CUS_PLANE_7			(1 << 30)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6760  #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE		(1 << 19)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6761  #define  PLANE_CUS_HPHASE_0			(0 << 16)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6762  #define  PLANE_CUS_HPHASE_0_25			(1 << 16)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6763  #define  PLANE_CUS_HPHASE_0_5			(2 << 16)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6764  #define  PLANE_CUS_VPHASE_SIGN_NEGATIVE		(1 << 15)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6765  #define  PLANE_CUS_VPHASE_0			(0 << 12)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6766  #define  PLANE_CUS_VPHASE_0_25			(1 << 12)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6767  #define  PLANE_CUS_VPHASE_0_5			(2 << 12)
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6768  #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6769  #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6770  #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
077ef1f09c2528b James Ausmus                  2018-03-28   6771  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
c8624ede3ed3b9f Ville Syrjälä                 2018-02-14   6772  #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6a255da783c6488 Uma Shankar                   2018-11-02   6773  #define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
077ef1f09c2528b James Ausmus                  2018-03-28   6774  #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
38f24f21ae9bb0f Ville Syrjälä                 2018-02-14   6775  #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
38f24f21ae9bb0f Ville Syrjälä                 2018-02-14   6776  #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709		(1 << 17)
38f24f21ae9bb0f Ville Syrjälä                 2018-02-14   6777  #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709		(2 << 17)
38f24f21ae9bb0f Ville Syrjälä                 2018-02-14   6778  #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020	(3 << 17)
38f24f21ae9bb0f Ville Syrjälä                 2018-02-14   6779  #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020	(4 << 17)
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6780  #define   PLANE_COLOR_PLANE_GAMMA_DISABLE	(1 << 13)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6781  #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6782  #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6783  #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY	(2 << 4)
4036c78ccf6bf41 James Ausmus                  2017-11-13   6784  #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY	(3 << 4)
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6785  #define _PLANE_BUF_CFG_1_A			0x7027c
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6786  #define _PLANE_BUF_CFG_2_A			0x7037c
2cd601c620ccf7b Chandra Konduru               2015-04-27   6787  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
2cd601c620ccf7b Chandra Konduru               2015-04-27   6788  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
70d21f0e914415c Damien Lespiau                2013-07-03   6789  
6a255da783c6488 Uma Shankar                   2018-11-02   6790  /* Input CSC Register Definitions */
6a255da783c6488 Uma Shankar                   2018-11-02   6791  #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
6a255da783c6488 Uma Shankar                   2018-11-02   6792  #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
6a255da783c6488 Uma Shankar                   2018-11-02   6793  
6a255da783c6488 Uma Shankar                   2018-11-02   6794  #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
6a255da783c6488 Uma Shankar                   2018-11-02   6795  #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
6a255da783c6488 Uma Shankar                   2018-11-02   6796  
6a255da783c6488 Uma Shankar                   2018-11-02   6797  #define _PLANE_INPUT_CSC_RY_GY_1(pipe)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6798  	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6a255da783c6488 Uma Shankar                   2018-11-02   6799  	     _PLANE_INPUT_CSC_RY_GY_1_B)
6a255da783c6488 Uma Shankar                   2018-11-02   6800  #define _PLANE_INPUT_CSC_RY_GY_2(pipe)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6801  	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6a255da783c6488 Uma Shankar                   2018-11-02   6802  	     _PLANE_INPUT_CSC_RY_GY_2_B)
6a255da783c6488 Uma Shankar                   2018-11-02   6803  
6a255da783c6488 Uma Shankar                   2018-11-02   6804  #define PLANE_INPUT_CSC_COEFF(pipe, plane, index)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6805  	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
6a255da783c6488 Uma Shankar                   2018-11-02   6806  		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6a255da783c6488 Uma Shankar                   2018-11-02   6807  
6a255da783c6488 Uma Shankar                   2018-11-02   6808  #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
6a255da783c6488 Uma Shankar                   2018-11-02   6809  #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
6a255da783c6488 Uma Shankar                   2018-11-02   6810  
6a255da783c6488 Uma Shankar                   2018-11-02   6811  #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
6a255da783c6488 Uma Shankar                   2018-11-02   6812  #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
6a255da783c6488 Uma Shankar                   2018-11-02   6813  
6a255da783c6488 Uma Shankar                   2018-11-02   6814  #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6815  	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6a255da783c6488 Uma Shankar                   2018-11-02   6816  	     _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6a255da783c6488 Uma Shankar                   2018-11-02   6817  #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6818  	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6a255da783c6488 Uma Shankar                   2018-11-02   6819  	     _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6a255da783c6488 Uma Shankar                   2018-11-02   6820  #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6821  	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6a255da783c6488 Uma Shankar                   2018-11-02   6822  		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6a255da783c6488 Uma Shankar                   2018-11-02   6823  
6a255da783c6488 Uma Shankar                   2018-11-02   6824  #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
6a255da783c6488 Uma Shankar                   2018-11-02   6825  #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
6a255da783c6488 Uma Shankar                   2018-11-02   6826  
6a255da783c6488 Uma Shankar                   2018-11-02   6827  #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
6a255da783c6488 Uma Shankar                   2018-11-02   6828  #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
6a255da783c6488 Uma Shankar                   2018-11-02   6829  
6a255da783c6488 Uma Shankar                   2018-11-02   6830  #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6831  	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6a255da783c6488 Uma Shankar                   2018-11-02   6832  	     _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6a255da783c6488 Uma Shankar                   2018-11-02   6833  #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6834  	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6a255da783c6488 Uma Shankar                   2018-11-02   6835  	     _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6a255da783c6488 Uma Shankar                   2018-11-02   6836  #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)	\
6a255da783c6488 Uma Shankar                   2018-11-02   6837  	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6a255da783c6488 Uma Shankar                   2018-11-02   6838  		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6839  
70d21f0e914415c Damien Lespiau                2013-07-03   6840  #define _PLANE_CTL_1_B				0x71180
70d21f0e914415c Damien Lespiau                2013-07-03   6841  #define _PLANE_CTL_2_B				0x71280
70d21f0e914415c Damien Lespiau                2013-07-03   6842  #define _PLANE_CTL_3_B				0x71380
70d21f0e914415c Damien Lespiau                2013-07-03   6843  #define _PLANE_CTL_1(pipe)	_PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6844  #define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6845  #define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6846  #define PLANE_CTL(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6847  	_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
70d21f0e914415c Damien Lespiau                2013-07-03   6848  
70d21f0e914415c Damien Lespiau                2013-07-03   6849  #define _PLANE_STRIDE_1_B			0x71188
70d21f0e914415c Damien Lespiau                2013-07-03   6850  #define _PLANE_STRIDE_2_B			0x71288
70d21f0e914415c Damien Lespiau                2013-07-03   6851  #define _PLANE_STRIDE_3_B			0x71388
70d21f0e914415c Damien Lespiau                2013-07-03   6852  #define _PLANE_STRIDE_1(pipe)	\
70d21f0e914415c Damien Lespiau                2013-07-03   6853  	_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6854  #define _PLANE_STRIDE_2(pipe)	\
70d21f0e914415c Damien Lespiau                2013-07-03   6855  	_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6856  #define _PLANE_STRIDE_3(pipe)	\
70d21f0e914415c Damien Lespiau                2013-07-03   6857  	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6858  #define PLANE_STRIDE(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6859  	_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
70d21f0e914415c Damien Lespiau                2013-07-03   6860  
70d21f0e914415c Damien Lespiau                2013-07-03   6861  #define _PLANE_POS_1_B				0x7118c
70d21f0e914415c Damien Lespiau                2013-07-03   6862  #define _PLANE_POS_2_B				0x7128c
70d21f0e914415c Damien Lespiau                2013-07-03   6863  #define _PLANE_POS_3_B				0x7138c
70d21f0e914415c Damien Lespiau                2013-07-03   6864  #define _PLANE_POS_1(pipe)	_PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6865  #define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6866  #define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6867  #define PLANE_POS(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6868  	_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
70d21f0e914415c Damien Lespiau                2013-07-03   6869  
70d21f0e914415c Damien Lespiau                2013-07-03   6870  #define _PLANE_SIZE_1_B				0x71190
70d21f0e914415c Damien Lespiau                2013-07-03   6871  #define _PLANE_SIZE_2_B				0x71290
70d21f0e914415c Damien Lespiau                2013-07-03   6872  #define _PLANE_SIZE_3_B				0x71390
70d21f0e914415c Damien Lespiau                2013-07-03   6873  #define _PLANE_SIZE_1(pipe)	_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6874  #define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6875  #define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6876  #define PLANE_SIZE(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6877  	_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
70d21f0e914415c Damien Lespiau                2013-07-03   6878  
70d21f0e914415c Damien Lespiau                2013-07-03   6879  #define _PLANE_SURF_1_B				0x7119c
70d21f0e914415c Damien Lespiau                2013-07-03   6880  #define _PLANE_SURF_2_B				0x7129c
70d21f0e914415c Damien Lespiau                2013-07-03   6881  #define _PLANE_SURF_3_B				0x7139c
70d21f0e914415c Damien Lespiau                2013-07-03   6882  #define _PLANE_SURF_1(pipe)	_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6883  #define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6884  #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6885  #define PLANE_SURF(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6886  	_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
70d21f0e914415c Damien Lespiau                2013-07-03   6887  
70d21f0e914415c Damien Lespiau                2013-07-03   6888  #define _PLANE_OFFSET_1_B			0x711a4
70d21f0e914415c Damien Lespiau                2013-07-03   6889  #define _PLANE_OFFSET_2_B			0x712a4
70d21f0e914415c Damien Lespiau                2013-07-03   6890  #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6891  #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
70d21f0e914415c Damien Lespiau                2013-07-03   6892  #define PLANE_OFFSET(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6893  	_MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
70d21f0e914415c Damien Lespiau                2013-07-03   6894  
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6895  #define _PLANE_KEYVAL_1_B			0x71194
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6896  #define _PLANE_KEYVAL_2_B			0x71294
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6897  #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6898  #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6899  #define PLANE_KEYVAL(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6900  	_MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6901  
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6902  #define _PLANE_KEYMSK_1_B			0x71198
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6903  #define _PLANE_KEYMSK_2_B			0x71298
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6904  #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6905  #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6906  #define PLANE_KEYMSK(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6907  	_MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6908  
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6909  #define _PLANE_KEYMAX_1_B			0x711a0
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6910  #define _PLANE_KEYMAX_2_B			0x712a0
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6911  #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6912  #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6913  #define PLANE_KEYMAX(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6914  	_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
dc2a41b4cd2b544 Damien Lespiau                2013-12-04   6915  
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6916  #define _PLANE_BUF_CFG_1_B			0x7127c
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6917  #define _PLANE_BUF_CFG_2_B			0x7137c
d7e449a858ec280 Ville Syrjälä                 2019-02-05   6918  #define  DDB_ENTRY_MASK				0x7FF /* skl+: 10 bits, icl+ 11 bits */
37cde11ba720cc4 Mahesh Kumar                  2018-04-26   6919  #define  DDB_ENTRY_END_SHIFT			16
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6920  #define _PLANE_BUF_CFG_1(pipe)	\
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6921  	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6922  #define _PLANE_BUF_CFG_2(pipe)	\
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6923  	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6924  #define PLANE_BUF_CFG(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6925  	_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6926  
2cd601c620ccf7b Chandra Konduru               2015-04-27   6927  #define _PLANE_NV12_BUF_CFG_1_B		0x71278
2cd601c620ccf7b Chandra Konduru               2015-04-27   6928  #define _PLANE_NV12_BUF_CFG_2_B		0x71378
2cd601c620ccf7b Chandra Konduru               2015-04-27   6929  #define _PLANE_NV12_BUF_CFG_1(pipe)	\
2cd601c620ccf7b Chandra Konduru               2015-04-27   6930  	_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
2cd601c620ccf7b Chandra Konduru               2015-04-27   6931  #define _PLANE_NV12_BUF_CFG_2(pipe)	\
2cd601c620ccf7b Chandra Konduru               2015-04-27   6932  	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
2cd601c620ccf7b Chandra Konduru               2015-04-27   6933  #define PLANE_NV12_BUF_CFG(pipe, plane)	\
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6934  	_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
2cd601c620ccf7b Chandra Konduru               2015-04-27   6935  
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6936  #define _PLANE_AUX_DIST_1_B		0x711c0
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6937  #define _PLANE_AUX_DIST_2_B		0x712c0
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6938  #define _PLANE_AUX_DIST_1(pipe) \
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6939  			_PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6940  #define _PLANE_AUX_DIST_2(pipe) \
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6941  			_PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6942  #define PLANE_AUX_DIST(pipe, plane)     \
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6943  	_MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6944  
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6945  #define _PLANE_AUX_OFFSET_1_B		0x711c4
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6946  #define _PLANE_AUX_OFFSET_2_B		0x712c4
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6947  #define _PLANE_AUX_OFFSET_1(pipe)       \
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6948  		_PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6949  #define _PLANE_AUX_OFFSET_2(pipe)       \
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6950  		_PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6951  #define PLANE_AUX_OFFSET(pipe, plane)   \
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6952  	_MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
2e2adb05736c310 Ville Syrjälä                 2017-08-01   6953  
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6954  #define _PLANE_CUS_CTL_1_B		0x711c8
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6955  #define _PLANE_CUS_CTL_2_B		0x712c8
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6956  #define _PLANE_CUS_CTL_1(pipe)       \
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6957  		_PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6958  #define _PLANE_CUS_CTL_2(pipe)       \
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6959  		_PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6960  #define PLANE_CUS_CTL(pipe, plane)   \
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6961  	_MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
cb2458baf8b55c3 Maarten Lankhorst             2018-10-18   6962  
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6963  #define _PLANE_COLOR_CTL_1_B			0x711CC
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6964  #define _PLANE_COLOR_CTL_2_B			0x712CC
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6965  #define _PLANE_COLOR_CTL_3_B			0x713CC
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6966  #define _PLANE_COLOR_CTL_1(pipe)	\
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6967  	_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6968  #define _PLANE_COLOR_CTL_2(pipe)	\
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6969  	_PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6970  #define PLANE_COLOR_CTL(pipe, plane)	\
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6971  	_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6972  
47f9ea8b9143890 Ander Conselvan de Oliveira   2017-01-26   6973  #/* SKL new cursor registers */
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6974  #define _CUR_BUF_CFG_A				0x7017c
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6975  #define _CUR_BUF_CFG_B				0x7117c
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6976  #define CUR_BUF_CFG(pipe)	_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
8211bd5bdf5e1cf Damien Lespiau                2014-11-04   6977  
585fb111348f7cd Jesse Barnes                  2008-07-29   6978  /* VBIOS regs */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6979  #define VGACNTRL		_MMIO(0x71400)
585fb111348f7cd Jesse Barnes                  2008-07-29   6980  # define VGA_DISP_DISABLE			(1 << 31)
585fb111348f7cd Jesse Barnes                  2008-07-29   6981  # define VGA_2X_MODE				(1 << 30)
585fb111348f7cd Jesse Barnes                  2008-07-29   6982  # define VGA_PIPE_B_SELECT			(1 << 29)
585fb111348f7cd Jesse Barnes                  2008-07-29   6983  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6984  #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
766aa1c42362eaf Ville Syrjälä                 2013-01-25   6985  
f2b115e69d46344 Adam Jackson                  2009-12-03   6986  /* Ironlake */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   6987  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6988  #define CPU_VGACNTRL	_MMIO(0x41000)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   6989  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   6990  #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   6991  #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6992  #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6993  #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6994  #define  DIGITAL_PORTA_PULSE_DURATION_6ms	(2 << 2) /* pre-HSW */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6995  #define  DIGITAL_PORTA_PULSE_DURATION_100ms	(3 << 2) /* pre-HSW */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6996  #define  DIGITAL_PORTA_PULSE_DURATION_MASK	(3 << 2) /* pre-HSW */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6997  #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6998  #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   6999  #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7000  #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7001  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7002  /* refresh rate hardware control */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7003  #define RR_HW_CTL       _MMIO(0x45300)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7004  #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7005  #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7006  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7007  #define FDI_PLL_BIOS_0  _MMIO(0x46000)
021357acc8ea852 Chris Wilson                  2010-09-07   7008  #define  FDI_PLL_FB_CLOCK_MASK  0xff
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7009  #define FDI_PLL_BIOS_1  _MMIO(0x46004)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7010  #define FDI_PLL_BIOS_2  _MMIO(0x46008)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7011  #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7012  #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7013  #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7014  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7015  #define PCH_3DCGDIS0		_MMIO(0x46020)
8956c8bba5b11b3 Eric Anholt                   2010-03-18   7016  # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
8956c8bba5b11b3 Eric Anholt                   2010-03-18   7017  # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
8956c8bba5b11b3 Eric Anholt                   2010-03-18   7018  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7019  #define PCH_3DCGDIS1		_MMIO(0x46024)
06f37751af77192 Eric Anholt                   2010-12-14   7020  # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
06f37751af77192 Eric Anholt                   2010-12-14   7021  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7022  #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7023  #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1 << 24)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7024  #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7025  #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7026  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7027  
a57c774ab2b849b Antti Koskipaa                2014-02-04   7028  #define _PIPEA_DATA_M1		0x60030
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7029  #define  PIPE_DATA_M1_OFFSET    0
a57c774ab2b849b Antti Koskipaa                2014-02-04   7030  #define _PIPEA_DATA_N1		0x60034
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7031  #define  PIPE_DATA_N1_OFFSET    0
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7032  
a57c774ab2b849b Antti Koskipaa                2014-02-04   7033  #define _PIPEA_DATA_M2		0x60038
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7034  #define  PIPE_DATA_M2_OFFSET    0
a57c774ab2b849b Antti Koskipaa                2014-02-04   7035  #define _PIPEA_DATA_N2		0x6003c
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7036  #define  PIPE_DATA_N2_OFFSET    0
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7037  
a57c774ab2b849b Antti Koskipaa                2014-02-04   7038  #define _PIPEA_LINK_M1		0x60040
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7039  #define  PIPE_LINK_M1_OFFSET    0
a57c774ab2b849b Antti Koskipaa                2014-02-04   7040  #define _PIPEA_LINK_N1		0x60044
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7041  #define  PIPE_LINK_N1_OFFSET    0
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7042  
a57c774ab2b849b Antti Koskipaa                2014-02-04   7043  #define _PIPEA_LINK_M2		0x60048
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7044  #define  PIPE_LINK_M2_OFFSET    0
a57c774ab2b849b Antti Koskipaa                2014-02-04   7045  #define _PIPEA_LINK_N2		0x6004c
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   7046  #define  PIPE_LINK_N2_OFFSET    0
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7047  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7048  /* PIPEB timing regs are same start from 0x61000 */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7049  
a57c774ab2b849b Antti Koskipaa                2014-02-04   7050  #define _PIPEB_DATA_M1		0x61030
a57c774ab2b849b Antti Koskipaa                2014-02-04   7051  #define _PIPEB_DATA_N1		0x61034
a57c774ab2b849b Antti Koskipaa                2014-02-04   7052  #define _PIPEB_DATA_M2		0x61038
a57c774ab2b849b Antti Koskipaa                2014-02-04   7053  #define _PIPEB_DATA_N2		0x6103c
a57c774ab2b849b Antti Koskipaa                2014-02-04   7054  #define _PIPEB_LINK_M1		0x61040
a57c774ab2b849b Antti Koskipaa                2014-02-04   7055  #define _PIPEB_LINK_N1		0x61044
a57c774ab2b849b Antti Koskipaa                2014-02-04   7056  #define _PIPEB_LINK_M2		0x61048
a57c774ab2b849b Antti Koskipaa                2014-02-04   7057  #define _PIPEB_LINK_N2		0x6104c
a57c774ab2b849b Antti Koskipaa                2014-02-04   7058  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7059  #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7060  #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7061  #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7062  #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7063  #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7064  #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7065  #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7066  #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7067  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7068  /* CPU panel fitter */
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7069  /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7070  #define _PFA_CTL_1               0x68080
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7071  #define _PFB_CTL_1               0x68880
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7072  #define  PF_ENABLE              (1 << 31)
13888d78c664a1f Paulo Zanoni                  2012-11-20   7073  #define  PF_PIPE_SEL_MASK_IVB	(3 << 29)
13888d78c664a1f Paulo Zanoni                  2012-11-20   7074  #define  PF_PIPE_SEL_IVB(pipe)	((pipe) << 29)
b1f60b7029989da Zhenyu Wang                   2009-10-19   7075  #define  PF_FILTER_MASK		(3 << 23)
b1f60b7029989da Zhenyu Wang                   2009-10-19   7076  #define  PF_FILTER_PROGRAMMED	(0 << 23)
b1f60b7029989da Zhenyu Wang                   2009-10-19   7077  #define  PF_FILTER_MED_3x3	(1 << 23)
b1f60b7029989da Zhenyu Wang                   2009-10-19   7078  #define  PF_FILTER_EDGE_ENHANCE	(2 << 23)
b1f60b7029989da Zhenyu Wang                   2009-10-19   7079  #define  PF_FILTER_EDGE_SOFTEN	(3 << 23)
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7080  #define _PFA_WIN_SZ		0x68074
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7081  #define _PFB_WIN_SZ		0x68874
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7082  #define _PFA_WIN_POS		0x68070
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7083  #define _PFB_WIN_POS		0x68870
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7084  #define _PFA_VSCALE		0x68084
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7085  #define _PFB_VSCALE		0x68884
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7086  #define _PFA_HSCALE		0x68090
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7087  #define _PFB_HSCALE		0x68890
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7088  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7089  #define PF_CTL(pipe)		_MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7090  #define PF_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7091  #define PF_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7092  #define PF_VSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7093  #define PF_HSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7094  
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7095  #define _PSA_CTL		0x68180
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7096  #define _PSB_CTL		0x68980
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7097  #define PS_ENABLE		(1 << 31)
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7098  #define _PSA_WIN_SZ		0x68174
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7099  #define _PSB_WIN_SZ		0x68974
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7100  #define _PSA_WIN_POS		0x68170
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7101  #define _PSB_WIN_POS		0x68970
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7102  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7103  #define PS_CTL(pipe)		_MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7104  #define PS_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7105  #define PS_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
bd2e244f847d8e8 Jesse Barnes                  2014-11-13   7106  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7107  /*
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7108   * Skylake scalers
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7109   */
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7110  #define _PS_1A_CTRL      0x68180
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7111  #define _PS_2A_CTRL      0x68280
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7112  #define _PS_1B_CTRL      0x68980
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7113  #define _PS_2B_CTRL      0x68A80
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7114  #define _PS_1C_CTRL      0x69180
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7115  #define PS_SCALER_EN        (1 << 31)
0aaf29b35f93f68 Maarten Lankhorst             2018-09-21   7116  #define SKL_PS_SCALER_MODE_MASK (3 << 28)
0aaf29b35f93f68 Maarten Lankhorst             2018-09-21   7117  #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
0aaf29b35f93f68 Maarten Lankhorst             2018-09-21   7118  #define SKL_PS_SCALER_MODE_HQ  (1 << 28)
e6e1948c9fabe1a Chandra Konduru               2018-04-09   7119  #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
e6e1948c9fabe1a Chandra Konduru               2018-04-09   7120  #define PS_SCALER_MODE_PLANAR (1 << 29)
b1554e23ccb6d8e Maarten Lankhorst             2018-10-18   7121  #define PS_SCALER_MODE_NORMAL (0 << 29)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7122  #define PS_PLANE_SEL_MASK  (7 << 25)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   7123  #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7124  #define PS_FILTER_MASK         (3 << 23)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7125  #define PS_FILTER_MEDIUM       (0 << 23)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7126  #define PS_FILTER_EDGE_ENHANCE (2 << 23)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7127  #define PS_FILTER_BILINEAR     (3 << 23)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7128  #define PS_VERT3TAP            (1 << 21)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7129  #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7130  #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7131  #define PS_PWRUP_PROGRESS         (1 << 17)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7132  #define PS_V_FILTER_BYPASS        (1 << 8)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7133  #define PS_VADAPT_EN              (1 << 7)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7134  #define PS_VADAPT_MODE_MASK        (3 << 5)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7135  #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7136  #define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7137  #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
b1554e23ccb6d8e Maarten Lankhorst             2018-10-18   7138  #define PS_PLANE_Y_SEL_MASK  (7 << 5)
b1554e23ccb6d8e Maarten Lankhorst             2018-10-18   7139  #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7140  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7141  #define _PS_PWR_GATE_1A     0x68160
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7142  #define _PS_PWR_GATE_2A     0x68260
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7143  #define _PS_PWR_GATE_1B     0x68960
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7144  #define _PS_PWR_GATE_2B     0x68A60
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7145  #define _PS_PWR_GATE_1C     0x69160
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7146  #define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7147  #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7148  #define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7149  #define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7150  #define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7151  #define PS_PWR_GATE_SLPEN_8             0
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7152  #define PS_PWR_GATE_SLPEN_16            1
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7153  #define PS_PWR_GATE_SLPEN_24            2
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7154  #define PS_PWR_GATE_SLPEN_32            3
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7155  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7156  #define _PS_WIN_POS_1A      0x68170
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7157  #define _PS_WIN_POS_2A      0x68270
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7158  #define _PS_WIN_POS_1B      0x68970
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7159  #define _PS_WIN_POS_2B      0x68A70
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7160  #define _PS_WIN_POS_1C      0x69170
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7161  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7162  #define _PS_WIN_SZ_1A       0x68174
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7163  #define _PS_WIN_SZ_2A       0x68274
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7164  #define _PS_WIN_SZ_1B       0x68974
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7165  #define _PS_WIN_SZ_2B       0x68A74
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7166  #define _PS_WIN_SZ_1C       0x69174
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7167  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7168  #define _PS_VSCALE_1A       0x68184
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7169  #define _PS_VSCALE_2A       0x68284
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7170  #define _PS_VSCALE_1B       0x68984
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7171  #define _PS_VSCALE_2B       0x68A84
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7172  #define _PS_VSCALE_1C       0x69184
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7173  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7174  #define _PS_HSCALE_1A       0x68190
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7175  #define _PS_HSCALE_2A       0x68290
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7176  #define _PS_HSCALE_1B       0x68990
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7177  #define _PS_HSCALE_2B       0x68A90
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7178  #define _PS_HSCALE_1C       0x69190
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7179  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7180  #define _PS_VPHASE_1A       0x68188
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7181  #define _PS_VPHASE_2A       0x68288
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7182  #define _PS_VPHASE_1B       0x68988
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7183  #define _PS_VPHASE_2B       0x68A88
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7184  #define _PS_VPHASE_1C       0x69188
0a59952b24e24e1 Ville Syrjälä                 2018-05-21   7185  #define  PS_Y_PHASE(x)		((x) << 16)
0a59952b24e24e1 Ville Syrjälä                 2018-05-21   7186  #define  PS_UV_RGB_PHASE(x)	((x) << 0)
0a59952b24e24e1 Ville Syrjälä                 2018-05-21   7187  #define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
0a59952b24e24e1 Ville Syrjälä                 2018-05-21   7188  #define   PS_PHASE_TRIP	(1 << 0)
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7189  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7190  #define _PS_HPHASE_1A       0x68194
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7191  #define _PS_HPHASE_2A       0x68294
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7192  #define _PS_HPHASE_1B       0x68994
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7193  #define _PS_HPHASE_2B       0x68A94
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7194  #define _PS_HPHASE_1C       0x69194
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7195  
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7196  #define _PS_ECC_STAT_1A     0x681D0
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7197  #define _PS_ECC_STAT_2A     0x682D0
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7198  #define _PS_ECC_STAT_1B     0x689D0
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7199  #define _PS_ECC_STAT_2B     0x68AD0
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7200  #define _PS_ECC_STAT_1C     0x691D0
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7201  
e67005e59a74613 Jani Nikula                   2018-06-29   7202  #define _ID(id, a, b) _PICK_EVEN(id, a, b)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7203  #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7204  			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7205  			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7206  #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe,    \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7207  			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7208  			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7209  #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe,     \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7210  			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7211  			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7212  #define SKL_PS_WIN_SZ(pipe, id)  _MMIO_PIPE(pipe,     \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7213  			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7214  			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7215  #define SKL_PS_VSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7216  			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7217  			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7218  #define SKL_PS_HSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7219  			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7220  			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7221  #define SKL_PS_VPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7222  			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7223  			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7224  #define SKL_PS_HPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7225  			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7226  			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7227  #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7228  			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
9bca5d0ca76c0ce Ville Syrjälä                 2015-11-04   7229  			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
1c9a2d4ace0d93a Chandra Konduru               2015-04-07   7230  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7231  /* legacy palette */
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7232  #define _LGC_PALETTE_A           0x4a000
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   7233  #define _LGC_PALETTE_B           0x4a800
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7234  #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7235  
514462caf757700 Ville Syrjälä                 2019-04-01   7236  /* ilk/snb precision palette */
514462caf757700 Ville Syrjälä                 2019-04-01   7237  #define _PREC_PALETTE_A           0x4b000
514462caf757700 Ville Syrjälä                 2019-04-01   7238  #define _PREC_PALETTE_B           0x4c000
514462caf757700 Ville Syrjälä                 2019-04-01   7239  #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
514462caf757700 Ville Syrjälä                 2019-04-01   7240  
514462caf757700 Ville Syrjälä                 2019-04-01   7241  #define  _PREC_PIPEAGCMAX              0x4d000
514462caf757700 Ville Syrjälä                 2019-04-01   7242  #define  _PREC_PIPEBGCMAX              0x4d010
514462caf757700 Ville Syrjälä                 2019-04-01   7243  #define PREC_PIPEGCMAX(pipe, i)        _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
514462caf757700 Ville Syrjälä                 2019-04-01   7244  
42db64efcd95014 Paulo Zanoni                  2013-05-31   7245  #define _GAMMA_MODE_A		0x4a480
42db64efcd95014 Paulo Zanoni                  2013-05-31   7246  #define _GAMMA_MODE_B		0x4ac80
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7247  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
13717cef4c1d627 Uma Shankar                   2019-02-11   7248  #define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
13717cef4c1d627 Uma Shankar                   2019-02-11   7249  #define  POST_CSC_GAMMA_ENABLE	(1 << 30)
5bda1aca5d9475e Ville Syrjälä                 2019-04-01   7250  #define  GAMMA_MODE_MODE_MASK	(3 << 0)
3eff4faa9f59c58 Daniel Vetter                 2013-06-13   7251  #define  GAMMA_MODE_MODE_8BIT	(0 << 0)
3eff4faa9f59c58 Daniel Vetter                 2013-06-13   7252  #define  GAMMA_MODE_MODE_10BIT	(1 << 0)
3eff4faa9f59c58 Daniel Vetter                 2013-06-13   7253  #define  GAMMA_MODE_MODE_12BIT	(2 << 0)
377c70edd486754 Uma Shankar                   2019-06-12   7254  #define  GAMMA_MODE_MODE_SPLIT	(3 << 0) /* ivb-bdw */
377c70edd486754 Uma Shankar                   2019-06-12   7255  #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
42db64efcd95014 Paulo Zanoni                  2013-05-31   7256  
8337206d3bf088c Damien Lespiau                2015-10-30   7257  /* DMC/CSR */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7258  #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
6fb403de3620dea Mika Kuoppala                 2015-10-30   7259  #define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
6fb403de3620dea Mika Kuoppala                 2015-10-30   7260  #define CSR_HTP_ADDR_SKL	0x00500034
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7261  #define CSR_SSP_BASE		_MMIO(0x8F074)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7262  #define CSR_HTP_SKL		_MMIO(0x8F004)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7263  #define CSR_LAST_WRITE		_MMIO(0x8F034)
6fb403de3620dea Mika Kuoppala                 2015-10-30   7264  #define CSR_LAST_WRITE_VALUE	0xc003b400
6fb403de3620dea Mika Kuoppala                 2015-10-30   7265  /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
6fb403de3620dea Mika Kuoppala                 2015-10-30   7266  #define CSR_MMIO_START_RANGE	0x80000
6fb403de3620dea Mika Kuoppala                 2015-10-30   7267  #define CSR_MMIO_END_RANGE	0x8FFFF
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7268  #define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7269  #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7270  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
8337206d3bf088c Damien Lespiau                2015-10-30   7271  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7272  /* interrupts */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7273  #define DE_MASTER_IRQ_CONTROL   (1 << 31)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7274  #define DE_SPRITEB_FLIP_DONE    (1 << 29)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7275  #define DE_SPRITEA_FLIP_DONE    (1 << 28)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7276  #define DE_PLANEB_FLIP_DONE     (1 << 27)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7277  #define DE_PLANEA_FLIP_DONE     (1 << 26)
40da17c29be95ac Daniel Vetter                 2013-10-21   7278  #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7279  #define DE_PCU_EVENT            (1 << 25)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7280  #define DE_GTT_FAULT            (1 << 24)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7281  #define DE_POISON               (1 << 23)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7282  #define DE_PERFORM_COUNTER      (1 << 22)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7283  #define DE_PCH_EVENT            (1 << 21)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7284  #define DE_AUX_CHANNEL_A        (1 << 20)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7285  #define DE_DP_A_HOTPLUG         (1 << 19)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7286  #define DE_GSE                  (1 << 18)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7287  #define DE_PIPEB_VBLANK         (1 << 15)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7288  #define DE_PIPEB_EVEN_FIELD     (1 << 14)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7289  #define DE_PIPEB_ODD_FIELD      (1 << 13)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7290  #define DE_PIPEB_LINE_COMPARE   (1 << 12)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7291  #define DE_PIPEB_VSYNC          (1 << 11)
5b3a856bcfa3d24 Daniel Vetter                 2013-10-16   7292  #define DE_PIPEB_CRC_DONE	(1 << 10)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7293  #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7294  #define DE_PIPEA_VBLANK         (1 << 7)
40da17c29be95ac Daniel Vetter                 2013-10-21   7295  #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7296  #define DE_PIPEA_EVEN_FIELD     (1 << 6)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7297  #define DE_PIPEA_ODD_FIELD      (1 << 5)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7298  #define DE_PIPEA_LINE_COMPARE   (1 << 4)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7299  #define DE_PIPEA_VSYNC          (1 << 3)
5b3a856bcfa3d24 Daniel Vetter                 2013-10-16   7300  #define DE_PIPEA_CRC_DONE	(1 << 2)
40da17c29be95ac Daniel Vetter                 2013-10-21   7301  #define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7302  #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
40da17c29be95ac Daniel Vetter                 2013-10-21   7303  #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7304  
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7305  /* More Ivybridge lolz */
8664281b64c4577 Paulo Zanoni                  2013-04-12   7306  #define DE_ERR_INT_IVB			(1 << 30)
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7307  #define DE_GSE_IVB			(1 << 29)
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7308  #define DE_PCH_EVENT_IVB		(1 << 28)
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7309  #define DE_DP_A_HOTPLUG_IVB		(1 << 27)
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7310  #define DE_AUX_CHANNEL_A_IVB		(1 << 26)
fc34044248b611e Daniel Vetter                 2018-04-05   7311  #define DE_EDP_PSR_INT_HSW		(1 << 19)
b615b57a124a4af Chris Wilson                  2012-05-02   7312  #define DE_SPRITEC_FLIP_DONE_IVB	(1 << 14)
b615b57a124a4af Chris Wilson                  2012-05-02   7313  #define DE_PLANEC_FLIP_DONE_IVB		(1 << 13)
b615b57a124a4af Chris Wilson                  2012-05-02   7314  #define DE_PIPEC_VBLANK_IVB		(1 << 10)
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7315  #define DE_SPRITEB_FLIP_DONE_IVB	(1 << 9)
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7316  #define DE_PLANEB_FLIP_DONE_IVB		(1 << 8)
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7317  #define DE_PIPEB_VBLANK_IVB		(1 << 5)
b615b57a124a4af Chris Wilson                  2012-05-02   7318  #define DE_SPRITEA_FLIP_DONE_IVB	(1 << 4)
b615b57a124a4af Chris Wilson                  2012-05-02   7319  #define DE_PLANEA_FLIP_DONE_IVB		(1 << 3)
40da17c29be95ac Daniel Vetter                 2013-10-21   7320  #define DE_PLANE_FLIP_DONE_IVB(plane)	(1 << (3 + 5 * (plane)))
b1f14ad01ab09f5 Jesse Barnes                  2011-04-06   7321  #define DE_PIPEA_VBLANK_IVB		(1 << 0)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   7322  #define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
b518421f5f91365 Paulo Zanoni                  2013-07-12   7323  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7324  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
7eea1ddf6168cbe Jesse Barnes                  2012-03-22   7325  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
7eea1ddf6168cbe Jesse Barnes                  2012-03-22   7326  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7327  #define DEISR   _MMIO(0x44000)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7328  #define DEIMR   _MMIO(0x44004)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7329  #define DEIIR   _MMIO(0x44008)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7330  #define DEIER   _MMIO(0x4400c)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7331  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7332  #define GTISR   _MMIO(0x44010)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7333  #define GTIMR   _MMIO(0x44014)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7334  #define GTIIR   _MMIO(0x44018)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7335  #define GTIER   _MMIO(0x4401c)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7336  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7337  #define GEN8_MASTER_IRQ			_MMIO(0x44200)
abd58f0175915be Ben Widawsky                  2013-11-02   7338  #define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
abd58f0175915be Ben Widawsky                  2013-11-02   7339  #define  GEN8_PCU_IRQ			(1 << 30)
abd58f0175915be Ben Widawsky                  2013-11-02   7340  #define  GEN8_DE_PCH_IRQ		(1 << 23)
abd58f0175915be Ben Widawsky                  2013-11-02   7341  #define  GEN8_DE_MISC_IRQ		(1 << 22)
abd58f0175915be Ben Widawsky                  2013-11-02   7342  #define  GEN8_DE_PORT_IRQ		(1 << 20)
abd58f0175915be Ben Widawsky                  2013-11-02   7343  #define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
abd58f0175915be Ben Widawsky                  2013-11-02   7344  #define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
abd58f0175915be Ben Widawsky                  2013-11-02   7345  #define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   7346  #define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
abd58f0175915be Ben Widawsky                  2013-11-02   7347  #define  GEN8_GT_VECS_IRQ		(1 << 6)
26705e20752a4ad Sagar Arun Kamble             2016-10-12   7348  #define  GEN8_GT_GUC_IRQ		(1 << 5)
0961021aef788e9 Ben Widawsky                  2014-05-15   7349  #define  GEN8_GT_PM_IRQ			(1 << 4)
8a68d464366efb5 Chris Wilson                  2019-03-05   7350  #define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
8a68d464366efb5 Chris Wilson                  2019-03-05   7351  #define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
abd58f0175915be Ben Widawsky                  2013-11-02   7352  #define  GEN8_GT_BCS_IRQ		(1 << 1)
abd58f0175915be Ben Widawsky                  2013-11-02   7353  #define  GEN8_GT_RCS_IRQ		(1 << 0)
abd58f0175915be Ben Widawsky                  2013-11-02   7354  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7355  #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7356  #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7357  #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7358  #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
abd58f0175915be Ben Widawsky                  2013-11-02   7359  
abd58f0175915be Ben Widawsky                  2013-11-02   7360  #define GEN8_RCS_IRQ_SHIFT 0
4df001d3989ed31 Dave Gordon                   2015-08-12   7361  #define GEN8_BCS_IRQ_SHIFT 16
8a68d464366efb5 Chris Wilson                  2019-03-05   7362  #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
8a68d464366efb5 Chris Wilson                  2019-03-05   7363  #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
abd58f0175915be Ben Widawsky                  2013-11-02   7364  #define GEN8_VECS_IRQ_SHIFT 0
4df001d3989ed31 Dave Gordon                   2015-08-12   7365  #define GEN8_WD_IRQ_SHIFT 16
abd58f0175915be Ben Widawsky                  2013-11-02   7366  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7367  #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7368  #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7369  #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7370  #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
38d83c96a3f67ba Daniel Vetter                 2013-11-07   7371  #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
abd58f0175915be Ben Widawsky                  2013-11-02   7372  #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
abd58f0175915be Ben Widawsky                  2013-11-02   7373  #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
abd58f0175915be Ben Widawsky                  2013-11-02   7374  #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
abd58f0175915be Ben Widawsky                  2013-11-02   7375  #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
abd58f0175915be Ben Widawsky                  2013-11-02   7376  #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
abd58f0175915be Ben Widawsky                  2013-11-02   7377  #define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
d0e1f1cbe3e4536 Damien Lespiau                2014-04-08   7378  #define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
abd58f0175915be Ben Widawsky                  2013-11-02   7379  #define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
abd58f0175915be Ben Widawsky                  2013-11-02   7380  #define  GEN8_PIPE_VSYNC		(1 << 1)
abd58f0175915be Ben Widawsky                  2013-11-02   7381  #define  GEN8_PIPE_VBLANK		(1 << 0)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7382  #define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
b21249c90e7ad8f Damien Lespiau                2015-03-17   7383  #define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7384  #define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7385  #define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7386  #define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
b21249c90e7ad8f Damien Lespiau                2015-03-17   7387  #define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7388  #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7389  #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7390  #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   7391  #define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
30100f2bea6b079 Daniel Vetter                 2013-11-07   7392  #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
30100f2bea6b079 Daniel Vetter                 2013-11-07   7393  	(GEN8_PIPE_CURSOR_FAULT | \
abd58f0175915be Ben Widawsky                  2013-11-02   7394  	 GEN8_PIPE_SPRITE_FAULT | \
abd58f0175915be Ben Widawsky                  2013-11-02   7395  	 GEN8_PIPE_PRIMARY_FAULT)
770de83dc0b4f13 Damien Lespiau                2014-03-20   7396  #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
770de83dc0b4f13 Damien Lespiau                2014-03-20   7397  	(GEN9_PIPE_CURSOR_FAULT | \
b21249c90e7ad8f Damien Lespiau                2015-03-17   7398  	 GEN9_PIPE_PLANE4_FAULT | \
770de83dc0b4f13 Damien Lespiau                2014-03-20   7399  	 GEN9_PIPE_PLANE3_FAULT | \
770de83dc0b4f13 Damien Lespiau                2014-03-20   7400  	 GEN9_PIPE_PLANE2_FAULT | \
770de83dc0b4f13 Damien Lespiau                2014-03-20   7401  	 GEN9_PIPE_PLANE1_FAULT)
abd58f0175915be Ben Widawsky                  2013-11-02   7402  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7403  #define GEN8_DE_PORT_ISR _MMIO(0x44440)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7404  #define GEN8_DE_PORT_IMR _MMIO(0x44444)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7405  #define GEN8_DE_PORT_IIR _MMIO(0x44448)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7406  #define GEN8_DE_PORT_IER _MMIO(0x4444c)
bb187e93e48d3a3 James Ausmus                  2018-06-11   7407  #define  ICL_AUX_CHANNEL_E		(1 << 29)
a324fcaca314caf Rodrigo Vivi                  2018-01-29   7408  #define  CNL_AUX_CHANNEL_F		(1 << 28)
88e047034084ca2 Jesse Barnes                  2014-11-13   7409  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
88e047034084ca2 Jesse Barnes                  2014-11-13   7410  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
88e047034084ca2 Jesse Barnes                  2014-11-13   7411  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
e0a20ad78c06be2 Shashank Sharma               2015-03-27   7412  #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
e0a20ad78c06be2 Shashank Sharma               2015-03-27   7413  #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
e0a20ad78c06be2 Shashank Sharma               2015-03-27   7414  #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
e0a20ad78c06be2 Shashank Sharma               2015-03-27   7415  #define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
e0a20ad78c06be2 Shashank Sharma               2015-03-27   7416  					 BXT_DE_PORT_HP_DDIB | \
e0a20ad78c06be2 Shashank Sharma               2015-03-27   7417  					 BXT_DE_PORT_HP_DDIC)
e0a20ad78c06be2 Shashank Sharma               2015-03-27   7418  #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
9e63743ebbcb138 Shashank Sharma               2014-08-22   7419  #define  BXT_DE_PORT_GMBUS		(1 << 1)
6d766f022a57446 Daniel Vetter                 2013-11-07   7420  #define  GEN8_AUX_CHANNEL_A		(1 << 0)
abd58f0175915be Ben Widawsky                  2013-11-02   7421  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7422  #define GEN8_DE_MISC_ISR _MMIO(0x44460)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7423  #define GEN8_DE_MISC_IMR _MMIO(0x44464)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7424  #define GEN8_DE_MISC_IIR _MMIO(0x44468)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7425  #define GEN8_DE_MISC_IER _MMIO(0x4446c)
abd58f0175915be Ben Widawsky                  2013-11-02   7426  #define  GEN8_DE_MISC_GSE		(1 << 27)
e04f7ece1c4530b Ville Syrjälä                 2018-04-03   7427  #define  GEN8_DE_EDP_PSR		(1 << 19)
abd58f0175915be Ben Widawsky                  2013-11-02   7428  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7429  #define GEN8_PCU_ISR _MMIO(0x444e0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7430  #define GEN8_PCU_IMR _MMIO(0x444e4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7431  #define GEN8_PCU_IIR _MMIO(0x444e8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7432  #define GEN8_PCU_IER _MMIO(0x444ec)
abd58f0175915be Ben Widawsky                  2013-11-02   7433  
df0d28c185ad29d Dhinakaran Pandiyan           2018-06-15   7434  #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
df0d28c185ad29d Dhinakaran Pandiyan           2018-06-15   7435  #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
df0d28c185ad29d Dhinakaran Pandiyan           2018-06-15   7436  #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
df0d28c185ad29d Dhinakaran Pandiyan           2018-06-15   7437  #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
df0d28c185ad29d Dhinakaran Pandiyan           2018-06-15   7438  #define  GEN11_GU_MISC_GSE	(1 << 27)
df0d28c185ad29d Dhinakaran Pandiyan           2018-06-15   7439  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7440  #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7441  #define  GEN11_MASTER_IRQ		(1 << 31)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7442  #define  GEN11_PCU_IRQ			(1 << 30)
df0d28c185ad29d Dhinakaran Pandiyan           2018-06-15   7443  #define  GEN11_GU_MISC_IRQ		(1 << 29)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7444  #define  GEN11_DISPLAY_IRQ		(1 << 16)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7445  #define  GEN11_GT_DW_IRQ(x)		(1 << (x))
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7446  #define  GEN11_GT_DW1_IRQ		(1 << 1)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7447  #define  GEN11_GT_DW0_IRQ		(1 << 0)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7448  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7449  #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7450  #define  GEN11_DISPLAY_IRQ_ENABLE	(1 << 31)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7451  #define  GEN11_AUDIO_CODEC_IRQ		(1 << 24)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7452  #define  GEN11_DE_PCH_IRQ		(1 << 23)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7453  #define  GEN11_DE_MISC_IRQ		(1 << 22)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7454  #define  GEN11_DE_HPD_IRQ		(1 << 21)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7455  #define  GEN11_DE_PORT_IRQ		(1 << 20)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7456  #define  GEN11_DE_PIPE_C		(1 << 18)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7457  #define  GEN11_DE_PIPE_B		(1 << 17)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7458  #define  GEN11_DE_PIPE_A		(1 << 16)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7459  
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7460  #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7461  #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7462  #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7463  #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7464  #define  GEN11_TC4_HOTPLUG			(1 << 19)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7465  #define  GEN11_TC3_HOTPLUG			(1 << 18)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7466  #define  GEN11_TC2_HOTPLUG			(1 << 17)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7467  #define  GEN11_TC1_HOTPLUG			(1 << 16)
b9fcddab4afbac6 Paulo Zanoni                  2018-07-25   7468  #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7469  #define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC4_HOTPLUG | \
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7470  						 GEN11_TC3_HOTPLUG | \
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7471  						 GEN11_TC2_HOTPLUG | \
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7472  						 GEN11_TC1_HOTPLUG)
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7473  #define  GEN11_TBT4_HOTPLUG			(1 << 3)
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7474  #define  GEN11_TBT3_HOTPLUG			(1 << 2)
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7475  #define  GEN11_TBT2_HOTPLUG			(1 << 1)
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7476  #define  GEN11_TBT1_HOTPLUG			(1 << 0)
b9fcddab4afbac6 Paulo Zanoni                  2018-07-25   7477  #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7478  #define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT4_HOTPLUG | \
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7479  						 GEN11_TBT3_HOTPLUG | \
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7480  						 GEN11_TBT2_HOTPLUG | \
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7481  						 GEN11_TBT1_HOTPLUG)
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7482  
b796b9710fd52d7 Dhinakaran Pandiyan           2018-06-15   7483  #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7484  #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7485  #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7486  #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7487  #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7488  #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
121e758ee5782b3 Dhinakaran Pandiyan           2018-06-15   7489  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7490  #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7491  #define  GEN11_CSME			(31)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7492  #define  GEN11_GUNIT			(28)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7493  #define  GEN11_GUC			(25)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7494  #define  GEN11_WDPERF			(20)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7495  #define  GEN11_KCR			(19)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7496  #define  GEN11_GTPM			(16)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7497  #define  GEN11_BCS			(15)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7498  #define  GEN11_RCS0			(0)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7499  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7500  #define GEN11_GT_INTR_DW1		_MMIO(0x19001c)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7501  #define  GEN11_VECS(x)			(31 - (x))
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7502  #define  GEN11_VCS(x)			(x)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7503  
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   7504  #define GEN11_GT_INTR_DW(x)		_MMIO(0x190018 + ((x) * 4))
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7505  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7506  #define GEN11_INTR_IDENTITY_REG0	_MMIO(0x190060)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7507  #define GEN11_INTR_IDENTITY_REG1	_MMIO(0x190064)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7508  #define  GEN11_INTR_DATA_VALID		(1 << 31)
f744dbc2a64d5de Mika Kuoppala                 2018-04-06   7509  #define  GEN11_INTR_ENGINE_CLASS(x)	(((x) & GENMASK(18, 16)) >> 16)
f744dbc2a64d5de Mika Kuoppala                 2018-04-06   7510  #define  GEN11_INTR_ENGINE_INSTANCE(x)	(((x) & GENMASK(25, 20)) >> 20)
f744dbc2a64d5de Mika Kuoppala                 2018-04-06   7511  #define  GEN11_INTR_ENGINE_INTR(x)	((x) & 0xffff)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7512  
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   7513  #define GEN11_INTR_IDENTITY_REG(x)	_MMIO(0x190060 + ((x) * 4))
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7514  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7515  #define GEN11_IIR_REG0_SELECTOR		_MMIO(0x190070)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7516  #define GEN11_IIR_REG1_SELECTOR		_MMIO(0x190074)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7517  
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   7518  #define GEN11_IIR_REG_SELECTOR(x)	_MMIO(0x190070 + ((x) * 4))
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7519  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7520  #define GEN11_RENDER_COPY_INTR_ENABLE	_MMIO(0x190030)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7521  #define GEN11_VCS_VECS_INTR_ENABLE	_MMIO(0x190034)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7522  #define GEN11_GUC_SG_INTR_ENABLE	_MMIO(0x190038)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7523  #define GEN11_GPM_WGBOXPERF_INTR_ENABLE	_MMIO(0x19003c)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7524  #define GEN11_CRYPTO_RSVD_INTR_ENABLE	_MMIO(0x190040)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7525  #define GEN11_GUNIT_CSME_INTR_ENABLE	_MMIO(0x190044)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7526  
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7527  #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7528  #define GEN11_BCS_RSVD_INTR_MASK	_MMIO(0x1900a0)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7529  #define GEN11_VCS0_VCS1_INTR_MASK	_MMIO(0x1900a8)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7530  #define GEN11_VCS2_VCS3_INTR_MASK	_MMIO(0x1900ac)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7531  #define GEN11_VECS0_VECS1_INTR_MASK	_MMIO(0x1900d0)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7532  #define GEN11_GUC_SG_INTR_MASK		_MMIO(0x1900e8)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7533  #define GEN11_GPM_WGBOXPERF_INTR_MASK	_MMIO(0x1900ec)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7534  #define GEN11_CRYPTO_RSVD_INTR_MASK	_MMIO(0x1900f0)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7535  #define GEN11_GUNIT_CSME_INTR_MASK	_MMIO(0x1900f4)
a6358dda29a2caa Tvrtko Ursulin                2018-01-09   7536  
54c52a8412501fe Oscar Mateo                   2019-05-27   7537  #define   ENGINE1_MASK			REG_GENMASK(31, 16)
54c52a8412501fe Oscar Mateo                   2019-05-27   7538  #define   ENGINE0_MASK			REG_GENMASK(15, 0)
54c52a8412501fe Oscar Mateo                   2019-05-27   7539  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7540  #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
67e92af01cb6f7e Eric Anholt                   2010-11-06   7541  /* Required on all Ironlake and Sandybridge according to the B-Spec. */
67e92af01cb6f7e Eric Anholt                   2010-11-06   7542  #define  ILK_ELPIN_409_SELECT	(1 << 25)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   7543  #define  ILK_DPARB_GATE	(1 << 22)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   7544  #define  ILK_VSDPFD_FULL	(1 << 21)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7545  #define FUSE_STRAP			_MMIO(0x42014)
4d3024428f5c3ef Chris Wilson                  2010-12-14   7546  #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
4d3024428f5c3ef Chris Wilson                  2010-12-14   7547  #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
4d3024428f5c3ef Chris Wilson                  2010-12-14   7548  #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
8c448cadd4dd1bb Gabriel Feceoru               2016-01-22   7549  #define  IVB_PIPE_C_DISABLE		(1 << 28)
4d3024428f5c3ef Chris Wilson                  2010-12-14   7550  #define  ILK_HDCP_DISABLE		(1 << 25)
4d3024428f5c3ef Chris Wilson                  2010-12-14   7551  #define  ILK_eDP_A_DISABLE		(1 << 24)
e3589908592cae9 Damien Lespiau                2014-02-07   7552  #define  HSW_CDCLK_LIMIT		(1 << 24)
4d3024428f5c3ef Chris Wilson                  2010-12-14   7553  #define  ILK_DESKTOP			(1 << 23)
b16c7ed95caf270 Ville Syrjälä                 2019-06-04   7554  #define  HSW_CPU_SSC_ENABLE		(1 << 21)
231e54f6391ccc7 Damien Lespiau                2012-10-19   7555  
86761789b38a90e Ville Syrjälä                 2019-06-04   7556  #define FUSE_STRAP3			_MMIO(0x42020)
86761789b38a90e Ville Syrjälä                 2019-06-04   7557  #define  HSW_REF_CLK_SELECT		(1 << 1)
86761789b38a90e Ville Syrjälä                 2019-06-04   7558  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7559  #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
231e54f6391ccc7 Damien Lespiau                2012-10-19   7560  #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
231e54f6391ccc7 Damien Lespiau                2012-10-19   7561  #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
231e54f6391ccc7 Damien Lespiau                2012-10-19   7562  #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
231e54f6391ccc7 Damien Lespiau                2012-10-19   7563  #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
231e54f6391ccc7 Damien Lespiau                2012-10-19   7564  #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   7565  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7566  #define IVB_CHICKEN3	_MMIO(0x4200c)
116ac8d26101c06 Eric Anholt                   2011-12-21   7567  # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
116ac8d26101c06 Eric Anholt                   2011-12-21   7568  # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
116ac8d26101c06 Eric Anholt                   2011-12-21   7569  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7570  #define CHICKEN_PAR1_1		_MMIO(0x42080)
93564044fb2c938 Ville Syrjälä                 2017-08-24   7571  #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
fe4ab3ceef20655 Ben Widawsky                  2013-11-02   7572  #define  DPA_MASK_VBLANK_SRD	(1 << 15)
90a8864320b2a9f Paulo Zanoni                  2013-05-03   7573  #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
dc00b6a07c2206e Daniel Vetter                 2016-05-19   7574  #define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)
90a8864320b2a9f Paulo Zanoni                  2013-05-03   7575  
17e0adf079a3bf2 Mika Kuoppala                 2016-06-07   7576  #define CHICKEN_PAR2_1		_MMIO(0x42090)
17e0adf079a3bf2 Mika Kuoppala                 2016-06-07   7577  #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
17e0adf079a3bf2 Mika Kuoppala                 2016-06-07   7578  
f4f4b59be52b288 Ander Conselvan de Oliveira   2017-02-22   7579  #define CHICKEN_MISC_2		_MMIO(0x42084)
746a51732688de0 Paulo Zanoni                  2017-07-14   7580  #define  CNL_COMP_PWR_DOWN	(1 << 23)
f4f4b59be52b288 Ander Conselvan de Oliveira   2017-02-22   7581  #define  GLK_CL2_PWR_DOWN	(1 << 12)
746a51732688de0 Paulo Zanoni                  2017-07-14   7582  #define  GLK_CL1_PWR_DOWN	(1 << 11)
746a51732688de0 Paulo Zanoni                  2017-07-14   7583  #define  GLK_CL0_PWR_DOWN	(1 << 10)
d8d4a512a6ffa97 Ville Syrjälä                 2017-06-09   7584  
5654a1623c8717c Praveen Paneri                2017-08-11   7585  #define CHICKEN_MISC_4		_MMIO(0x4208c)
5654a1623c8717c Praveen Paneri                2017-08-11   7586  #define   FBC_STRIDE_OVERRIDE	(1 << 13)
5654a1623c8717c Praveen Paneri                2017-08-11   7587  #define   FBC_STRIDE_MASK	0x1FFF
5654a1623c8717c Praveen Paneri                2017-08-11   7588  
fe4ab3ceef20655 Ben Widawsky                  2013-11-02   7589  #define _CHICKEN_PIPESL_1_A	0x420b0
fe4ab3ceef20655 Ben Widawsky                  2013-11-02   7590  #define _CHICKEN_PIPESL_1_B	0x420b4
8f670bb15a69e11 Ville Syrjälä                 2014-03-05   7591  #define  HSW_FBCQ_DIS			(1 << 22)
8f670bb15a69e11 Ville Syrjälä                 2014-03-05   7592  #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7593  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
fe4ab3ceef20655 Ben Widawsky                  2013-11-02   7594  
8f19b401a6fc6d1 Imre Deak                     2018-11-19   7595  #define CHICKEN_TRANS_A		_MMIO(0x420c0)
8f19b401a6fc6d1 Imre Deak                     2018-11-19   7596  #define CHICKEN_TRANS_B		_MMIO(0x420c4)
8f19b401a6fc6d1 Imre Deak                     2018-11-19   7597  #define CHICKEN_TRANS_C		_MMIO(0x420c8)
8f19b401a6fc6d1 Imre Deak                     2018-11-19   7598  #define CHICKEN_TRANS_EDP	_MMIO(0x420cc)
5e87325f5c57ba5 José Roberto de Souza         2018-03-28   7599  #define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK and CNL+ */
0519c102f528547 Ville Syrjälä                 2018-01-22   7600  #define  DDI_TRAINING_OVERRIDE_ENABLE	(1 << 19)
0519c102f528547 Ville Syrjälä                 2018-01-22   7601  #define  DDI_TRAINING_OVERRIDE_VALUE	(1 << 18)
0519c102f528547 Ville Syrjälä                 2018-01-22   7602  #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1 << 17) /* CHICKEN_TRANS_A only */
0519c102f528547 Ville Syrjälä                 2018-01-22   7603  #define  DDIE_TRAINING_OVERRIDE_VALUE	(1 << 16) /* CHICKEN_TRANS_A only */
d86f0482cd03c70 Nagaraju, Vathsala            2017-01-13   7604  #define  PSR2_ADD_VERTICAL_LINE_COUNT   (1 << 15)
0519c102f528547 Ville Syrjälä                 2018-01-22   7605  #define  PSR2_VSC_ENABLE_PROG_HEADER    (1 << 12)
d86f0482cd03c70 Nagaraju, Vathsala            2017-01-13   7606  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7607  #define DISP_ARB_CTL	_MMIO(0x45000)
303d4ea522e8672 Mika Kuoppala                 2016-06-07   7608  #define  DISP_FBC_MEMORY_WAKE		(1 << 31)
553bd149bb2de78 Zhenyu Wang                   2009-09-02   7609  #define  DISP_TILE_SURFACE_SWIZZLING	(1 << 13)
7f8a85698f5c8a9 Zhenyu Wang                   2010-04-01   7610  #define  DISP_FBC_WM_DIS		(1 << 15)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7611  #define DISP_ARB_CTL2	_MMIO(0x45004)
ac9545fda6ed13c Ville Syrjälä                 2013-12-05   7612  #define  DISP_DATA_PARTITION_5_6	(1 << 6)
2503a0fef214dda Kumar, Mahesh                 2017-08-17   7613  #define  DISP_IPC_ENABLE		(1 << 3)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7614  #define DBUF_CTL	_MMIO(0x45008)
746edf8f66ed8aa Mahesh Kumar                  2018-02-05   7615  #define DBUF_CTL_S1	_MMIO(0x45008)
746edf8f66ed8aa Mahesh Kumar                  2018-02-05   7616  #define DBUF_CTL_S2	_MMIO(0x44FE8)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   7617  #define  DBUF_POWER_REQUEST		(1 << 31)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   7618  #define  DBUF_POWER_STATE		(1 << 30)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7619  #define GEN7_MSG_CTL	_MMIO(0x45010)
88a2b2a32d71aad Ben Widawsky                  2013-04-05   7620  #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
88a2b2a32d71aad Ben Widawsky                  2013-04-05   7621  #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7622  #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
6ba844b090b62ef Daniel Vetter                 2014-01-22   7623  #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
553bd149bb2de78 Zhenyu Wang                   2009-09-02   7624  
590e8ff04bc0182 Mika Kuoppala                 2016-06-07   7625  #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
53421c2fe99ce16 Lucas De Marchi               2017-12-04   7626  #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
590e8ff04bc0182 Mika Kuoppala                 2016-06-07   7627  #define   MASK_WAKEMEM			(1 << 13)
ad186f3fd98a958 Paulo Zanoni                  2018-02-05   7628  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
590e8ff04bc0182 Mika Kuoppala                 2016-06-07   7629  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7630  #define SKL_DFSM			_MMIO(0x51000)
a9419e846bd8c8e Damien Lespiau                2015-06-04   7631  #define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
a9419e846bd8c8e Damien Lespiau                2015-06-04   7632  #define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
a9419e846bd8c8e Damien Lespiau                2015-06-04   7633  #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
a9419e846bd8c8e Damien Lespiau                2015-06-04   7634  #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
a9419e846bd8c8e Damien Lespiau                2015-06-04   7635  #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
bf4f2fb05f89ac5 Patrik Jakobsson              2016-01-20   7636  #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
bf4f2fb05f89ac5 Patrik Jakobsson              2016-01-20   7637  #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
bf4f2fb05f89ac5 Patrik Jakobsson              2016-01-20   7638  #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
7ff0fca4964ff19 José Roberto de Souza         2019-07-11   7639  #define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
a9419e846bd8c8e Damien Lespiau                2015-06-04   7640  
945f2672ccbb5c9 Ville Syrjälä                 2017-06-09   7641  #define SKL_DSSM				_MMIO(0x51004)
945f2672ccbb5c9 Ville Syrjälä                 2017-06-09   7642  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
186a277e317a14d Paulo Zanoni                  2018-02-06   7643  #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
186a277e317a14d Paulo Zanoni                  2018-02-06   7644  #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
186a277e317a14d Paulo Zanoni                  2018-02-06   7645  #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
186a277e317a14d Paulo Zanoni                  2018-02-06   7646  #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
945f2672ccbb5c9 Ville Syrjälä                 2017-06-09   7647  
a78536e73f35471 Arun Siluvery                 2016-01-21   7648  #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
a78536e73f35471 Arun Siluvery                 2016-01-21   7649  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1 << 14)
a78536e73f35471 Arun Siluvery                 2016-01-21   7650  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7651  #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
2caa3b260aa6a3d Damien Lespiau                2015-02-09   7652  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1 << 8)
780f0aebda2e2f9 arun.siluvery at linux.intel.com 2016-06-03   7653  #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
2caa3b260aa6a3d Damien Lespiau                2015-02-09   7654  
2c8580e4e21c170 Arun Siluvery                 2016-01-21   7655  #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
6bb6285582e0cf9 arun.siluvery at linux.intel.com 2016-06-06   7656  #define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)
e0f3fa096d6f319 Arun Siluvery                 2016-01-21   7657  #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
5152defe4a53ad1 Michał Winiarski              2017-10-03   7658  #define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)
5152defe4a53ad1 Michał Winiarski              2017-10-03   7659  #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)	(((hi) << 2) | ((lo) << 1))
5152defe4a53ad1 Michał Winiarski              2017-10-03   7660  #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
5152defe4a53ad1 Michał Winiarski              2017-10-03   7661  #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
5152defe4a53ad1 Michał Winiarski              2017-10-03   7662  #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
5152defe4a53ad1 Michał Winiarski              2017-10-03   7663  #define GEN9_PREEMPT_GPGPU_LEVEL_MASK		GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
e0f3fa096d6f319 Arun Siluvery                 2016-01-21   7664  
e4e0c058a19c411 Eugeni Dodonov                2012-02-08   7665  /* GEN7 chicken */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7666  #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
d71de14ddf423cc Kenneth Graunke               2012-02-08   7667    #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1 << 10) | (1 << 26))
183c6daceb7efa5 Damien Lespiau                2015-02-09   7668    #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
b1f88820f4d7ea5 Oscar Mateo                   2018-05-25   7669  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7670  #define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
93564044fb2c938 Ville Syrjälä                 2017-08-24   7671    #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
873e8171aebe9e6 Mika Kuoppala                 2016-07-20   7672    #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
ad2bdb44b19529b Mika Kuoppala                 2016-06-07   7673    #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
a75f36283d12d13 Ben Widawsky                  2013-11-02   7674    #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
d71de14ddf423cc Kenneth Graunke               2012-02-08   7675  
cbe3e1d10379370 Tvrtko Ursulin                2019-05-20   7676  #define GEN8_L3CNTLREG	_MMIO(0x7034)
cbe3e1d10379370 Tvrtko Ursulin                2019-05-20   7677    #define GEN8_ERRDETBCTRL (1 << 9)
cbe3e1d10379370 Tvrtko Ursulin                2019-05-20   7678  
b1f88820f4d7ea5 Oscar Mateo                   2018-05-25   7679  #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
b1f88820f4d7ea5 Oscar Mateo                   2018-05-25   7680    #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
b1f88820f4d7ea5 Oscar Mateo                   2018-05-25   7681  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7682  #define HIZ_CHICKEN					_MMIO(0x7018)
d60de81da48aa25 Kenneth Graunke               2015-01-10   7683  # define CHV_HZ_8X8_MODE_IN_1X				(1 << 15)
d0bbbc4faf7bc12 Damien Lespiau                2015-02-09   7684  # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1 << 3)
d60de81da48aa25 Kenneth Graunke               2015-01-10   7685  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7686  #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
183c6daceb7efa5 Damien Lespiau                2015-02-09   7687  #define  DISABLE_PIXEL_MASK_CAMMING		(1 << 14)
183c6daceb7efa5 Damien Lespiau                2015-02-09   7688  
ab062639edb0412 Kenneth Graunke               2018-01-05   7689  #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
f63c7b4880aabaf Oscar Mateo                   2018-05-25   7690  #define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
ab062639edb0412 Kenneth Graunke               2018-01-05   7691  
0c7d2aedf51b0a9 Radhakrishna Sripada          2018-10-04   7692  #define GEN7_SARCHKMD				_MMIO(0xB000)
0c7d2aedf51b0a9 Radhakrishna Sripada          2018-10-04   7693  #define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)
71ffd49cc9b9da5 Anuj Phogat                   2018-10-04   7694  #define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
0c7d2aedf51b0a9 Radhakrishna Sripada          2018-10-04   7695  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7696  #define GEN7_L3SQCREG1				_MMIO(0xB010)
031994ee8dedfa6 Ville Syrjälä                 2014-01-22   7697  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
031994ee8dedfa6 Ville Syrjälä                 2014-01-22   7698  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7699  #define GEN8_L3SQCREG1				_MMIO(0xB100)
450174fe9cc6a1f Imre Deak                     2016-05-03   7700  /*
450174fe9cc6a1f Imre Deak                     2016-05-03   7701   * Note that on CHV the following has an off-by-one error wrt. to BSpec.
450174fe9cc6a1f Imre Deak                     2016-05-03   7702   * Using the formula in BSpec leads to a hang, while the formula here works
450174fe9cc6a1f Imre Deak                     2016-05-03   7703   * fine and matches the formulas for all other platforms. A BSpec change
450174fe9cc6a1f Imre Deak                     2016-05-03   7704   * request has been filed to clarify this.
450174fe9cc6a1f Imre Deak                     2016-05-03   7705   */
36579cb63b87b7a Imre Deak                     2016-05-03   7706  #define  L3_GENERAL_PRIO_CREDITS(x)		(((x) >> 1) << 19)
36579cb63b87b7a Imre Deak                     2016-05-03   7707  #define  L3_HIGH_PRIO_CREDITS(x)		(((x) >> 1) << 14)
930a784d02339be Oscar Mateo                   2017-10-17   7708  #define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))
51ce4db1749028b Rodrigo Vivi                  2015-03-31   7709  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7710  #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
1af8452f1644acd Chris Wilson                  2014-02-14   7711  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
d0cf5eadc018280 Jesse Barnes                  2012-10-25   7712  #define  GEN7_L3AGDIS				(1 << 19)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7713  #define GEN7_L3CNTLREG2				_MMIO(0xB020)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7714  #define GEN7_L3CNTLREG3				_MMIO(0xB024)
e4e0c058a19c411 Eugeni Dodonov                2012-02-08   7715  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7716  #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
e4e0c058a19c411 Eugeni Dodonov                2012-02-08   7717  #define   GEN7_WA_L3_CHICKEN_MODE		0x20000000
5215eef35fcbbc8 Oscar Mateo                   2018-05-08   7718  #define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
5215eef35fcbbc8 Oscar Mateo                   2018-05-08   7719  #define   GEN11_I2M_WRITE_DISABLE		(1 << 28)
e4e0c058a19c411 Eugeni Dodonov                2012-02-08   7720  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7721  #define GEN7_L3SQCREG4				_MMIO(0xb034)
61939d977d66951 Jesse Barnes                  2012-10-02   7722  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1 << 27)
61939d977d66951 Jesse Barnes                  2012-10-02   7723  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7724  #define GEN8_L3SQCREG4				_MMIO(0xb118)
5246ae4bdb4ceae Oscar Mateo                   2018-05-08   7725  #define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
8bc0ccf6b1f0c0c Damien Lespiau                2015-02-09   7726  #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
c82435bbe5aca62 Arun Siluvery                 2015-06-19   7727  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
8bc0ccf6b1f0c0c Damien Lespiau                2015-02-09   7728  
63801f211c6eeb6 Ben Widawsky                  2013-12-12   7729  /* GEN8 chicken */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7730  #define HDC_CHICKEN0				_MMIO(0x7300)
acfb5554c769ad7 Rodrigo Vivi                  2017-08-23   7731  #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
cc38cae7c4e9350 Oscar Mateo                   2018-05-08   7732  #define ICL_HDC_MODE				_MMIO(0xE5F4)
2a0ee94fef9aa87 Imre Deak                     2015-05-19   7733  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
da09654d777c361 Rodrigo Vivi                  2014-09-19   7734  #define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
35cb6f3b4ee352b Damien Lespiau                2015-02-10   7735  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
35cb6f3b4ee352b Damien Lespiau                2015-02-10   7736  #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
35cb6f3b4ee352b Damien Lespiau                2015-02-10   7737  #define  HDC_FORCE_NON_COHERENT			(1 << 4)
65ca7514e21adbe Damien Lespiau                2015-02-09   7738  #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
63801f211c6eeb6 Ben Widawsky                  2013-12-12   7739  
3669ab6191b24ee Arun Siluvery                 2016-01-21   7740  #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
3669ab6191b24ee Arun Siluvery                 2016-01-21   7741  
38a39a7be77a097 Ben Widawsky                  2015-03-11   7742  /* GEN9 chicken */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7743  #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
38a39a7be77a097 Ben Widawsky                  2015-03-11   7744  #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
38a39a7be77a097 Ben Widawsky                  2015-03-11   7745  
0c79f9cb77eae28 Michel Thierry                2018-05-10   7746  #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
0c79f9cb77eae28 Michel Thierry                2018-05-10   7747  #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
0c79f9cb77eae28 Michel Thierry                2018-05-10   7748  
db099c8f963fe65 Eugeni Dodonov                2012-02-08   7749  /* WaCatErrorRejectionIssue */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7750  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
db099c8f963fe65 Eugeni Dodonov                2012-02-08   7751  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1 << 11)
db099c8f963fe65 Eugeni Dodonov                2012-02-08   7752  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7753  #define HSW_SCRATCH1				_MMIO(0xb038)
f3fc4884ebe6ae6 Francisco Jerez               2013-10-02   7754  #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1 << 27)
f3fc4884ebe6ae6 Francisco Jerez               2013-10-02   7755  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7756  #define BDW_SCRATCH1					_MMIO(0xb11c)
77719d28aeed5ca Damien Lespiau                2015-02-09   7757  #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
77719d28aeed5ca Damien Lespiau                2015-02-09   7758  
e16a375086337af Vandita Kulkarni              2018-06-21   7759  /*GEN11 chicken */
e16a375086337af Vandita Kulkarni              2018-06-21   7760  #define _PIPEA_CHICKEN				0x70038
e16a375086337af Vandita Kulkarni              2018-06-21   7761  #define _PIPEB_CHICKEN				0x71038
e16a375086337af Vandita Kulkarni              2018-06-21   7762  #define _PIPEC_CHICKEN				0x72038
e16a375086337af Vandita Kulkarni              2018-06-21   7763  #define PIPE_CHICKEN(pipe)			_MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
e16a375086337af Vandita Kulkarni              2018-06-21   7764  							   _PIPEB_CHICKEN)
26eeea1506838c7 Aditya Swarup                 2019-03-06   7765  #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
26eeea1506838c7 Aditya Swarup                 2019-03-06   7766  #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
e16a375086337af Vandita Kulkarni              2018-06-21   7767  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7768  /* PCH */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7769  
dce888798d3ed1c Lucas De Marchi               2018-07-27   7770  #define PCH_DISPLAY_BASE	0xc0000u
dce888798d3ed1c Lucas De Marchi               2018-07-27   7771  
23e81d691a81383 Adam Jackson                  2012-06-06   7772  /* south display engine interrupt: IBX */
776ad8062bb7769 Jesse Barnes                  2011-01-04   7773  #define SDE_AUDIO_POWER_D	(1 << 27)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7774  #define SDE_AUDIO_POWER_C	(1 << 26)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7775  #define SDE_AUDIO_POWER_B	(1 << 25)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7776  #define SDE_AUDIO_POWER_SHIFT	(25)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7777  #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7778  #define SDE_GMBUS		(1 << 24)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7779  #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7780  #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7781  #define SDE_AUDIO_HDCP_MASK	(3 << 22)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7782  #define SDE_AUDIO_TRANSB	(1 << 21)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7783  #define SDE_AUDIO_TRANSA	(1 << 20)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7784  #define SDE_AUDIO_TRANS_MASK	(3 << 20)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7785  #define SDE_POISON		(1 << 19)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7786  /* 18 reserved */
776ad8062bb7769 Jesse Barnes                  2011-01-04   7787  #define SDE_FDI_RXB		(1 << 17)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7788  #define SDE_FDI_RXA		(1 << 16)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7789  #define SDE_FDI_MASK		(3 << 16)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7790  #define SDE_AUXD		(1 << 15)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7791  #define SDE_AUXC		(1 << 14)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7792  #define SDE_AUXB		(1 << 13)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7793  #define SDE_AUX_MASK		(7 << 13)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7794  /* 12 reserved */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7795  #define SDE_CRT_HOTPLUG         (1 << 11)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7796  #define SDE_PORTD_HOTPLUG       (1 << 10)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7797  #define SDE_PORTC_HOTPLUG       (1 << 9)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7798  #define SDE_PORTB_HOTPLUG       (1 << 8)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7799  #define SDE_SDVOB_HOTPLUG       (1 << 6)
e5868a318d1ae28 Egbert Eich                   2013-02-28   7800  #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
e5868a318d1ae28 Egbert Eich                   2013-02-28   7801  				 SDE_SDVOB_HOTPLUG |	\
e5868a318d1ae28 Egbert Eich                   2013-02-28   7802  				 SDE_PORTB_HOTPLUG |	\
e5868a318d1ae28 Egbert Eich                   2013-02-28   7803  				 SDE_PORTC_HOTPLUG |	\
e5868a318d1ae28 Egbert Eich                   2013-02-28   7804  				 SDE_PORTD_HOTPLUG)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7805  #define SDE_TRANSB_CRC_DONE	(1 << 5)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7806  #define SDE_TRANSB_CRC_ERR	(1 << 4)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7807  #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7808  #define SDE_TRANSA_CRC_DONE	(1 << 2)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7809  #define SDE_TRANSA_CRC_ERR	(1 << 1)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7810  #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
776ad8062bb7769 Jesse Barnes                  2011-01-04   7811  #define SDE_TRANS_MASK		(0x3f)
23e81d691a81383 Adam Jackson                  2012-06-06   7812  
3160422251b214c Anusha Srivatsa               2018-06-26   7813  /* south display engine interrupt: CPT - CNP */
23e81d691a81383 Adam Jackson                  2012-06-06   7814  #define SDE_AUDIO_POWER_D_CPT	(1 << 31)
23e81d691a81383 Adam Jackson                  2012-06-06   7815  #define SDE_AUDIO_POWER_C_CPT	(1 << 30)
23e81d691a81383 Adam Jackson                  2012-06-06   7816  #define SDE_AUDIO_POWER_B_CPT	(1 << 29)
23e81d691a81383 Adam Jackson                  2012-06-06   7817  #define SDE_AUDIO_POWER_SHIFT_CPT   29
23e81d691a81383 Adam Jackson                  2012-06-06   7818  #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
23e81d691a81383 Adam Jackson                  2012-06-06   7819  #define SDE_AUXD_CPT		(1 << 27)
23e81d691a81383 Adam Jackson                  2012-06-06   7820  #define SDE_AUXC_CPT		(1 << 26)
23e81d691a81383 Adam Jackson                  2012-06-06   7821  #define SDE_AUXB_CPT		(1 << 25)
23e81d691a81383 Adam Jackson                  2012-06-06   7822  #define SDE_AUX_MASK_CPT	(7 << 25)
26951caf55d73ce Xiong Zhang                   2015-08-17   7823  #define SDE_PORTE_HOTPLUG_SPT	(1 << 25)
74c0b395fce4c80 Ville Syrjälä                 2015-08-27   7824  #define SDE_PORTA_HOTPLUG_SPT	(1 << 24)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   7825  #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   7826  #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   7827  #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
23e81d691a81383 Adam Jackson                  2012-06-06   7828  #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
73c352a265e8fde Daniel Vetter                 2013-03-26   7829  #define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
2d7b8366ae4a9ec Yuanhan Liu                   2010-10-08   7830  #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
73c352a265e8fde Daniel Vetter                 2013-03-26   7831  				 SDE_SDVOB_HOTPLUG_CPT |	\
2d7b8366ae4a9ec Yuanhan Liu                   2010-10-08   7832  				 SDE_PORTD_HOTPLUG_CPT |	\
2d7b8366ae4a9ec Yuanhan Liu                   2010-10-08   7833  				 SDE_PORTC_HOTPLUG_CPT |	\
2d7b8366ae4a9ec Yuanhan Liu                   2010-10-08   7834  				 SDE_PORTB_HOTPLUG_CPT)
26951caf55d73ce Xiong Zhang                   2015-08-17   7835  #define SDE_HOTPLUG_MASK_SPT	(SDE_PORTE_HOTPLUG_SPT |	\
26951caf55d73ce Xiong Zhang                   2015-08-17   7836  				 SDE_PORTD_HOTPLUG_CPT |	\
26951caf55d73ce Xiong Zhang                   2015-08-17   7837  				 SDE_PORTC_HOTPLUG_CPT |	\
74c0b395fce4c80 Ville Syrjälä                 2015-08-27   7838  				 SDE_PORTB_HOTPLUG_CPT |	\
74c0b395fce4c80 Ville Syrjälä                 2015-08-27   7839  				 SDE_PORTA_HOTPLUG_SPT)
23e81d691a81383 Adam Jackson                  2012-06-06   7840  #define SDE_GMBUS_CPT		(1 << 17)
8664281b64c4577 Paulo Zanoni                  2013-04-12   7841  #define SDE_ERROR_CPT		(1 << 16)
23e81d691a81383 Adam Jackson                  2012-06-06   7842  #define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
23e81d691a81383 Adam Jackson                  2012-06-06   7843  #define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
23e81d691a81383 Adam Jackson                  2012-06-06   7844  #define SDE_FDI_RXC_CPT		(1 << 8)
23e81d691a81383 Adam Jackson                  2012-06-06   7845  #define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
23e81d691a81383 Adam Jackson                  2012-06-06   7846  #define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
23e81d691a81383 Adam Jackson                  2012-06-06   7847  #define SDE_FDI_RXB_CPT		(1 << 4)
23e81d691a81383 Adam Jackson                  2012-06-06   7848  #define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
23e81d691a81383 Adam Jackson                  2012-06-06   7849  #define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
23e81d691a81383 Adam Jackson                  2012-06-06   7850  #define SDE_FDI_RXA_CPT		(1 << 0)
23e81d691a81383 Adam Jackson                  2012-06-06   7851  #define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
23e81d691a81383 Adam Jackson                  2012-06-06   7852  				 SDE_AUDIO_CP_REQ_B_CPT | \
23e81d691a81383 Adam Jackson                  2012-06-06   7853  				 SDE_AUDIO_CP_REQ_A_CPT)
23e81d691a81383 Adam Jackson                  2012-06-06   7854  #define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
23e81d691a81383 Adam Jackson                  2012-06-06   7855  				 SDE_AUDIO_CP_CHG_B_CPT | \
23e81d691a81383 Adam Jackson                  2012-06-06   7856  				 SDE_AUDIO_CP_CHG_A_CPT)
23e81d691a81383 Adam Jackson                  2012-06-06   7857  #define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
23e81d691a81383 Adam Jackson                  2012-06-06   7858  				 SDE_FDI_RXB_CPT | \
23e81d691a81383 Adam Jackson                  2012-06-06   7859  				 SDE_FDI_RXA_CPT)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7860  
3160422251b214c Anusha Srivatsa               2018-06-26   7861  /* south display engine interrupt: ICP */
3160422251b214c Anusha Srivatsa               2018-06-26   7862  #define SDE_TC4_HOTPLUG_ICP		(1 << 27)
3160422251b214c Anusha Srivatsa               2018-06-26   7863  #define SDE_TC3_HOTPLUG_ICP		(1 << 26)
3160422251b214c Anusha Srivatsa               2018-06-26   7864  #define SDE_TC2_HOTPLUG_ICP		(1 << 25)
3160422251b214c Anusha Srivatsa               2018-06-26   7865  #define SDE_TC1_HOTPLUG_ICP		(1 << 24)
3160422251b214c Anusha Srivatsa               2018-06-26   7866  #define SDE_GMBUS_ICP			(1 << 23)
3160422251b214c Anusha Srivatsa               2018-06-26   7867  #define SDE_DDIB_HOTPLUG_ICP		(1 << 17)
3160422251b214c Anusha Srivatsa               2018-06-26   7868  #define SDE_DDIA_HOTPLUG_ICP		(1 << 16)
b9fcddab4afbac6 Paulo Zanoni                  2018-07-25   7869  #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
b9fcddab4afbac6 Paulo Zanoni                  2018-07-25   7870  #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
3160422251b214c Anusha Srivatsa               2018-06-26   7871  #define SDE_DDI_MASK_ICP		(SDE_DDIB_HOTPLUG_ICP |	\
3160422251b214c Anusha Srivatsa               2018-06-26   7872  					 SDE_DDIA_HOTPLUG_ICP)
3160422251b214c Anusha Srivatsa               2018-06-26   7873  #define SDE_TC_MASK_ICP			(SDE_TC4_HOTPLUG_ICP |	\
3160422251b214c Anusha Srivatsa               2018-06-26   7874  					 SDE_TC3_HOTPLUG_ICP |	\
3160422251b214c Anusha Srivatsa               2018-06-26   7875  					 SDE_TC2_HOTPLUG_ICP |	\
3160422251b214c Anusha Srivatsa               2018-06-26   7876  					 SDE_TC1_HOTPLUG_ICP)
3160422251b214c Anusha Srivatsa               2018-06-26   7877  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7878  #define SDEISR  _MMIO(0xc4000)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7879  #define SDEIMR  _MMIO(0xc4004)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7880  #define SDEIIR  _MMIO(0xc4008)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7881  #define SDEIER  _MMIO(0xc400c)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7882  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7883  #define SERR_INT			_MMIO(0xc4040)
de032bf40a52dbb Paulo Zanoni                  2013-04-12   7884  #define  SERR_INT_POISON		(1 << 31)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   7885  #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
8664281b64c4577 Paulo Zanoni                  2013-04-12   7886  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7887  /* digital port hotplug */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7888  #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
195baa0673345c7 Ville Syrjälä                 2015-08-27   7889  #define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
d252bf68b757921 Shubhangi Shrivastava         2016-03-31   7890  #define  BXT_DDIA_HPD_INVERT            (1 << 27)
195baa0673345c7 Ville Syrjälä                 2015-08-27   7891  #define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
195baa0673345c7 Ville Syrjälä                 2015-08-27   7892  #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
195baa0673345c7 Ville Syrjälä                 2015-08-27   7893  #define  PORTA_HOTPLUG_SHORT_DETECT	(1 << 24) /* SPT+ & BXT */
195baa0673345c7 Ville Syrjälä                 2015-08-27   7894  #define  PORTA_HOTPLUG_LONG_DETECT	(2 << 24) /* SPT+ & BXT */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7895  #define  PORTD_HOTPLUG_ENABLE		(1 << 20)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7896  #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7897  #define  PORTD_PULSE_DURATION_4_5ms	(1 << 18) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7898  #define  PORTD_PULSE_DURATION_6ms	(2 << 18) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7899  #define  PORTD_PULSE_DURATION_100ms	(3 << 18) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7900  #define  PORTD_PULSE_DURATION_MASK	(3 << 18) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7901  #define  PORTD_HOTPLUG_STATUS_MASK	(3 << 16)
b696519e5191094 Damien Lespiau                2012-12-13   7902  #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7903  #define  PORTD_HOTPLUG_SHORT_DETECT	(1 << 16)
b696519e5191094 Damien Lespiau                2012-12-13   7904  #define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7905  #define  PORTC_HOTPLUG_ENABLE		(1 << 12)
d252bf68b757921 Shubhangi Shrivastava         2016-03-31   7906  #define  BXT_DDIC_HPD_INVERT            (1 << 11)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7907  #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7908  #define  PORTC_PULSE_DURATION_4_5ms	(1 << 10) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7909  #define  PORTC_PULSE_DURATION_6ms	(2 << 10) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7910  #define  PORTC_PULSE_DURATION_100ms	(3 << 10) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7911  #define  PORTC_PULSE_DURATION_MASK	(3 << 10) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7912  #define  PORTC_HOTPLUG_STATUS_MASK	(3 << 8)
b696519e5191094 Damien Lespiau                2012-12-13   7913  #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7914  #define  PORTC_HOTPLUG_SHORT_DETECT	(1 << 8)
b696519e5191094 Damien Lespiau                2012-12-13   7915  #define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7916  #define  PORTB_HOTPLUG_ENABLE		(1 << 4)
d252bf68b757921 Shubhangi Shrivastava         2016-03-31   7917  #define  BXT_DDIB_HPD_INVERT            (1 << 3)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7918  #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7919  #define  PORTB_PULSE_DURATION_4_5ms	(1 << 2) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7920  #define  PORTB_PULSE_DURATION_6ms	(2 << 2) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7921  #define  PORTB_PULSE_DURATION_100ms	(3 << 2) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7922  #define  PORTB_PULSE_DURATION_MASK	(3 << 2) /* pre-LPT */
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7923  #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
b696519e5191094 Damien Lespiau                2012-12-13   7924  #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7925  #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
b696519e5191094 Damien Lespiau                2012-12-13   7926  #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
d252bf68b757921 Shubhangi Shrivastava         2016-03-31   7927  #define  BXT_DDI_HPD_INVERT_MASK	(BXT_DDIA_HPD_INVERT | \
d252bf68b757921 Shubhangi Shrivastava         2016-03-31   7928  					BXT_DDIB_HPD_INVERT | \
d252bf68b757921 Shubhangi Shrivastava         2016-03-31   7929  					BXT_DDIC_HPD_INVERT)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7930  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   7931  #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
26951caf55d73ce Xiong Zhang                   2015-08-17   7932  #define  PORTE_HOTPLUG_ENABLE		(1 << 4)
40bfd7a3303b7c3 Ville Syrjälä                 2015-08-27   7933  #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
26951caf55d73ce Xiong Zhang                   2015-08-17   7934  #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
26951caf55d73ce Xiong Zhang                   2015-08-17   7935  #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
26951caf55d73ce Xiong Zhang                   2015-08-17   7936  #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   7937  
3160422251b214c Anusha Srivatsa               2018-06-26   7938  /* This register is a reuse of PCH_PORT_HOTPLUG register. The
3160422251b214c Anusha Srivatsa               2018-06-26   7939   * functionality covered in PCH_PORT_HOTPLUG is split into
3160422251b214c Anusha Srivatsa               2018-06-26   7940   * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
3160422251b214c Anusha Srivatsa               2018-06-26   7941   */
3160422251b214c Anusha Srivatsa               2018-06-26   7942  
3160422251b214c Anusha Srivatsa               2018-06-26   7943  #define SHOTPLUG_CTL_DDI			_MMIO(0xc4030)
3160422251b214c Anusha Srivatsa               2018-06-26   7944  #define   ICP_DDIB_HPD_ENABLE			(1 << 7)
3160422251b214c Anusha Srivatsa               2018-06-26   7945  #define   ICP_DDIB_HPD_STATUS_MASK		(3 << 4)
3160422251b214c Anusha Srivatsa               2018-06-26   7946  #define   ICP_DDIB_HPD_NO_DETECT		(0 << 4)
3160422251b214c Anusha Srivatsa               2018-06-26   7947  #define   ICP_DDIB_HPD_SHORT_DETECT		(1 << 4)
3160422251b214c Anusha Srivatsa               2018-06-26   7948  #define   ICP_DDIB_HPD_LONG_DETECT		(2 << 4)
3160422251b214c Anusha Srivatsa               2018-06-26   7949  #define   ICP_DDIB_HPD_SHORT_LONG_DETECT	(3 << 4)
3160422251b214c Anusha Srivatsa               2018-06-26   7950  #define   ICP_DDIA_HPD_ENABLE			(1 << 3)
05f2f03dd206177 Madhav Chauhan                2018-11-29   7951  #define   ICP_DDIA_HPD_OP_DRIVE_1		(1 << 2)
3160422251b214c Anusha Srivatsa               2018-06-26   7952  #define   ICP_DDIA_HPD_STATUS_MASK		(3 << 0)
3160422251b214c Anusha Srivatsa               2018-06-26   7953  #define   ICP_DDIA_HPD_NO_DETECT		(0 << 0)
3160422251b214c Anusha Srivatsa               2018-06-26   7954  #define   ICP_DDIA_HPD_SHORT_DETECT		(1 << 0)
3160422251b214c Anusha Srivatsa               2018-06-26   7955  #define   ICP_DDIA_HPD_LONG_DETECT		(2 << 0)
3160422251b214c Anusha Srivatsa               2018-06-26   7956  #define   ICP_DDIA_HPD_SHORT_LONG_DETECT	(3 << 0)
3160422251b214c Anusha Srivatsa               2018-06-26   7957  
3160422251b214c Anusha Srivatsa               2018-06-26   7958  #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
3160422251b214c Anusha Srivatsa               2018-06-26   7959  #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7960  /* Icelake DSC Rate Control Range Parameter Registers */
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7961  #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7962  #define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7963  #define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7964  #define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7965  #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7966  #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7967  #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7968  #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7969  #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7970  #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7971  #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7972  #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7973  #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7974  							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7975  							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7976  #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7977  							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7978  							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7979  #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7980  							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7981  							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7982  #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7983  							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7984  							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7985  #define RC_BPG_OFFSET_SHIFT			10
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7986  #define RC_MAX_QP_SHIFT				5
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7987  #define RC_MIN_QP_SHIFT				0
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7988  
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7989  #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7990  #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7991  #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7992  #define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7993  #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7994  #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7995  #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7996  #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7997  #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7998  #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   7999  #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8000  #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8001  #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8002  							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8003  							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8004  #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8005  							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8006  							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8007  #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8008  							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8009  							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8010  #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8011  							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8012  							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8013  
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8014  #define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8015  #define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8016  #define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8017  #define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8018  #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8019  #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8020  #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8021  #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8022  #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8023  #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8024  #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8025  #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8026  #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8027  							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8028  							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8029  #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8030  							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8031  							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8032  #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8033  							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8034  							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8035  #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8036  							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8037  							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8038  
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8039  #define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8040  #define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8041  #define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8042  #define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8043  #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8044  #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8045  #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8046  #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8047  #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8048  #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8049  #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8050  #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8051  #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8052  							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8053  							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8054  #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8055  							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8056  							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8057  #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8058  							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8059  							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8060  #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8061  							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8062  							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
c7d2959f032ddb0 Anusha Srivatsa               2018-07-17   8063  
3160422251b214c Anusha Srivatsa               2018-06-26   8064  #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
3160422251b214c Anusha Srivatsa               2018-06-26   8065  #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
3160422251b214c Anusha Srivatsa               2018-06-26   8066  
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8067  #define _PCH_DPLL_A              0xc6014
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8068  #define _PCH_DPLL_B              0xc6018
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   8069  #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8070  
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8071  #define _PCH_FPA0                0xc6040
c1858123dba4a9e Chris Wilson                  2010-12-03   8072  #define  FP_CB_TUNE		(0x3 << 22)
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8073  #define _PCH_FPA1                0xc6044
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8074  #define _PCH_FPB0                0xc6048
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8075  #define _PCH_FPB1                0xc604c
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   8076  #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   8077  #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8078  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8079  #define PCH_DPLL_TEST           _MMIO(0xc606c)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8080  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8081  #define PCH_DREF_CONTROL        _MMIO(0xC6200)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8082  #define  DREF_CONTROL_MASK      0x7fc3
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8083  #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8084  #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2 << 13)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8085  #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3 << 13)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8086  #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3 << 13)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8087  #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8088  #define  DREF_SSC_SOURCE_ENABLE                 (2 << 11)
c038e51e841581c Zhenyu Wang                   2009-10-19   8089  #define  DREF_SSC_SOURCE_MASK			(3 << 11)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8090  #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8091  #define  DREF_NONSPREAD_CK505_ENABLE		(1 << 9)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8092  #define  DREF_NONSPREAD_SOURCE_ENABLE           (2 << 9)
c038e51e841581c Zhenyu Wang                   2009-10-19   8093  #define  DREF_NONSPREAD_SOURCE_MASK		(3 << 9)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8094  #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8095  #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2 << 7)
92f2584a083986c Jesse Barnes                  2011-01-04   8096  #define  DREF_SUPERSPREAD_SOURCE_MASK		(3 << 7)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8097  #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8098  #define  DREF_SSC4_CENTERSPREAD                 (1 << 6)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8099  #define  DREF_SSC1_DISABLE                      (0 << 1)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8100  #define  DREF_SSC1_ENABLE                       (1 << 1)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8101  #define  DREF_SSC4_DISABLE                      (0)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8102  #define  DREF_SSC4_ENABLE                       (1)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8103  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8104  #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8105  #define  FDL_TP1_TIMER_SHIFT    12
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8106  #define  FDL_TP1_TIMER_MASK     (3 << 12)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8107  #define  FDL_TP2_TIMER_SHIFT    10
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8108  #define  FDL_TP2_TIMER_MASK     (3 << 10)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8109  #define  RAWCLK_FREQ_MASK       0x3ff
9d81a99713bc29b Rodrigo Vivi                  2017-06-02   8110  #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
9d81a99713bc29b Rodrigo Vivi                  2017-06-02   8111  #define  CNP_RAWCLK_DIV(div)	((div) << 16)
9d81a99713bc29b Rodrigo Vivi                  2017-06-02   8112  #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
228a5cf381f761c Paulo Zanoni                  2018-11-12   8113  #define  CNP_RAWCLK_DEN(den)	((den) << 26)
4ef99abd07ef3ce Anusha Srivatsa               2018-01-11   8114  #define  ICP_RAWCLK_NUM(num)	((num) << 11)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8115  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8116  #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8117  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8118  #define PCH_SSC4_PARMS          _MMIO(0xc6210)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8119  #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8120  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8121  #define PCH_DPLL_SEL		_MMIO(0xc7000)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   8122  #define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
1188739757d0e78 Daniel Vetter                 2013-06-05   8123  #define	 TRANS_DPLLA_SEL(pipe)		0
68d9753837db0e4 Ville Syrjälä                 2015-09-18   8124  #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8125  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8126  /* transcoder */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8127  
275f01b2694a52d Daniel Vetter                 2013-05-03   8128  #define _PCH_TRANS_HTOTAL_A		0xe0000
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8129  #define  TRANS_HTOTAL_SHIFT		16
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8130  #define  TRANS_HACTIVE_SHIFT		0
275f01b2694a52d Daniel Vetter                 2013-05-03   8131  #define _PCH_TRANS_HBLANK_A		0xe0004
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8132  #define  TRANS_HBLANK_END_SHIFT		16
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8133  #define  TRANS_HBLANK_START_SHIFT	0
275f01b2694a52d Daniel Vetter                 2013-05-03   8134  #define _PCH_TRANS_HSYNC_A		0xe0008
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8135  #define  TRANS_HSYNC_END_SHIFT		16
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8136  #define  TRANS_HSYNC_START_SHIFT	0
275f01b2694a52d Daniel Vetter                 2013-05-03   8137  #define _PCH_TRANS_VTOTAL_A		0xe000c
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8138  #define  TRANS_VTOTAL_SHIFT		16
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8139  #define  TRANS_VACTIVE_SHIFT		0
275f01b2694a52d Daniel Vetter                 2013-05-03   8140  #define _PCH_TRANS_VBLANK_A		0xe0010
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8141  #define  TRANS_VBLANK_END_SHIFT		16
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8142  #define  TRANS_VBLANK_START_SHIFT	0
275f01b2694a52d Daniel Vetter                 2013-05-03   8143  #define _PCH_TRANS_VSYNC_A		0xe0014
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8144  #define  TRANS_VSYNC_END_SHIFT		16
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8145  #define  TRANS_VSYNC_START_SHIFT	0
275f01b2694a52d Daniel Vetter                 2013-05-03   8146  #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8147  
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8148  #define _PCH_TRANSA_DATA_M1	0xe0030
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8149  #define _PCH_TRANSA_DATA_N1	0xe0034
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8150  #define _PCH_TRANSA_DATA_M2	0xe0038
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8151  #define _PCH_TRANSA_DATA_N2	0xe003c
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8152  #define _PCH_TRANSA_LINK_M1	0xe0040
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8153  #define _PCH_TRANSA_LINK_N1	0xe0044
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8154  #define _PCH_TRANSA_LINK_M2	0xe0048
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8155  #define _PCH_TRANSA_LINK_N2	0xe004c
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8156  
2dcbc34d12ba463 Ville Syrjälä                 2014-04-09   8157  /* Per-transcoder DIP controls (PCH) */
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8158  #define _VIDEO_DIP_CTL_A         0xe0200
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8159  #define _VIDEO_DIP_DATA_A        0xe0208
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8160  #define _VIDEO_DIP_GCP_A         0xe0210
6d67415f40b1f16 Ville Syrjälä                 2015-05-05   8161  #define  GCP_COLOR_INDICATION		(1 << 2)
6d67415f40b1f16 Ville Syrjälä                 2015-05-05   8162  #define  GCP_DEFAULT_PHASE_ENABLE	(1 << 1)
6d67415f40b1f16 Ville Syrjälä                 2015-05-05   8163  #define  GCP_AV_MUTE			(1 << 0)
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8164  
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8165  #define _VIDEO_DIP_CTL_B         0xe1200
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8166  #define _VIDEO_DIP_DATA_B        0xe1208
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8167  #define _VIDEO_DIP_GCP_B         0xe1210
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8168  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8169  #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8170  #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8171  #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
b055c8f3ef9f7bc Jesse Barnes                  2011-07-08   8172  
2dcbc34d12ba463 Ville Syrjälä                 2014-04-09   8173  /* Per-transcoder DIP controls (VLV) */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8174  #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8175  #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8176  #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
90b107c8f7ea75e Shobhit Kumar                 2012-03-28   8177  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8178  #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8179  #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8180  #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
90b107c8f7ea75e Shobhit Kumar                 2012-03-28   8181  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8182  #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8183  #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8184  #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
2dcbc34d12ba463 Ville Syrjälä                 2014-04-09   8185  
90b107c8f7ea75e Shobhit Kumar                 2012-03-28   8186  #define VLV_TVIDEO_DIP_CTL(pipe) \
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8187  	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8188  	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
90b107c8f7ea75e Shobhit Kumar                 2012-03-28   8189  #define VLV_TVIDEO_DIP_DATA(pipe) \
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8190  	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8191  	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
90b107c8f7ea75e Shobhit Kumar                 2012-03-28   8192  #define VLV_TVIDEO_DIP_GCP(pipe) \
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8193  	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8194  		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
90b107c8f7ea75e Shobhit Kumar                 2012-03-28   8195  
8c5f5f7c42e009b Eugeni Dodonov                2012-05-10   8196  /* Haswell DIP controls */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8197  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8198  #define _HSW_VIDEO_DIP_CTL_A		0x60200
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8199  #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8200  #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8201  #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8202  #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8203  #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
44b42ebfccfd9d6 Ville Syrjälä                 2019-05-17   8204  #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8205  #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8206  #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8207  #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8208  #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8209  #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8210  #define _HSW_VIDEO_DIP_GCP_A		0x60210
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8211  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8212  #define _HSW_VIDEO_DIP_CTL_B		0x61200
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8213  #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8214  #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8215  #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8216  #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8217  #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
44b42ebfccfd9d6 Ville Syrjälä                 2019-05-17   8218  #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8219  #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8220  #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8221  #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8222  #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8223  #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8224  #define _HSW_VIDEO_DIP_GCP_B		0x61210
8c5f5f7c42e009b Eugeni Dodonov                2012-05-10   8225  
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8226  /* Icelake PPS_DATA and _ECC DIP Registers.
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8227   * These are available for transcoders B,C and eDP.
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8228   * Adding the _A so as to reuse the _MMIO_TRANS2
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8229   * definition, with which it offsets to the right location.
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8230   */
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8231  
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8232  #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8233  #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8234  #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8235  #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8236  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8237  #define HSW_TVIDEO_DIP_CTL(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
5cb3c1a123fc337 Ville Syrjälä                 2019-02-25   8238  #define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8239  #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8240  #define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8241  #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
5cb3c1a123fc337 Ville Syrjälä                 2019-02-25   8242  #define HSW_TVIDEO_DIP_GMP_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8243  #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
44b42ebfccfd9d6 Ville Syrjälä                 2019-05-17   8244  #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)	_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8245  #define ICL_VIDEO_DIP_PPS_DATA(trans, i)	_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
7af2be6d54d4eda Anusha Srivatsa               2018-07-17   8246  #define ICL_VIDEO_DIP_PPS_ECC(trans, i)		_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8c5f5f7c42e009b Eugeni Dodonov                2012-05-10   8247  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8248  #define _HSW_STEREO_3D_CTL_A		0x70020
3f51e4713fc57ab Rodrigo Vivi                  2013-07-11   8249  #define   S3D_ENABLE			(1 << 31)
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8250  #define _HSW_STEREO_3D_CTL_B		0x71020
3f51e4713fc57ab Rodrigo Vivi                  2013-07-11   8251  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8252  #define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
3f51e4713fc57ab Rodrigo Vivi                  2013-07-11   8253  
275f01b2694a52d Daniel Vetter                 2013-05-03   8254  #define _PCH_TRANS_HTOTAL_B          0xe1000
275f01b2694a52d Daniel Vetter                 2013-05-03   8255  #define _PCH_TRANS_HBLANK_B          0xe1004
275f01b2694a52d Daniel Vetter                 2013-05-03   8256  #define _PCH_TRANS_HSYNC_B           0xe1008
275f01b2694a52d Daniel Vetter                 2013-05-03   8257  #define _PCH_TRANS_VTOTAL_B          0xe100c
275f01b2694a52d Daniel Vetter                 2013-05-03   8258  #define _PCH_TRANS_VBLANK_B          0xe1010
275f01b2694a52d Daniel Vetter                 2013-05-03   8259  #define _PCH_TRANS_VSYNC_B           0xe1014
275f01b2694a52d Daniel Vetter                 2013-05-03   8260  #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
275f01b2694a52d Daniel Vetter                 2013-05-03   8261  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8262  #define PCH_TRANS_HTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8263  #define PCH_TRANS_HBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8264  #define PCH_TRANS_HSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8265  #define PCH_TRANS_VTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8266  #define PCH_TRANS_VBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8267  #define PCH_TRANS_VSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8268  #define PCH_TRANS_VSYNCSHIFT(pipe)	_MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8269  
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8270  #define _PCH_TRANSB_DATA_M1	0xe1030
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8271  #define _PCH_TRANSB_DATA_N1	0xe1034
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8272  #define _PCH_TRANSB_DATA_M2	0xe1038
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8273  #define _PCH_TRANSB_DATA_N2	0xe103c
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8274  #define _PCH_TRANSB_LINK_M1	0xe1040
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8275  #define _PCH_TRANSB_LINK_N1	0xe1044
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8276  #define _PCH_TRANSB_LINK_M2	0xe1048
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8277  #define _PCH_TRANSB_LINK_N2	0xe104c
e3b95f1eb5b9a7e Daniel Vetter                 2013-05-03   8278  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8279  #define PCH_TRANS_DATA_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8280  #define PCH_TRANS_DATA_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8281  #define PCH_TRANS_DATA_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8282  #define PCH_TRANS_DATA_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8283  #define PCH_TRANS_LINK_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8284  #define PCH_TRANS_LINK_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8285  #define PCH_TRANS_LINK_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8286  #define PCH_TRANS_LINK_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8287  
ab9412ba06484cd Daniel Vetter                 2013-05-03   8288  #define _PCH_TRANSACONF              0xf0008
ab9412ba06484cd Daniel Vetter                 2013-05-03   8289  #define _PCH_TRANSBCONF              0xf1008
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8290  #define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8291  #define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8292  #define  TRANS_DISABLE          (0 << 31)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8293  #define  TRANS_ENABLE           (1 << 31)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8294  #define  TRANS_STATE_MASK       (1 << 30)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8295  #define  TRANS_STATE_DISABLE    (0 << 30)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8296  #define  TRANS_STATE_ENABLE     (1 << 30)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8297  #define  TRANS_FSYNC_DELAY_HB1  (0 << 27)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8298  #define  TRANS_FSYNC_DELAY_HB2  (1 << 27)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8299  #define  TRANS_FSYNC_DELAY_HB3  (2 << 27)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8300  #define  TRANS_FSYNC_DELAY_HB4  (3 << 27)
5f7f726d2caf1e5 Paulo Zanoni                  2012-02-03   8301  #define  TRANS_INTERLACE_MASK   (7 << 21)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8302  #define  TRANS_PROGRESSIVE      (0 << 21)
5f7f726d2caf1e5 Paulo Zanoni                  2012-02-03   8303  #define  TRANS_INTERLACED       (3 << 21)
7c26e5c6edaec70 Paulo Zanoni                  2012-02-14   8304  #define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8305  #define  TRANS_8BPC             (0 << 5)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8306  #define  TRANS_10BPC            (1 << 5)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8307  #define  TRANS_6BPC             (2 << 5)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8308  #define  TRANS_12BPC            (3 << 5)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8309  
ce40141f55fa68f Daniel Vetter                 2012-10-31   8310  #define _TRANSA_CHICKEN1	 0xf0060
ce40141f55fa68f Daniel Vetter                 2012-10-31   8311  #define _TRANSB_CHICKEN1	 0xf1060
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8312  #define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
d1b1589c4800678 Ville Syrjälä                 2015-05-05   8313  #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1 << 10)
ce40141f55fa68f Daniel Vetter                 2012-10-31   8314  #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1 << 4)
3bcf603f6d5d18b Jesse Barnes                  2011-07-27   8315  #define _TRANSA_CHICKEN2	 0xf0064
3bcf603f6d5d18b Jesse Barnes                  2011-07-27   8316  #define _TRANSB_CHICKEN2	 0xf1064
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8317  #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
23670b322c100c8 Daniel Vetter                 2012-11-01   8318  #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1 << 31)
3f704fa2778d3fe Paulo Zanoni                  2013-04-08   8319  #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1 << 29)
dc4bd2d1095d0a7 Paulo Zanoni                  2013-04-08   8320  #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3 << 27)
dc4bd2d1095d0a7 Paulo Zanoni                  2013-04-08   8321  #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1 << 26)
dc4bd2d1095d0a7 Paulo Zanoni                  2013-04-08   8322  #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1 << 25)
3bcf603f6d5d18b Jesse Barnes                  2011-07-27   8323  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8324  #define SOUTH_CHICKEN1		_MMIO(0xc2000)
291427f5fdadec6 Jesse Barnes                  2011-07-29   8325  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
291427f5fdadec6 Jesse Barnes                  2011-07-29   8326  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
291427f5fdadec6 Jesse Barnes                  2011-07-29   8327  #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
291427f5fdadec6 Jesse Barnes                  2011-07-29   8328  #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
01a415fd026c1a4 Daniel Vetter                 2012-10-27   8329  #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
3b92e263dd4a38f Rodrigo Vivi                  2017-09-19   8330  #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
3b92e263dd4a38f Rodrigo Vivi                  2017-09-19   8331  #define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
aa17cdb4f836787 Jani Nikula                   2015-09-04   8332  #define  SPT_PWM_GRANULARITY		(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8333  #define SOUTH_CHICKEN2		_MMIO(0xc2004)
dde86e2db54545e Paulo Zanoni                  2012-12-01   8334  #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
dde86e2db54545e Paulo Zanoni                  2012-12-01   8335  #define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
aa17cdb4f836787 Jani Nikula                   2015-09-04   8336  #define  LPT_PWM_GRANULARITY		(1 << 5)
645c62a5e95a5f9 Jesse Barnes                  2011-05-11   8337  #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
645c62a5e95a5f9 Jesse Barnes                  2011-05-11   8338  
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8339  #define _FDI_RXA_CHICKEN        0xc200c
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8340  #define _FDI_RXB_CHICKEN        0xc2010
6f06ce184c765fd Jesse Barnes                  2011-01-04   8341  #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1 << 1)
6f06ce184c765fd Jesse Barnes                  2011-01-04   8342  #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8343  #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8344  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8345  #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
6481d5ed076e69d Ville Syrjälä                 2017-12-21   8346  #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
cd6640781086970 Jesse Barnes                  2013-10-02   8347  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
382b09362711d7d Jesse Barnes                  2010-10-07   8348  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
cd6640781086970 Jesse Barnes                  2013-10-02   8349  #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
0a46ddd57c9ef9f Rodrigo Vivi                  2017-08-30   8350  #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
17a303ec7cd5a24 Paulo Zanoni                  2012-11-20   8351  #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
382b09362711d7d Jesse Barnes                  2010-10-07   8352  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8353  /* CPU: FDI_TX */
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8354  #define _FDI_TXA_CTL            0x60100
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8355  #define _FDI_TXB_CTL            0x61100
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8356  #define FDI_TX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8357  #define  FDI_TX_DISABLE         (0 << 31)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8358  #define  FDI_TX_ENABLE          (1 << 31)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8359  #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8360  #define  FDI_LINK_TRAIN_PATTERN_2       (1 << 28)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8361  #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2 << 28)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8362  #define  FDI_LINK_TRAIN_NONE            (3 << 28)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8363  #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8364  #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1 << 25)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8365  #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2 << 25)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8366  #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3 << 25)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8367  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8368  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8369  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2 << 22)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8370  #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8371  /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8372     SNB has different settings. */
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8373  /* SNB A-stepping */
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8374  #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8375  #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8376  #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8377  #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8378  /* SNB B-stepping */
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8379  #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8380  #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8381  #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8382  #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8383  #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
627eb5a318a6cac Daniel Vetter                 2013-04-29   8384  #define  FDI_DP_PORT_WIDTH_SHIFT		19
627eb5a318a6cac Daniel Vetter                 2013-04-29   8385  #define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
627eb5a318a6cac Daniel Vetter                 2013-04-29   8386  #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8387  #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1 << 18)
f2b115e69d46344 Adam Jackson                  2009-12-03   8388  /* Ironlake: hardwired to 1 */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8389  #define  FDI_TX_PLL_ENABLE              (1 << 14)
357555c00f84140 Jesse Barnes                  2011-04-28   8390  
357555c00f84140 Jesse Barnes                  2011-04-28   8391  /* Ivybridge has different bits for lolz */
357555c00f84140 Jesse Barnes                  2011-04-28   8392  #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
357555c00f84140 Jesse Barnes                  2011-04-28   8393  #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1 << 8)
357555c00f84140 Jesse Barnes                  2011-04-28   8394  #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2 << 8)
357555c00f84140 Jesse Barnes                  2011-04-28   8395  #define  FDI_LINK_TRAIN_NONE_IVB            (3 << 8)
357555c00f84140 Jesse Barnes                  2011-04-28   8396  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8397  /* both Tx and Rx */
c4f9c4c2b3f1831 Jesse Barnes                  2011-10-10   8398  #define  FDI_COMPOSITE_SYNC		(1 << 11)
357555c00f84140 Jesse Barnes                  2011-04-28   8399  #define  FDI_LINK_TRAIN_AUTO		(1 << 10)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8400  #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8401  #define  FDI_SCRAMBLING_DISABLE         (1 << 7)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8402  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8403  /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8404  #define _FDI_RXA_CTL             0xf000c
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8405  #define _FDI_RXB_CTL             0xf100c
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8406  #define FDI_RX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8407  #define  FDI_RX_ENABLE          (1 << 31)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8408  /* train, dp width same as FDI_TX */
357555c00f84140 Jesse Barnes                  2011-04-28   8409  #define  FDI_FS_ERRC_ENABLE		(1 << 27)
357555c00f84140 Jesse Barnes                  2011-04-28   8410  #define  FDI_FE_ERRC_ENABLE		(1 << 26)
68d18ad7fbc1628 Paulo Zanoni                  2012-12-01   8411  #define  FDI_RX_POLARITY_REVERSED_LPT	(1 << 16)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8412  #define  FDI_8BPC                       (0 << 16)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8413  #define  FDI_10BPC                      (1 << 16)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8414  #define  FDI_6BPC                       (2 << 16)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8415  #define  FDI_12BPC                      (3 << 16)
3e68320ef845286 Damien Lespiau                2012-12-11   8416  #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1 << 15)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8417  #define  FDI_DMI_LINK_REVERSE_MASK      (1 << 14)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8418  #define  FDI_RX_PLL_ENABLE              (1 << 13)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8419  #define  FDI_FS_ERR_CORRECT_ENABLE      (1 << 11)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8420  #define  FDI_FE_ERR_CORRECT_ENABLE      (1 << 10)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8421  #define  FDI_FS_ERR_REPORT_ENABLE       (1 << 9)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8422  #define  FDI_FE_ERR_REPORT_ENABLE       (1 << 8)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8423  #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1 << 6)
5eddb70ba2b8cdb Chris Wilson                  2010-09-11   8424  #define  FDI_PCDCLK	                (1 << 4)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8425  /* CPT */
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8426  #define  FDI_AUTO_TRAINING			(1 << 10)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8427  #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8428  #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8429  #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8430  #define  FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8431  #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8432  
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8433  #define _FDI_RXA_MISC			0xf0010
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8434  #define _FDI_RXB_MISC			0xf1010
049456416f74a4a Paulo Zanoni                  2012-11-01   8435  #define  FDI_RX_PWRDN_LANE1_MASK	(3 << 26)
049456416f74a4a Paulo Zanoni                  2012-11-01   8436  #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x) << 26)
049456416f74a4a Paulo Zanoni                  2012-11-01   8437  #define  FDI_RX_PWRDN_LANE0_MASK	(3 << 24)
049456416f74a4a Paulo Zanoni                  2012-11-01   8438  #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x) << 24)
4acf518626cdad5 Eugeni Dodonov                2012-07-04   8439  #define  FDI_RX_TP1_TO_TP2_48		(2 << 20)
4acf518626cdad5 Eugeni Dodonov                2012-07-04   8440  #define  FDI_RX_TP1_TO_TP2_64		(3 << 20)
4acf518626cdad5 Eugeni Dodonov                2012-07-04   8441  #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8442  #define FDI_RX_MISC(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
049456416f74a4a Paulo Zanoni                  2012-11-01   8443  
049456416f74a4a Paulo Zanoni                  2012-11-01   8444  #define _FDI_RXA_TUSIZE1        0xf0030
049456416f74a4a Paulo Zanoni                  2012-11-01   8445  #define _FDI_RXA_TUSIZE2        0xf0038
049456416f74a4a Paulo Zanoni                  2012-11-01   8446  #define _FDI_RXB_TUSIZE1        0xf1030
049456416f74a4a Paulo Zanoni                  2012-11-01   8447  #define _FDI_RXB_TUSIZE2        0xf1038
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8448  #define FDI_RX_TUSIZE1(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8449  #define FDI_RX_TUSIZE2(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8450  
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8451  /* FDI_RX interrupt register format */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8452  #define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8453  #define FDI_RX_SYMBOL_LOCK              (1 << 9) /* train 2 */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8454  #define FDI_RX_BIT_LOCK                 (1 << 8) /* train 1 */
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8455  #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8456  #define FDI_RX_FS_CODE_ERR              (1 << 6)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8457  #define FDI_RX_FE_CODE_ERR              (1 << 5)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8458  #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8459  #define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8460  #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8461  #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8462  #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8463  
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8464  #define _FDI_RXA_IIR            0xf0014
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8465  #define _FDI_RXA_IMR            0xf0018
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8466  #define _FDI_RXB_IIR            0xf1014
9db4a9c7b2a3bd5 Jesse Barnes                  2011-02-07   8467  #define _FDI_RXB_IMR            0xf1018
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8468  #define FDI_RX_IIR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8469  #define FDI_RX_IMR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8470  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8471  #define FDI_PLL_CTL_1           _MMIO(0xfe000)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8472  #define FDI_PLL_CTL_2           _MMIO(0xfe004)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8473  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8474  #define PCH_LVDS	_MMIO(0xe1180)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8475  #define  LVDS_DETECTED	(1 << 1)
b9055052d3e0388 Zhenyu Wang                   2009-06-05   8476  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8477  #define _PCH_DP_B		0xe4100
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8478  #define PCH_DP_B		_MMIO(_PCH_DP_B)
750a951fd34808d Ville Syrjälä                 2015-11-11   8479  #define _PCH_DPB_AUX_CH_CTL	0xe4110
750a951fd34808d Ville Syrjälä                 2015-11-11   8480  #define _PCH_DPB_AUX_CH_DATA1	0xe4114
750a951fd34808d Ville Syrjälä                 2015-11-11   8481  #define _PCH_DPB_AUX_CH_DATA2	0xe4118
750a951fd34808d Ville Syrjälä                 2015-11-11   8482  #define _PCH_DPB_AUX_CH_DATA3	0xe411c
750a951fd34808d Ville Syrjälä                 2015-11-11   8483  #define _PCH_DPB_AUX_CH_DATA4	0xe4120
750a951fd34808d Ville Syrjälä                 2015-11-11   8484  #define _PCH_DPB_AUX_CH_DATA5	0xe4124
5eb08b69f510fad Zhenyu Wang                   2009-07-24   8485  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8486  #define _PCH_DP_C		0xe4200
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8487  #define PCH_DP_C		_MMIO(_PCH_DP_C)
750a951fd34808d Ville Syrjälä                 2015-11-11   8488  #define _PCH_DPC_AUX_CH_CTL	0xe4210
750a951fd34808d Ville Syrjälä                 2015-11-11   8489  #define _PCH_DPC_AUX_CH_DATA1	0xe4214
750a951fd34808d Ville Syrjälä                 2015-11-11   8490  #define _PCH_DPC_AUX_CH_DATA2	0xe4218
750a951fd34808d Ville Syrjälä                 2015-11-11   8491  #define _PCH_DPC_AUX_CH_DATA3	0xe421c
750a951fd34808d Ville Syrjälä                 2015-11-11   8492  #define _PCH_DPC_AUX_CH_DATA4	0xe4220
750a951fd34808d Ville Syrjälä                 2015-11-11   8493  #define _PCH_DPC_AUX_CH_DATA5	0xe4224
5eb08b69f510fad Zhenyu Wang                   2009-07-24   8494  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8495  #define _PCH_DP_D		0xe4300
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8496  #define PCH_DP_D		_MMIO(_PCH_DP_D)
750a951fd34808d Ville Syrjälä                 2015-11-11   8497  #define _PCH_DPD_AUX_CH_CTL	0xe4310
750a951fd34808d Ville Syrjälä                 2015-11-11   8498  #define _PCH_DPD_AUX_CH_DATA1	0xe4314
750a951fd34808d Ville Syrjälä                 2015-11-11   8499  #define _PCH_DPD_AUX_CH_DATA2	0xe4318
750a951fd34808d Ville Syrjälä                 2015-11-11   8500  #define _PCH_DPD_AUX_CH_DATA3	0xe431c
750a951fd34808d Ville Syrjälä                 2015-11-11   8501  #define _PCH_DPD_AUX_CH_DATA4	0xe4320
750a951fd34808d Ville Syrjälä                 2015-11-11   8502  #define _PCH_DPD_AUX_CH_DATA5	0xe4324
750a951fd34808d Ville Syrjälä                 2015-11-11   8503  
bdabdb635010a3b Ville Syrjälä                 2018-02-22   8504  #define PCH_DP_AUX_CH_CTL(aux_ch)		_MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
bdabdb635010a3b Ville Syrjälä                 2018-02-22   8505  #define PCH_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5eb08b69f510fad Zhenyu Wang                   2009-07-24   8506  
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8507  /* CPT */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8508  #define _TRANS_DP_CTL_A		0xe0300
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8509  #define _TRANS_DP_CTL_B		0xe1300
086f8e84a085a43 Ville Syrjälä                 2015-11-04   8510  #define _TRANS_DP_CTL_C		0xe2300
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8511  #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8512  #define  TRANS_DP_OUTPUT_ENABLE	(1 << 31)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8513  #define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
f67dc6d8869fd29 Ville Syrjälä                 2018-05-18   8514  #define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
f67dc6d8869fd29 Ville Syrjälä                 2018-05-18   8515  #define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8516  #define  TRANS_DP_AUDIO_ONLY	(1 << 26)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8517  #define  TRANS_DP_ENH_FRAMING	(1 << 18)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8518  #define  TRANS_DP_8BPC		(0 << 9)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8519  #define  TRANS_DP_10BPC		(1 << 9)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8520  #define  TRANS_DP_6BPC		(2 << 9)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8521  #define  TRANS_DP_12BPC		(3 << 9)
220cad3cbf553f8 Eric Anholt                   2010-11-18   8522  #define  TRANS_DP_BPC_MASK	(3 << 9)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8523  #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1 << 4)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8524  #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8525  #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1 << 3)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8526  #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
94113cecaea5067 Chris Wilson                  2010-08-04   8527  #define  TRANS_DP_SYNC_MASK	(3 << 3)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8528  
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8529  /* SNB eDP training params */
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8530  /* SNB A-stepping */
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8531  #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8532  #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8533  #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8534  #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8535  /* SNB B-stepping */
3c5a62b5226ca5d Yuanhan Liu                   2011-01-06   8536  #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
3c5a62b5226ca5d Yuanhan Liu                   2011-01-06   8537  #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
3c5a62b5226ca5d Yuanhan Liu                   2011-01-06   8538  #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
3c5a62b5226ca5d Yuanhan Liu                   2011-01-06   8539  #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
3c5a62b5226ca5d Yuanhan Liu                   2011-01-06   8540  #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8541  #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
8db9d77b1b14fd7 Zhenyu Wang                   2010-04-07   8542  
1a2eb4604b85c5e Keith Packard                 2011-11-16   8543  /* IVB */
1a2eb4604b85c5e Keith Packard                 2011-11-16   8544  #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8545  #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8546  #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8547  #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8548  #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8549  #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
77fa4cbd5fa389e Imre Deak                     2013-08-23   8550  #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8551  
1a2eb4604b85c5e Keith Packard                 2011-11-16   8552  /* legacy values */
1a2eb4604b85c5e Keith Packard                 2011-11-16   8553  #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8554  #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8555  #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8556  #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8557  #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8558  
1a2eb4604b85c5e Keith Packard                 2011-11-16   8559  #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
1a2eb4604b85c5e Keith Packard                 2011-11-16   8560  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8561  #define  VLV_PMWGICZ				_MMIO(0x1300a4)
9e72b46c0d92735 Imre Deak                     2014-05-05   8562  
274008e89d78ded Sagar Arun Kamble             2016-02-06   8563  #define  RC6_LOCATION				_MMIO(0xD40)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8564  #define	   RC6_CTX_IN_DRAM			(1 << 0)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8565  #define  RC6_CTX_BASE				_MMIO(0xD48)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8566  #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
274008e89d78ded Sagar Arun Kamble             2016-02-06   8567  #define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8568  #define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8569  #define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8570  #define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8571  #define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
274008e89d78ded Sagar Arun Kamble             2016-02-06   8572  #define    IDLE_TIME_MASK			0xFFFFF
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8573  #define  FORCEWAKE				_MMIO(0xA18C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8574  #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8575  #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8576  #define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8577  #define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8578  #define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8579  #define  FORCEWAKE_ACK				_MMIO(0x130090)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8580  #define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8581  #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8582  #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8583  #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8584  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8585  #define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8586  #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8587  #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8588  #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
981a5aead1fcfe3 Imre Deak                     2014-04-14   8589  #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8590  #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8591  #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
a89a70a8b50d672 Daniele Ceraolo Spurio        2018-03-02   8592  #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
a89a70a8b50d672 Daniele Ceraolo Spurio        2018-03-02   8593  #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8594  #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8595  #define  FORCEWAKE_BLITTER_GEN9			_MMIO(0xa188)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8596  #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
a89a70a8b50d672 Daniele Ceraolo Spurio        2018-03-02   8597  #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
a89a70a8b50d672 Daniele Ceraolo Spurio        2018-03-02   8598  #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8599  #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8600  #define  FORCEWAKE_ACK_BLITTER_GEN9		_MMIO(0x130044)
7130630323c5625 Mika Kuoppala                 2017-11-02   8601  #define   FORCEWAKE_KERNEL			BIT(0)
7130630323c5625 Mika Kuoppala                 2017-11-02   8602  #define   FORCEWAKE_USER			BIT(1)
7130630323c5625 Mika Kuoppala                 2017-11-02   8603  #define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8604  #define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8605  #define  ECOBUS					_MMIO(0xa180)
8d715f0024f64ad Keith Packard                 2011-11-18   8606  #define    FORCEWAKE_MT_ENABLE			(1 << 5)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8607  #define  VLV_SPAREG2H				_MMIO(0xA194)
f2dd7578c4f4ea9 Akash Goel                    2016-06-27   8608  #define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
f2dd7578c4f4ea9 Akash Goel                    2016-06-27   8609  #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
f2dd7578c4f4ea9 Akash Goel                    2016-06-27   8610  #define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8611  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8612  #define  GTFIFODBG				_MMIO(0x120000)
297b32ec7e9a207 Ville Syrjälä                 2016-04-13   8613  #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
297b32ec7e9a207 Ville Syrjälä                 2016-04-13   8614  #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
90f256b5bbdd5c6 Ville Syrjälä                 2013-11-14   8615  #define    GT_FIFO_SBDROPERR			(1 << 6)
90f256b5bbdd5c6 Ville Syrjälä                 2013-11-14   8616  #define    GT_FIFO_BLOBDROPERR			(1 << 5)
90f256b5bbdd5c6 Ville Syrjälä                 2013-11-14   8617  #define    GT_FIFO_SB_READ_ABORTERR		(1 << 4)
90f256b5bbdd5c6 Ville Syrjälä                 2013-11-14   8618  #define    GT_FIFO_DROPERR			(1 << 3)
dd202c6dd612bee Ben Widawsky                  2012-02-09   8619  #define    GT_FIFO_OVFERR			(1 << 2)
dd202c6dd612bee Ben Widawsky                  2012-02-09   8620  #define    GT_FIFO_IAWRERR			(1 << 1)
dd202c6dd612bee Ben Widawsky                  2012-02-09   8621  #define    GT_FIFO_IARDERR			(1 << 0)
dd202c6dd612bee Ben Widawsky                  2012-02-09   8622  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8623  #define  GTFIFOCTL				_MMIO(0x120008)
46520e2baa861a0 Ville Syrjälä                 2013-11-14   8624  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
95736720fc866ea Chris Wilson                  2011-05-12   8625  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
a04f90a33fab747 Deepak S                      2015-04-16   8626  #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
a04f90a33fab747 Deepak S                      2015-04-16   8627  #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
91355834646328e Chris Wilson                  2011-03-04   8628  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8629  #define  HSW_IDICR				_MMIO(0x9008)
05e21cc43da5a1a Ben Widawsky                  2013-07-04   8630  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
3accaf7e734d691 Mika Kuoppala                 2016-04-13   8631  #define  HSW_EDRAM_CAP				_MMIO(0x120010)
2db59d530777b76 Damien Lespiau                2015-02-03   8632  #define    EDRAM_ENABLED			0x1
c02e85a06e191f9 Mika Kuoppala                 2016-04-13   8633  #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
c02e85a06e191f9 Mika Kuoppala                 2016-04-13   8634  #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
c02e85a06e191f9 Mika Kuoppala                 2016-04-13   8635  #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
05e21cc43da5a1a Ben Widawsky                  2013-07-04   8636  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8637  #define GEN6_UCGCTL1				_MMIO(0x9400)
8aeb7f624fbf8a6 Mika Kuoppala                 2016-06-07   8638  # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE		(1 << 22)
e4443e459ccf43f Ville Syrjälä                 2014-04-09   8639  # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
80e829fade4eea5 Daniel Vetter                 2012-03-31   8640  # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
de4a8bd16205283 Daniel Vetter                 2012-04-11   8641  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
80e829fade4eea5 Daniel Vetter                 2012-03-31   8642  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8643  #define GEN6_UCGCTL2				_MMIO(0x9404)
f9fc42f4bd9a6b9 Damien Lespiau                2015-02-26   8644  # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
0f846f81a154cc1 Jesse Barnes                  2012-06-14   8645  # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
6edaa7fcf287b92 Jesse Barnes                  2012-06-14   8646  # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
eae66b50c760233 Eugeni Dodonov                2012-02-08   8647  # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
406478dc911e166 Eric Anholt                   2011-11-07   8648  # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
9ca1d10d748e569 Eric Anholt                   2011-11-07   8649  # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
406478dc911e166 Eric Anholt                   2011-11-07   8650  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8651  #define GEN6_UCGCTL3				_MMIO(0x9408)
d79651522e89c4f Robert Bragg                  2016-11-07   8652  # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE		(1 << 20)
9e72b46c0d92735 Imre Deak                     2014-05-05   8653  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8654  #define GEN7_UCGCTL4				_MMIO(0x940c)
e3f33d46fd91774 Jesse Barnes                  2012-06-14   8655  #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1 << 25)
eee8efb02a0f928 Mika Kuoppala                 2016-06-07   8656  #define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE	(1 << 14)
e3f33d46fd91774 Jesse Barnes                  2012-06-14   8657  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8658  #define GEN6_RCGCTL1				_MMIO(0x9410)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8659  #define GEN6_RCGCTL2				_MMIO(0x9414)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8660  #define GEN6_RSTCTL				_MMIO(0x9420)
9e72b46c0d92735 Imre Deak                     2014-05-05   8661  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8662  #define GEN8_UCGCTL6				_MMIO(0x9430)
9253c2e56b83dcc Damien Lespiau                2015-02-09   8663  #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1 << 24)
4f1ca9e94057de0 Ville Syrjälä                 2014-02-27   8664  #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1 << 14)
868434c51ec13c7 Ben Widawsky                  2015-03-11   8665  #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
4f1ca9e94057de0 Ville Syrjälä                 2014-02-27   8666  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8667  #define GEN6_GFXPAUSE				_MMIO(0xA000)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8668  #define GEN6_RPNSWREQ				_MMIO(0xA008)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8669  #define   GEN6_TURBO_DISABLE			(1 << 31)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8670  #define   GEN6_FREQUENCY(x)			((x) << 25)
92bd1bf089762df Rodrigo Vivi                  2013-03-25   8671  #define   HSW_FREQUENCY(x)			((x) << 24)
de43ae9dd263d50 Akash Goel                    2015-03-06   8672  #define   GEN9_FREQUENCY(x)			((x) << 23)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8673  #define   GEN6_OFFSET(x)			((x) << 19)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8674  #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8675  #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8676  #define GEN6_RC_CONTROL				_MMIO(0xA090)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8677  #define   GEN6_RC_CTL_RC6pp_ENABLE		(1 << 16)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8678  #define   GEN6_RC_CTL_RC6p_ENABLE		(1 << 17)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8679  #define   GEN6_RC_CTL_RC6_ENABLE		(1 << 18)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8680  #define   GEN6_RC_CTL_RC1e_ENABLE		(1 << 20)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8681  #define   GEN6_RC_CTL_RC7_ENABLE		(1 << 22)
6b88f295690d334 Jesse Barnes                  2013-11-15   8682  #define   VLV_RC_CTL_CTX_RST_PARALLEL		(1 << 24)
0a073b843bcd9a6 Jesse Barnes                  2013-04-17   8683  #define   GEN7_RC_CTL_TO_MODE			(1 << 28)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8684  #define   GEN6_RC_CTL_EI_MODE(x)		((x) << 27)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8685  #define   GEN6_RC_CTL_HW_ENABLE			(1 << 31)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8686  #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8687  #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8688  #define GEN6_RPSTAT1				_MMIO(0xA01C)
ccab5c82759e2ac Jesse Barnes                  2011-01-18   8689  #define   GEN6_CAGF_SHIFT			8
f82855d342b6c84 Ben Widawsky                  2013-01-29   8690  #define   HSW_CAGF_SHIFT			7
de43ae9dd263d50 Akash Goel                    2015-03-06   8691  #define   GEN9_CAGF_SHIFT			23
ccab5c82759e2ac Jesse Barnes                  2011-01-18   8692  #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
f82855d342b6c84 Ben Widawsky                  2013-01-29   8693  #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
de43ae9dd263d50 Akash Goel                    2015-03-06   8694  #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8695  #define GEN6_RP_CONTROL				_MMIO(0xA024)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8696  #define   GEN6_RP_MEDIA_TURBO			(1 << 11)
6ed55ee7da15329 Ben Widawsky                  2011-12-12   8697  #define   GEN6_RP_MEDIA_MODE_MASK		(3 << 9)
6ed55ee7da15329 Ben Widawsky                  2011-12-12   8698  #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3 << 9)
6ed55ee7da15329 Ben Widawsky                  2011-12-12   8699  #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2 << 9)
6ed55ee7da15329 Ben Widawsky                  2011-12-12   8700  #define   GEN6_RP_MEDIA_HW_MODE			(1 << 9)
6ed55ee7da15329 Ben Widawsky                  2011-12-12   8701  #define   GEN6_RP_MEDIA_SW_MODE			(0 << 9)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8702  #define   GEN6_RP_MEDIA_IS_GFX			(1 << 8)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8703  #define   GEN6_RP_ENABLE			(1 << 7)
ccab5c82759e2ac Jesse Barnes                  2011-01-18   8704  #define   GEN6_RP_UP_IDLE_MIN			(0x1 << 3)
ccab5c82759e2ac Jesse Barnes                  2011-01-18   8705  #define   GEN6_RP_UP_BUSY_AVG			(0x2 << 3)
ccab5c82759e2ac Jesse Barnes                  2011-01-18   8706  #define   GEN6_RP_UP_BUSY_CONT			(0x4 << 3)
dd75fdc8c69587c Chris Wilson                  2013-09-25   8707  #define   GEN6_RP_DOWN_IDLE_AVG			(0x2 << 0)
ccab5c82759e2ac Jesse Barnes                  2011-01-18   8708  #define   GEN6_RP_DOWN_IDLE_CONT		(0x1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8709  #define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8710  #define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8711  #define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
7466c291b1d2fa3 Chris Wilson                  2016-08-15   8712  #define   GEN6_RP_EI_MASK			0xffffff
7466c291b1d2fa3 Chris Wilson                  2016-08-15   8713  #define   GEN6_CURICONT_MASK			GEN6_RP_EI_MASK
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8714  #define GEN6_RP_CUR_UP				_MMIO(0xA054)
7466c291b1d2fa3 Chris Wilson                  2016-08-15   8715  #define   GEN6_CURBSYTAVG_MASK			GEN6_RP_EI_MASK
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8716  #define GEN6_RP_PREV_UP				_MMIO(0xA058)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8717  #define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
7466c291b1d2fa3 Chris Wilson                  2016-08-15   8718  #define   GEN6_CURIAVG_MASK			GEN6_RP_EI_MASK
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8719  #define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8720  #define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8721  #define GEN6_RP_UP_EI				_MMIO(0xA068)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8722  #define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8723  #define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8724  #define GEN6_RPDEUHWTC				_MMIO(0xA080)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8725  #define GEN6_RPDEUC				_MMIO(0xA084)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8726  #define GEN6_RPDEUCSW				_MMIO(0xA088)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8727  #define GEN6_RC_STATE				_MMIO(0xA094)
fc6198417264e75 Imre Deak                     2016-06-29   8728  #define   RC_SW_TARGET_STATE_SHIFT		16
fc6198417264e75 Imre Deak                     2016-06-29   8729  #define   RC_SW_TARGET_STATE_MASK		(7 << RC_SW_TARGET_STATE_SHIFT)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8730  #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8731  #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8732  #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
0aab201b4ad10fa Rodrigo Vivi                  2017-10-23   8733  #define GEN10_MEDIA_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8734  #define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8735  #define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8736  #define GEN6_RC_SLEEP				_MMIO(0xA0B0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8737  #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8738  #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8739  #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8740  #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8741  #define VLV_RCEDATA				_MMIO(0xA0BC)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8742  #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8743  #define GEN6_PMINTRMSK				_MMIO(0xA168)
655d49ef77fa8d5 Chris Wilson                  2017-03-12   8744  #define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC	(1 << 31)
9735b04d0c1b766 Sagar Arun Kamble             2017-03-07   8745  #define   ARAT_EXPIRED_INTRMSK			(1 << 9)
fc6198417264e75 Imre Deak                     2016-06-29   8746  #define GEN8_MISC_CTRL0				_MMIO(0xA180)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8747  #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8748  #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8749  #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8750  #define GEN9_PG_ENABLE				_MMIO(0xA210)
2ea7414159cdbba Mika Kuoppala                 2019-04-10   8751  #define GEN9_RENDER_PG_ENABLE			REG_BIT(0)
2ea7414159cdbba Mika Kuoppala                 2019-04-10   8752  #define GEN9_MEDIA_PG_ENABLE			REG_BIT(1)
2ea7414159cdbba Mika Kuoppala                 2019-04-10   8753  #define GEN11_MEDIA_SAMPLER_PG_ENABLE		REG_BIT(2)
fc6198417264e75 Imre Deak                     2016-06-29   8754  #define GEN8_PUSHBUS_CONTROL			_MMIO(0xA248)
fc6198417264e75 Imre Deak                     2016-06-29   8755  #define GEN8_PUSHBUS_ENABLE			_MMIO(0xA250)
fc6198417264e75 Imre Deak                     2016-06-29   8756  #define GEN8_PUSHBUS_SHIFT			_MMIO(0xA25C)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8757  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8758  #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
a9da9bce88ee842 Gaurav K Singh                2014-12-05   8759  #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
a9da9bce88ee842 Gaurav K Singh                2014-12-05   8760  #define  PIXEL_OVERLAP_CNT_SHIFT		30
a9da9bce88ee842 Gaurav K Singh                2014-12-05   8761  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8762  #define GEN6_PMISR				_MMIO(0x44020)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8763  #define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8764  #define GEN6_PMIIR				_MMIO(0x44028)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8765  #define GEN6_PMIER				_MMIO(0x4402C)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8766  #define  GEN6_PM_MBOX_EVENT			(1 << 25)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8767  #define  GEN6_PM_THERMAL_EVENT			(1 << 24)
917dc6b53c273dd Mika Kuoppala                 2019-04-10   8768  
917dc6b53c273dd Mika Kuoppala                 2019-04-10   8769  /*
917dc6b53c273dd Mika Kuoppala                 2019-04-10   8770   * For Gen11 these are in the upper word of the GPM_WGBOXPERF
917dc6b53c273dd Mika Kuoppala                 2019-04-10   8771   * registers. Shifting is handled on accessing the imr and ier.
917dc6b53c273dd Mika Kuoppala                 2019-04-10   8772   */
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8773  #define  GEN6_PM_RP_DOWN_TIMEOUT		(1 << 6)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8774  #define  GEN6_PM_RP_UP_THRESHOLD		(1 << 5)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8775  #define  GEN6_PM_RP_DOWN_THRESHOLD		(1 << 4)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8776  #define  GEN6_PM_RP_UP_EI_EXPIRED		(1 << 2)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8777  #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1 << 1)
4668f69544328dd Chris Wilson                  2018-08-02   8778  #define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_EI_EXPIRED   | \
4668f69544328dd Chris Wilson                  2018-08-02   8779  						 GEN6_PM_RP_UP_THRESHOLD    | \
4668f69544328dd Chris Wilson                  2018-08-02   8780  						 GEN6_PM_RP_DOWN_EI_EXPIRED | \
4912d04193733a8 Ben Widawsky                  2011-04-25   8781  						 GEN6_PM_RP_DOWN_THRESHOLD  | \
4912d04193733a8 Ben Widawsky                  2011-04-25   8782  						 GEN6_PM_RP_DOWN_TIMEOUT)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8783  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8784  #define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
9e72b46c0d92735 Imre Deak                     2014-05-05   8785  #define GEN7_GT_SCRATCH_REG_NUM			8
9e72b46c0d92735 Imre Deak                     2014-05-05   8786  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8787  #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
76c3552f9f65005 Deepak S                      2014-01-30   8788  #define VLV_GFX_CLK_STATUS_BIT			(1 << 3)
76c3552f9f65005 Deepak S                      2014-01-30   8789  #define VLV_GFX_CLK_FORCE_ON_BIT		(1 << 2)
76c3552f9f65005 Deepak S                      2014-01-30   8790  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8791  #define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8792  #define VLV_COUNTER_CONTROL			_MMIO(0x138104)
49798eb2fe72409 Jesse Barnes                  2013-09-26   8793  #define   VLV_COUNT_RANGE_HIGH			(1 << 15)
31685c258e0b0ad Deepak S                      2014-07-03   8794  #define   VLV_MEDIA_RC0_COUNT_EN		(1 << 5)
31685c258e0b0ad Deepak S                      2014-07-03   8795  #define   VLV_RENDER_RC0_COUNT_EN		(1 << 4)
49798eb2fe72409 Jesse Barnes                  2013-09-26   8796  #define   VLV_MEDIA_RC6_COUNT_EN		(1 << 1)
49798eb2fe72409 Jesse Barnes                  2013-09-26   8797  #define   VLV_RENDER_RC6_COUNT_EN		(1 << 0)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8798  #define GEN6_GT_GFX_RC6				_MMIO(0x138108)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8799  #define VLV_GT_RENDER_RC6			_MMIO(0x138108)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8800  #define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
9cc19be518cb9c6 Imre Deak                     2014-04-14   8801  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8802  #define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8803  #define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8804  #define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8805  #define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
cce66a283e36e74 Ben Widawsky                  2012-03-27   8806  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8807  #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8808  #define   GEN6_PCODE_READY			(1 << 31)
87660502f1a4d51 Lyude                         2016-08-17   8809  #define   GEN6_PCODE_ERROR_MASK			0xFF
87660502f1a4d51 Lyude                         2016-08-17   8810  #define     GEN6_PCODE_SUCCESS			0x0
87660502f1a4d51 Lyude                         2016-08-17   8811  #define     GEN6_PCODE_ILLEGAL_CMD		0x1
87660502f1a4d51 Lyude                         2016-08-17   8812  #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
87660502f1a4d51 Lyude                         2016-08-17   8813  #define     GEN6_PCODE_TIMEOUT			0x3
87660502f1a4d51 Lyude                         2016-08-17   8814  #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
87660502f1a4d51 Lyude                         2016-08-17   8815  #define     GEN7_PCODE_TIMEOUT			0x2
87660502f1a4d51 Lyude                         2016-08-17   8816  #define     GEN7_PCODE_ILLEGAL_DATA		0x3
87660502f1a4d51 Lyude                         2016-08-17   8817  #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
31643d54a739382 Ben Widawsky                  2012-09-26   8818  #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
31643d54a739382 Ben Widawsky                  2012-09-26   8819  #define   GEN6_PCODE_READ_RC6VIDS		0x5
7083e05072b88d5 Ben Widawsky                  2013-02-01   8820  #define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
7083e05072b88d5 Ben Widawsky                  2013-02-01   8821  #define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
b432e5cfd5e9212 Ville Syrjälä                 2015-06-03   8822  #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
57520bc55cf56b7 Damien Lespiau                2015-04-30   8823  #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
57520bc55cf56b7 Damien Lespiau                2015-04-30   8824  #define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
57520bc55cf56b7 Damien Lespiau                2015-04-30   8825  #define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8
57520bc55cf56b7 Damien Lespiau                2015-04-30   8826  #define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16
57520bc55cf56b7 Damien Lespiau                2015-04-30   8827  #define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   8828  #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
5d96d8afcfbb150 Damien Lespiau                2015-05-21   8829  #define   SKL_PCODE_CDCLK_CONTROL		0x7
5d96d8afcfbb150 Damien Lespiau                2015-05-21   8830  #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
5d96d8afcfbb150 Damien Lespiau                2015-05-21   8831  #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
9043ae020506808 Damien Lespiau                2015-04-30   8832  #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
9043ae020506808 Damien Lespiau                2015-04-30   8833  #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
9043ae020506808 Damien Lespiau                2015-04-30   8834  #define   GEN6_READ_OC_PARAMS			0xc
c457d9cf256e942 Ville Syrjälä                 2019-05-24   8835  #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
c457d9cf256e942 Ville Syrjälä                 2019-05-24   8836  #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
c457d9cf256e942 Ville Syrjälä                 2019-05-24   8837  #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
9043ae020506808 Damien Lespiau                2015-04-30   8838  #define   GEN6_PCODE_READ_D_COMP		0x10
9043ae020506808 Damien Lespiau                2015-04-30   8839  #define   GEN6_PCODE_WRITE_D_COMP		0x11
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   8840  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
2a114cc1b964ba0 Ben Widawsky                  2013-11-02   8841  #define   DISPLAY_IPS_CONTROL			0x19
61843f0e6212a85 Ville Syrjälä                 2017-09-12   8842              /* See also IPS_CTL */
61843f0e6212a85 Ville Syrjälä                 2017-09-12   8843  #define     IPS_PCODE_CONTROL			(1 << 30)
93ee29203f50658 Tom O'Rourke                  2014-11-19   8844  #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
656d1b89e5ffb83 Lyude                         2016-08-17   8845  #define   GEN9_PCODE_SAGV_CONTROL		0x21
656d1b89e5ffb83 Lyude                         2016-08-17   8846  #define     GEN9_SAGV_DISABLE			0x0
656d1b89e5ffb83 Lyude                         2016-08-17   8847  #define     GEN9_SAGV_IS_DISABLED		0x1
656d1b89e5ffb83 Lyude                         2016-08-17   8848  #define     GEN9_SAGV_ENABLE			0x3
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8849  #define GEN6_PCODE_DATA				_MMIO(0x138128)
23b2f8bb92feb83 Jesse Barnes                  2011-06-28   8850  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
3ebecd07d382c02 Chris Wilson                  2013-04-12   8851  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8852  #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
8fd2685911cb6c1 Chris Wilson                  2010-12-08   8853  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8854  #define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
4d85529d584856d Ben Widawsky                  2011-12-12   8855  #define   GEN6_CORE_CPD_STATE_MASK	(7 << 4)
4d85529d584856d Ben Widawsky                  2011-12-12   8856  #define   GEN6_RCn_MASK			7
4d85529d584856d Ben Widawsky                  2011-12-12   8857  #define   GEN6_RC0			0
4d85529d584856d Ben Widawsky                  2011-12-12   8858  #define   GEN6_RC3			2
4d85529d584856d Ben Widawsky                  2011-12-12   8859  #define   GEN6_RC6			3
4d85529d584856d Ben Widawsky                  2011-12-12   8860  #define   GEN6_RC7			4
4d85529d584856d Ben Widawsky                  2011-12-12   8861  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8862  #define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   8863  #define   GEN8_LSLICESTAT_MASK		0x7
91bedd34abf0cd3 Łukasz Daniluk                2015-09-25   8864  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8865  #define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8866  #define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
5575f03a603d267 Jeff McGee                    2015-02-27   8867  #define   CHV_SS_PG_ENABLE		(1 << 1)
5575f03a603d267 Jeff McGee                    2015-02-27   8868  #define   CHV_EU08_PG_ENABLE		(1 << 9)
5575f03a603d267 Jeff McGee                    2015-02-27   8869  #define   CHV_EU19_PG_ENABLE		(1 << 17)
5575f03a603d267 Jeff McGee                    2015-02-27   8870  #define   CHV_EU210_PG_ENABLE		(1 << 25)
5575f03a603d267 Jeff McGee                    2015-02-27   8871  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8872  #define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8873  #define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
5575f03a603d267 Jeff McGee                    2015-02-27   8874  #define   CHV_EU311_PG_ENABLE		(1 << 1)
5575f03a603d267 Jeff McGee                    2015-02-27   8875  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8876  #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
f8c3dcf946bfb1e Rodrigo Vivi                  2017-10-25   8877  #define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
f8c3dcf946bfb1e Rodrigo Vivi                  2017-10-25   8878  					      ((slice) % 3) * 0x4)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8879  #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
1c046bc1db49e5a Jeff McGee                    2015-04-03   8880  #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
f8c3dcf946bfb1e Rodrigo Vivi                  2017-10-25   8881  #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8882  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8883  #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
f8c3dcf946bfb1e Rodrigo Vivi                  2017-10-25   8884  #define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
f8c3dcf946bfb1e Rodrigo Vivi                  2017-10-25   8885  					      ((slice) % 3) * 0x8)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8886  #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
f8c3dcf946bfb1e Rodrigo Vivi                  2017-10-25   8887  #define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
f8c3dcf946bfb1e Rodrigo Vivi                  2017-10-25   8888  					      ((slice) % 3) * 0x8)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8889  #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8890  #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8891  #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8892  #define   GEN9_PGCTL_SSA_EU311_ACK	(1 << 6)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8893  #define   GEN9_PGCTL_SSB_EU08_ACK	(1 << 8)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8894  #define   GEN9_PGCTL_SSB_EU19_ACK	(1 << 10)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8895  #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8896  #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
7f992aba1eb5a8b Jeff McGee                    2015-02-13   8897  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8898  #define GEN7_MISCCPCTL				_MMIO(0x9424)
e36891900855b3b Ben Widawsky                  2012-05-25   8899  #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
33a732f407fed46 Alex Dai                      2015-08-12   8900  #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)
33a732f407fed46 Alex Dai                      2015-08-12   8901  #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)
5b88abacd4820c6 Arun Siluvery                 2015-09-08   8902  #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1 << 6)
e36891900855b3b Ben Widawsky                  2012-05-25   8903  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8904  #define GEN8_GARBCNTL				_MMIO(0xB004)
245d96670d2655f Arun Siluvery                 2015-08-03   8905  #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
5bcebe76704f43d Oscar Mateo                   2018-05-08   8906  #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
d41bab687999793 Oscar Mateo                   2018-05-08   8907  #define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
d41bab687999793 Oscar Mateo                   2018-05-08   8908  #define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
d41bab687999793 Oscar Mateo                   2018-05-08   8909  
d41bab687999793 Oscar Mateo                   2018-05-08   8910  #define GEN11_GLBLINVL				_MMIO(0xB404)
d41bab687999793 Oscar Mateo                   2018-05-08   8911  #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
d41bab687999793 Oscar Mateo                   2018-05-08   8912  #define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
245d96670d2655f Arun Siluvery                 2015-08-03   8913  
d65dc3e40b80ab6 Oscar Mateo                   2018-05-08   8914  #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
d65dc3e40b80ab6 Oscar Mateo                   2018-05-08   8915  #define   DFR_DISABLE			(1 << 9)
d65dc3e40b80ab6 Oscar Mateo                   2018-05-08   8916  
f4a357140a5693b Oscar Mateo                   2018-05-08   8917  #define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
f4a357140a5693b Oscar Mateo                   2018-05-08   8918  #define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
f4a357140a5693b Oscar Mateo                   2018-05-08   8919  #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
f4a357140a5693b Oscar Mateo                   2018-05-08   8920  #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
f4a357140a5693b Oscar Mateo                   2018-05-08   8921  
6b967dc39209083 Oscar Mateo                   2018-05-08   8922  #define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
6b967dc39209083 Oscar Mateo                   2018-05-08   8923  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC	(1 << 9)
6b967dc39209083 Oscar Mateo                   2018-05-08   8924  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
6b967dc39209083 Oscar Mateo                   2018-05-08   8925  
f57f9371e285ce5 Oscar Mateo                   2018-10-30   8926  #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
397049a03022702 Dongwon Kim                   2019-04-25   8927  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
f57f9371e285ce5 Oscar Mateo                   2018-10-30   8928  
e36891900855b3b Ben Widawsky                  2012-05-25   8929  /* IVYBRIDGE DPF */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8930  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
e36891900855b3b Ben Widawsky                  2012-05-25   8931  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
e36891900855b3b Ben Widawsky                  2012-05-25   8932  #define   GEN7_PARITY_ERROR_VALID	(1 << 13)
e36891900855b3b Ben Widawsky                  2012-05-25   8933  #define   GEN7_L3CDERRST1_BANK_MASK	(3 << 11)
e36891900855b3b Ben Widawsky                  2012-05-25   8934  #define   GEN7_L3CDERRST1_SUBBANK_MASK	(7 << 8)
e36891900855b3b Ben Widawsky                  2012-05-25   8935  #define GEN7_PARITY_ERROR_ROW(reg) \
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   8936  		(((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
e36891900855b3b Ben Widawsky                  2012-05-25   8937  #define GEN7_PARITY_ERROR_BANK(reg) \
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   8938  		(((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
e36891900855b3b Ben Widawsky                  2012-05-25   8939  #define GEN7_PARITY_ERROR_SUBBANK(reg) \
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   8940  		(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
e36891900855b3b Ben Widawsky                  2012-05-25   8941  #define   GEN7_L3CDERRST1_ENABLE	(1 << 7)
e36891900855b3b Ben Widawsky                  2012-05-25   8942  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8943  #define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
b9524a1e1c48cf4 Ben Widawsky                  2012-05-25   8944  #define GEN7_L3LOG_SIZE			0x80
b9524a1e1c48cf4 Ben Widawsky                  2012-05-25   8945  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8946  #define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8947  #define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
12f3382bc0262e9 Jesse Barnes                  2012-10-25   8948  #define   GEN7_MAX_PS_THREAD_DEP		(8 << 12)
4c2e7a5f6418775 Ben Widawsky                  2013-11-02   8949  #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1 << 10)
983b4b9def91399 Nick Hoath                    2015-04-10   8950  #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1 << 4)
12f3382bc0262e9 Jesse Barnes                  2012-10-25   8951  #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1 << 3)
12f3382bc0262e9 Jesse Barnes                  2012-10-25   8952  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8953  #define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
3ca5da43003a5bd Damien Lespiau                2014-03-26   8954  #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
e2db7071f14b7ac Damien Lespiau                2015-02-09   8955  #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
3ca5da43003a5bd Damien Lespiau                2014-03-26   8956  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8957  #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
950b2aaeea69605 Tim Gore                      2016-03-16   8958  #define   FLOW_CONTROL_ENABLE		(1 << 15)
c8966e1058e1e8a Kenneth Graunke               2014-02-26   8959  #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)
1411e6a57a1836b Kenneth Graunke               2014-02-26   8960  #define   STALL_DOP_GATING_DISABLE		(1 << 5)
aa9f4c4f19131e0 Rodrigo Vivi                  2017-09-06   8961  #define   THROTTLE_12_5				(7 << 2)
a2b16588578f8ed Rafael Antognolli             2017-12-15   8962  #define   DISABLE_EARLY_EOT			(1 << 1)
c8966e1058e1e8a Kenneth Graunke               2014-02-26   8963  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8964  #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8965  #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
8ab4397640de51f Jesse Barnes                  2012-10-25   8966  #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
2cbecff4122cedf Oscar Mateo                   2017-08-23   8967  #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
3c7ab27896804eb Oscar Mateo                   2018-05-25   8968  #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
8ab4397640de51f Jesse Barnes                  2012-10-25   8969  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8970  #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
f3fc4884ebe6ae6 Francisco Jerez               2013-10-02   8971  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
f3fc4884ebe6ae6 Francisco Jerez               2013-10-02   8972  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8973  #define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
6b6d5626750d72a Robert Beckett                2015-09-08   8974  #define   GEN8_ST_PO_DISABLE		(1 << 13)
6b6d5626750d72a Robert Beckett                2015-09-08   8975  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8976  #define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
944115934436b1f Kenneth Graunke               2014-12-31   8977  #define   HSW_SAMPLE_C_PERFORMANCE	(1 << 9)
fd392b6003ae79c Ben Widawsky                  2013-11-04   8978  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1 << 8)
8424171e135ce95 Nick Hoath                    2015-02-05   8979  #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1 << 5)
392572feb01c03c Rodrigo Vivi                  2017-08-29   8980  #define   CNL_FAST_ANISO_L1_BANKING_FIX	(1 << 4)
bf66347cd3a3e94 Ben Widawsky                  2013-11-02   8981  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1 << 1)
fd392b6003ae79c Ben Widawsky                  2013-11-04   8982  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8983  #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
93564044fb2c938 Ville Syrjälä                 2017-08-24   8984  #define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR	(1 << 8)
cac23df48af5311 Nick Hoath                    2015-02-05   8985  #define   GEN9_ENABLE_YV12_BUGFIX	(1 << 4)
bfd8ad4e4a180b9 Tim Gore                      2016-04-19   8986  #define   GEN9_ENABLE_GPGPU_PREEMPTION	(1 << 2)
cac23df48af5311 Nick Hoath                    2015-02-05   8987  
c46f111f5171b63 Jani Nikula                   2014-10-27   8988  /* Audio */
ed5eb1b78a88302 Jani Nikula                   2018-12-31   8989  #define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
e0dac65ed45e72f Wu Fengguang                  2011-09-05   8990  #define   INTEL_AUDIO_DEVCL		0x808629FB
e0dac65ed45e72f Wu Fengguang                  2011-09-05   8991  #define   INTEL_AUDIO_DEVBLC		0x80862801
e0dac65ed45e72f Wu Fengguang                  2011-09-05   8992  #define   INTEL_AUDIO_DEVCTG		0x80862802
e0dac65ed45e72f Wu Fengguang                  2011-09-05   8993  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8994  #define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
e0dac65ed45e72f Wu Fengguang                  2011-09-05   8995  #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
e0dac65ed45e72f Wu Fengguang                  2011-09-05   8996  #define   G4X_ELDV_DEVCTG		(1 << 14)
c46f111f5171b63 Jani Nikula                   2014-10-27   8997  #define   G4X_ELD_ADDR_MASK		(0xf << 5)
e0dac65ed45e72f Wu Fengguang                  2011-09-05   8998  #define   G4X_ELD_ACK			(1 << 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   8999  #define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
e0dac65ed45e72f Wu Fengguang                  2011-09-05   9000  
c46f111f5171b63 Jani Nikula                   2014-10-27   9001  #define _IBX_HDMIW_HDMIEDID_A		0xE2050
c46f111f5171b63 Jani Nikula                   2014-10-27   9002  #define _IBX_HDMIW_HDMIEDID_B		0xE2150
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9003  #define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
c46f111f5171b63 Jani Nikula                   2014-10-27   9004  						  _IBX_HDMIW_HDMIEDID_B)
c46f111f5171b63 Jani Nikula                   2014-10-27   9005  #define _IBX_AUD_CNTL_ST_A		0xE20B4
c46f111f5171b63 Jani Nikula                   2014-10-27   9006  #define _IBX_AUD_CNTL_ST_B		0xE21B4
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9007  #define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
c46f111f5171b63 Jani Nikula                   2014-10-27   9008  						  _IBX_AUD_CNTL_ST_B)
c46f111f5171b63 Jani Nikula                   2014-10-27   9009  #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
c46f111f5171b63 Jani Nikula                   2014-10-27   9010  #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
1202b4c6782e57a Wu Fengguang                  2011-12-09   9011  #define   IBX_ELD_ACK			(1 << 4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9012  #define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
82910ac6d575d4c Jani Nikula                   2014-10-27   9013  #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
82910ac6d575d4c Jani Nikula                   2014-10-27   9014  #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
1202b4c6782e57a Wu Fengguang                  2011-12-09   9015  
c46f111f5171b63 Jani Nikula                   2014-10-27   9016  #define _CPT_HDMIW_HDMIEDID_A		0xE5050
c46f111f5171b63 Jani Nikula                   2014-10-27   9017  #define _CPT_HDMIW_HDMIEDID_B		0xE5150
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9018  #define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
c46f111f5171b63 Jani Nikula                   2014-10-27   9019  #define _CPT_AUD_CNTL_ST_A		0xE50B4
c46f111f5171b63 Jani Nikula                   2014-10-27   9020  #define _CPT_AUD_CNTL_ST_B		0xE51B4
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9021  #define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9022  #define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
e0dac65ed45e72f Wu Fengguang                  2011-09-05   9023  
c46f111f5171b63 Jani Nikula                   2014-10-27   9024  #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
c46f111f5171b63 Jani Nikula                   2014-10-27   9025  #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9026  #define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
c46f111f5171b63 Jani Nikula                   2014-10-27   9027  #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
c46f111f5171b63 Jani Nikula                   2014-10-27   9028  #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9029  #define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9030  #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
9ca2fe731b3f12a Mengdong Lin                  2013-11-01   9031  
ae662d31264979e Eric Anholt                   2012-01-03   9032  /* These are the 4 32-bit write offset registers for each stream
ae662d31264979e Eric Anholt                   2012-01-03   9033   * output buffer.  It determines the offset from the
ae662d31264979e Eric Anholt                   2012-01-03   9034   * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
ae662d31264979e Eric Anholt                   2012-01-03   9035   */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9036  #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
ae662d31264979e Eric Anholt                   2012-01-03   9037  
c46f111f5171b63 Jani Nikula                   2014-10-27   9038  #define _IBX_AUD_CONFIG_A		0xe2000
c46f111f5171b63 Jani Nikula                   2014-10-27   9039  #define _IBX_AUD_CONFIG_B		0xe2100
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9040  #define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
c46f111f5171b63 Jani Nikula                   2014-10-27   9041  #define _CPT_AUD_CONFIG_A		0xe5000
c46f111f5171b63 Jani Nikula                   2014-10-27   9042  #define _CPT_AUD_CONFIG_B		0xe5100
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9043  #define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
c46f111f5171b63 Jani Nikula                   2014-10-27   9044  #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
c46f111f5171b63 Jani Nikula                   2014-10-27   9045  #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9046  #define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9ca2fe731b3f12a Mengdong Lin                  2013-11-01   9047  
b6daa025b1e1aeb Wu Fengguang                  2012-01-06   9048  #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
b6daa025b1e1aeb Wu Fengguang                  2012-01-06   9049  #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
b6daa025b1e1aeb Wu Fengguang                  2012-01-06   9050  #define   AUD_CONFIG_UPPER_N_SHIFT		20
c46f111f5171b63 Jani Nikula                   2014-10-27   9051  #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
b6daa025b1e1aeb Wu Fengguang                  2012-01-06   9052  #define   AUD_CONFIG_LOWER_N_SHIFT		4
c46f111f5171b63 Jani Nikula                   2014-10-27   9053  #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
2561389a128cd15 Jani Nikula                   2016-10-10   9054  #define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
2561389a128cd15 Jani Nikula                   2016-10-10   9055  #define   AUD_CONFIG_N(n) \
2561389a128cd15 Jani Nikula                   2016-10-10   9056  	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
2561389a128cd15 Jani Nikula                   2016-10-10   9057  	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
b6daa025b1e1aeb Wu Fengguang                  2012-01-06   9058  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
1a91510dc3b8098 Jani Nikula                   2013-10-16   9059  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9060  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9061  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9062  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9063  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9064  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9065  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9066  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9067  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9068  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
1a91510dc3b8098 Jani Nikula                   2013-10-16   9069  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
b6daa025b1e1aeb Wu Fengguang                  2012-01-06   9070  #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
b6daa025b1e1aeb Wu Fengguang                  2012-01-06   9071  
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9072  /* HSW Audio */
c46f111f5171b63 Jani Nikula                   2014-10-27   9073  #define _HSW_AUD_CONFIG_A		0x65000
c46f111f5171b63 Jani Nikula                   2014-10-27   9074  #define _HSW_AUD_CONFIG_B		0x65100
3904fb78a80da64 Ville Syrjälä                 2019-04-30   9075  #define HSW_AUD_CFG(trans)		_MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9076  
c46f111f5171b63 Jani Nikula                   2014-10-27   9077  #define _HSW_AUD_MISC_CTRL_A		0x65010
c46f111f5171b63 Jani Nikula                   2014-10-27   9078  #define _HSW_AUD_MISC_CTRL_B		0x65110
3904fb78a80da64 Ville Syrjälä                 2019-04-30   9079  #define HSW_AUD_MISC_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9080  
6014ac122ed081f Libin Yang                    2016-10-25   9081  #define _HSW_AUD_M_CTS_ENABLE_A		0x65028
6014ac122ed081f Libin Yang                    2016-10-25   9082  #define _HSW_AUD_M_CTS_ENABLE_B		0x65128
3904fb78a80da64 Ville Syrjälä                 2019-04-30   9083  #define HSW_AUD_M_CTS_ENABLE(trans)	_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
6014ac122ed081f Libin Yang                    2016-10-25   9084  #define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)
6014ac122ed081f Libin Yang                    2016-10-25   9085  #define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)
6014ac122ed081f Libin Yang                    2016-10-25   9086  #define   AUD_CONFIG_M_MASK		0xfffff
6014ac122ed081f Libin Yang                    2016-10-25   9087  
c46f111f5171b63 Jani Nikula                   2014-10-27   9088  #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
c46f111f5171b63 Jani Nikula                   2014-10-27   9089  #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
3904fb78a80da64 Ville Syrjälä                 2019-04-30   9090  #define HSW_AUD_DIP_ELD_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9091  
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9092  /* Audio Digital Converter */
c46f111f5171b63 Jani Nikula                   2014-10-27   9093  #define _HSW_AUD_DIG_CNVT_1		0x65080
c46f111f5171b63 Jani Nikula                   2014-10-27   9094  #define _HSW_AUD_DIG_CNVT_2		0x65180
3904fb78a80da64 Ville Syrjälä                 2019-04-30   9095  #define AUD_DIG_CNVT(trans)		_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9b138a836753643 Wang Xingchao                 2012-08-09   9096  #define DIP_PORT_SEL_MASK		0x3
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9097  
c46f111f5171b63 Jani Nikula                   2014-10-27   9098  #define _HSW_AUD_EDID_DATA_A		0x65050
c46f111f5171b63 Jani Nikula                   2014-10-27   9099  #define _HSW_AUD_EDID_DATA_B		0x65150
3904fb78a80da64 Ville Syrjälä                 2019-04-30   9100  #define HSW_AUD_EDID_DATA(trans)	_MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9101  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9102  #define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9103  #define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
82910ac6d575d4c Jani Nikula                   2014-10-27   9104  #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
82910ac6d575d4c Jani Nikula                   2014-10-27   9105  #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
82910ac6d575d4c Jani Nikula                   2014-10-27   9106  #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
82910ac6d575d4c Jani Nikula                   2014-10-27   9107  #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
9a78b6cce5ebb04 Wang Xingchao                 2012-08-09   9108  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9109  #define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
632f3ab95fe2ffe Lu, Han                       2015-05-05   9110  #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
632f3ab95fe2ffe Lu, Han                       2015-05-05   9111  
9c3a16c887f0f8f Imre Deak                     2017-08-14   9112  /*
75e39688f350f63 Imre Deak                     2018-08-06   9113   * HSW - ICL power wells
75e39688f350f63 Imre Deak                     2018-08-06   9114   *
75e39688f350f63 Imre Deak                     2018-08-06   9115   * Platforms have up to 3 power well control register sets, each set
75e39688f350f63 Imre Deak                     2018-08-06   9116   * controlling up to 16 power wells via a request/status HW flag tuple:
75e39688f350f63 Imre Deak                     2018-08-06   9117   * - main (HSW_PWR_WELL_CTL[1-4])
75e39688f350f63 Imre Deak                     2018-08-06   9118   * - AUX  (ICL_PWR_WELL_CTL_AUX[1-4])
75e39688f350f63 Imre Deak                     2018-08-06   9119   * - DDI  (ICL_PWR_WELL_CTL_DDI[1-4])
75e39688f350f63 Imre Deak                     2018-08-06   9120   * Each control register set consists of up to 4 registers used by different
75e39688f350f63 Imre Deak                     2018-08-06   9121   * sources that can request a power well to be enabled:
75e39688f350f63 Imre Deak                     2018-08-06   9122   * - BIOS   (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
75e39688f350f63 Imre Deak                     2018-08-06   9123   * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
75e39688f350f63 Imre Deak                     2018-08-06   9124   * - KVMR   (HSW_PWR_WELL_CTL3)   (only in the main register set)
75e39688f350f63 Imre Deak                     2018-08-06   9125   * - DEBUG  (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9c3a16c887f0f8f Imre Deak                     2017-08-14   9126   */
75e39688f350f63 Imre Deak                     2018-08-06   9127  #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
75e39688f350f63 Imre Deak                     2018-08-06   9128  #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
75e39688f350f63 Imre Deak                     2018-08-06   9129  #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
75e39688f350f63 Imre Deak                     2018-08-06   9130  #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
75e39688f350f63 Imre Deak                     2018-08-06   9131  #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
75e39688f350f63 Imre Deak                     2018-08-06   9132  #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
75e39688f350f63 Imre Deak                     2018-08-06   9133  
75e39688f350f63 Imre Deak                     2018-08-06   9134  /* HSW/BDW power well */
75e39688f350f63 Imre Deak                     2018-08-06   9135  #define   HSW_PW_CTL_IDX_GLOBAL			15
75e39688f350f63 Imre Deak                     2018-08-06   9136  
75e39688f350f63 Imre Deak                     2018-08-06   9137  /* SKL/BXT/GLK/CNL power wells */
75e39688f350f63 Imre Deak                     2018-08-06   9138  #define   SKL_PW_CTL_IDX_PW_2			15
75e39688f350f63 Imre Deak                     2018-08-06   9139  #define   SKL_PW_CTL_IDX_PW_1			14
75e39688f350f63 Imre Deak                     2018-08-06   9140  #define   CNL_PW_CTL_IDX_AUX_F			12
75e39688f350f63 Imre Deak                     2018-08-06   9141  #define   CNL_PW_CTL_IDX_AUX_D			11
75e39688f350f63 Imre Deak                     2018-08-06   9142  #define   GLK_PW_CTL_IDX_AUX_C			10
75e39688f350f63 Imre Deak                     2018-08-06   9143  #define   GLK_PW_CTL_IDX_AUX_B			9
75e39688f350f63 Imre Deak                     2018-08-06   9144  #define   GLK_PW_CTL_IDX_AUX_A			8
75e39688f350f63 Imre Deak                     2018-08-06   9145  #define   CNL_PW_CTL_IDX_DDI_F			6
75e39688f350f63 Imre Deak                     2018-08-06   9146  #define   SKL_PW_CTL_IDX_DDI_D			4
75e39688f350f63 Imre Deak                     2018-08-06   9147  #define   SKL_PW_CTL_IDX_DDI_C			3
75e39688f350f63 Imre Deak                     2018-08-06   9148  #define   SKL_PW_CTL_IDX_DDI_B			2
75e39688f350f63 Imre Deak                     2018-08-06   9149  #define   SKL_PW_CTL_IDX_DDI_A_E		1
75e39688f350f63 Imre Deak                     2018-08-06   9150  #define   GLK_PW_CTL_IDX_DDI_A			1
75e39688f350f63 Imre Deak                     2018-08-06   9151  #define   SKL_PW_CTL_IDX_MISC_IO		0
75e39688f350f63 Imre Deak                     2018-08-06   9152  
656409bbaf8792c Imre Deak                     2019-07-11   9153  /* ICL/TGL - power wells */
1db27a729119505 Mika Kahola                   2019-07-11   9154  #define   TGL_PW_CTL_IDX_PW_5			4
75e39688f350f63 Imre Deak                     2018-08-06   9155  #define   ICL_PW_CTL_IDX_PW_4			3
75e39688f350f63 Imre Deak                     2018-08-06   9156  #define   ICL_PW_CTL_IDX_PW_3			2
75e39688f350f63 Imre Deak                     2018-08-06   9157  #define   ICL_PW_CTL_IDX_PW_2			1
75e39688f350f63 Imre Deak                     2018-08-06   9158  #define   ICL_PW_CTL_IDX_PW_1			0
75e39688f350f63 Imre Deak                     2018-08-06   9159  
75e39688f350f63 Imre Deak                     2018-08-06   9160  #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
75e39688f350f63 Imre Deak                     2018-08-06   9161  #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
75e39688f350f63 Imre Deak                     2018-08-06   9162  #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
656409bbaf8792c Imre Deak                     2019-07-11   9163  #define   TGL_PW_CTL_IDX_AUX_TBT6		14
656409bbaf8792c Imre Deak                     2019-07-11   9164  #define   TGL_PW_CTL_IDX_AUX_TBT5		13
656409bbaf8792c Imre Deak                     2019-07-11   9165  #define   TGL_PW_CTL_IDX_AUX_TBT4		12
75e39688f350f63 Imre Deak                     2018-08-06   9166  #define   ICL_PW_CTL_IDX_AUX_TBT4		11
656409bbaf8792c Imre Deak                     2019-07-11   9167  #define   TGL_PW_CTL_IDX_AUX_TBT3		11
75e39688f350f63 Imre Deak                     2018-08-06   9168  #define   ICL_PW_CTL_IDX_AUX_TBT3		10
656409bbaf8792c Imre Deak                     2019-07-11   9169  #define   TGL_PW_CTL_IDX_AUX_TBT2		10
75e39688f350f63 Imre Deak                     2018-08-06   9170  #define   ICL_PW_CTL_IDX_AUX_TBT2		9
656409bbaf8792c Imre Deak                     2019-07-11   9171  #define   TGL_PW_CTL_IDX_AUX_TBT1		9
75e39688f350f63 Imre Deak                     2018-08-06   9172  #define   ICL_PW_CTL_IDX_AUX_TBT1		8
656409bbaf8792c Imre Deak                     2019-07-11   9173  #define   TGL_PW_CTL_IDX_AUX_TC6		8
656409bbaf8792c Imre Deak                     2019-07-11   9174  #define   TGL_PW_CTL_IDX_AUX_TC5		7
656409bbaf8792c Imre Deak                     2019-07-11   9175  #define   TGL_PW_CTL_IDX_AUX_TC4		6
75e39688f350f63 Imre Deak                     2018-08-06   9176  #define   ICL_PW_CTL_IDX_AUX_F			5
656409bbaf8792c Imre Deak                     2019-07-11   9177  #define   TGL_PW_CTL_IDX_AUX_TC3		5
75e39688f350f63 Imre Deak                     2018-08-06   9178  #define   ICL_PW_CTL_IDX_AUX_E			4
656409bbaf8792c Imre Deak                     2019-07-11   9179  #define   TGL_PW_CTL_IDX_AUX_TC2		4
75e39688f350f63 Imre Deak                     2018-08-06   9180  #define   ICL_PW_CTL_IDX_AUX_D			3
656409bbaf8792c Imre Deak                     2019-07-11   9181  #define   TGL_PW_CTL_IDX_AUX_TC1		3
75e39688f350f63 Imre Deak                     2018-08-06   9182  #define   ICL_PW_CTL_IDX_AUX_C			2
75e39688f350f63 Imre Deak                     2018-08-06   9183  #define   ICL_PW_CTL_IDX_AUX_B			1
75e39688f350f63 Imre Deak                     2018-08-06   9184  #define   ICL_PW_CTL_IDX_AUX_A			0
75e39688f350f63 Imre Deak                     2018-08-06   9185  
75e39688f350f63 Imre Deak                     2018-08-06   9186  #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
75e39688f350f63 Imre Deak                     2018-08-06   9187  #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
75e39688f350f63 Imre Deak                     2018-08-06   9188  #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
656409bbaf8792c Imre Deak                     2019-07-11   9189  #define   TGL_PW_CTL_IDX_DDI_TC6		8
656409bbaf8792c Imre Deak                     2019-07-11   9190  #define   TGL_PW_CTL_IDX_DDI_TC5		7
656409bbaf8792c Imre Deak                     2019-07-11   9191  #define   TGL_PW_CTL_IDX_DDI_TC4		6
75e39688f350f63 Imre Deak                     2018-08-06   9192  #define   ICL_PW_CTL_IDX_DDI_F			5
656409bbaf8792c Imre Deak                     2019-07-11   9193  #define   TGL_PW_CTL_IDX_DDI_TC3		5
75e39688f350f63 Imre Deak                     2018-08-06   9194  #define   ICL_PW_CTL_IDX_DDI_E			4
656409bbaf8792c Imre Deak                     2019-07-11   9195  #define   TGL_PW_CTL_IDX_DDI_TC2		4
75e39688f350f63 Imre Deak                     2018-08-06   9196  #define   ICL_PW_CTL_IDX_DDI_D			3
656409bbaf8792c Imre Deak                     2019-07-11   9197  #define   TGL_PW_CTL_IDX_DDI_TC1		3
75e39688f350f63 Imre Deak                     2018-08-06   9198  #define   ICL_PW_CTL_IDX_DDI_C			2
75e39688f350f63 Imre Deak                     2018-08-06   9199  #define   ICL_PW_CTL_IDX_DDI_B			1
75e39688f350f63 Imre Deak                     2018-08-06   9200  #define   ICL_PW_CTL_IDX_DDI_A			0
75e39688f350f63 Imre Deak                     2018-08-06   9201  
75e39688f350f63 Imre Deak                     2018-08-06   9202  /* HSW - power well misc debug registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9203  #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
9eb3a75276892b0 Eugeni Dodonov                2012-03-29   9204  #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1 << 31)
9eb3a75276892b0 Eugeni Dodonov                2012-03-29   9205  #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1 << 20)
9eb3a75276892b0 Eugeni Dodonov                2012-03-29   9206  #define   HSW_PWR_WELL_FORCE_ON			(1 << 19)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9207  #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
9eb3a75276892b0 Eugeni Dodonov                2012-03-29   9208  
94dd5138c5ed02d Satheeshakrishna M            2015-02-04   9209  /* SKL Fuse Status */
b2891eb2531e5e0 Imre Deak                     2017-07-11   9210  enum skl_power_gate {
b2891eb2531e5e0 Imre Deak                     2017-07-11   9211  	SKL_PG0,
b2891eb2531e5e0 Imre Deak                     2017-07-11   9212  	SKL_PG1,
b2891eb2531e5e0 Imre Deak                     2017-07-11   9213  	SKL_PG2,
1a260e1117a4ba5 Imre Deak                     2018-08-06   9214  	ICL_PG3,
1a260e1117a4ba5 Imre Deak                     2018-08-06   9215  	ICL_PG4,
b2891eb2531e5e0 Imre Deak                     2017-07-11   9216  };
b2891eb2531e5e0 Imre Deak                     2017-07-11   9217  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9218  #define SKL_FUSE_STATUS				_MMIO(0x42000)
94dd5138c5ed02d Satheeshakrishna M            2015-02-04   9219  #define  SKL_FUSE_DOWNLOAD_STATUS		(1 << 31)
75e39688f350f63 Imre Deak                     2018-08-06   9220  /*
75e39688f350f63 Imre Deak                     2018-08-06   9221   * PG0 is HW controlled, so doesn't have a corresponding power well control knob
75e39688f350f63 Imre Deak                     2018-08-06   9222   * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
75e39688f350f63 Imre Deak                     2018-08-06   9223   */
75e39688f350f63 Imre Deak                     2018-08-06   9224  #define  SKL_PW_CTL_IDX_TO_PG(pw_idx)		\
75e39688f350f63 Imre Deak                     2018-08-06   9225  	((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
75e39688f350f63 Imre Deak                     2018-08-06   9226  /*
75e39688f350f63 Imre Deak                     2018-08-06   9227   * PG0 is HW controlled, so doesn't have a corresponding power well control knob
75e39688f350f63 Imre Deak                     2018-08-06   9228   * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
75e39688f350f63 Imre Deak                     2018-08-06   9229   */
75e39688f350f63 Imre Deak                     2018-08-06   9230  #define  ICL_PW_CTL_IDX_TO_PG(pw_idx)		\
75e39688f350f63 Imre Deak                     2018-08-06   9231  	((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
b2891eb2531e5e0 Imre Deak                     2017-07-11   9232  #define  SKL_FUSE_PG_DIST_STATUS(pg)		(1 << (27 - (pg)))
94dd5138c5ed02d Satheeshakrishna M            2015-02-04   9233  
75e39688f350f63 Imre Deak                     2018-08-06   9234  #define _CNL_AUX_REG_IDX(pw_idx)	((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9235  #define _CNL_AUX_ANAOVRD1_B		0x162250
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9236  #define _CNL_AUX_ANAOVRD1_C		0x162210
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9237  #define _CNL_AUX_ANAOVRD1_D		0x1622D0
b1ae6a8b7a85e83 Rodrigo Vivi                  2018-01-29   9238  #define _CNL_AUX_ANAOVRD1_F		0x162A90
75e39688f350f63 Imre Deak                     2018-08-06   9239  #define CNL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9240  						    _CNL_AUX_ANAOVRD1_B, \
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9241  						    _CNL_AUX_ANAOVRD1_C, \
b1ae6a8b7a85e83 Rodrigo Vivi                  2018-01-29   9242  						    _CNL_AUX_ANAOVRD1_D, \
b1ae6a8b7a85e83 Rodrigo Vivi                  2018-01-29   9243  						    _CNL_AUX_ANAOVRD1_F))
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9244  #define   CNL_AUX_ANAOVRD1_ENABLE	(1 << 16)
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9245  #define   CNL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 23)
ddd39e4b3f8fb9b Lucas De Marchi               2017-11-28   9246  
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9247  #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9248  #define _ICL_AUX_ANAOVRD1_A		0x162398
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9249  #define _ICL_AUX_ANAOVRD1_B		0x6C398
deea06b47574de8 Lucas De Marchi               2019-07-11   9250  #define _TGL_AUX_ANAOVRD1_C		0x160398
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9251  #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9252  						    _ICL_AUX_ANAOVRD1_A, \
deea06b47574de8 Lucas De Marchi               2019-07-11   9253  						    _ICL_AUX_ANAOVRD1_B, \
deea06b47574de8 Lucas De Marchi               2019-07-11   9254  						    _TGL_AUX_ANAOVRD1_C))
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9255  #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9256  #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
ffd7e32d95db99f Lucas De Marchi               2018-10-12   9257  
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9258  /* HDCP Key Registers */
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9259  #define HDCP_KEY_CONF			_MMIO(0x66c00)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9260  #define  HDCP_AKSV_SEND_TRIGGER		BIT(31)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9261  #define  HDCP_CLEAR_KEYS_TRIGGER	BIT(30)
fdddd08c4875db0 Ramalingam C                  2018-01-18   9262  #define  HDCP_KEY_LOAD_TRIGGER		BIT(8)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9263  #define HDCP_KEY_STATUS			_MMIO(0x66c04)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9264  #define  HDCP_FUSE_IN_PROGRESS		BIT(7)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9265  #define  HDCP_FUSE_ERROR		BIT(6)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9266  #define  HDCP_FUSE_DONE			BIT(5)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9267  #define  HDCP_KEY_LOAD_STATUS		BIT(1)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9268  #define  HDCP_KEY_LOAD_DONE		BIT(0)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9269  #define HDCP_AKSV_LO			_MMIO(0x66c10)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9270  #define HDCP_AKSV_HI			_MMIO(0x66c14)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9271  
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9272  /* HDCP Repeater Registers */
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9273  #define HDCP_REP_CTL			_MMIO(0x66d00)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9274  #define  HDCP_DDIB_REP_PRESENT		BIT(30)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9275  #define  HDCP_DDIA_REP_PRESENT		BIT(29)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9276  #define  HDCP_DDIC_REP_PRESENT		BIT(28)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9277  #define  HDCP_DDID_REP_PRESENT		BIT(27)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9278  #define  HDCP_DDIF_REP_PRESENT		BIT(26)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9279  #define  HDCP_DDIE_REP_PRESENT		BIT(25)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9280  #define  HDCP_DDIB_SHA1_M0		(1 << 20)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9281  #define  HDCP_DDIA_SHA1_M0		(2 << 20)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9282  #define  HDCP_DDIC_SHA1_M0		(3 << 20)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9283  #define  HDCP_DDID_SHA1_M0		(4 << 20)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9284  #define  HDCP_DDIF_SHA1_M0		(5 << 20)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9285  #define  HDCP_DDIE_SHA1_M0		(6 << 20) /* Bspec says 5? */
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9286  #define  HDCP_SHA1_BUSY			BIT(16)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9287  #define  HDCP_SHA1_READY		BIT(17)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9288  #define  HDCP_SHA1_COMPLETE		BIT(18)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9289  #define  HDCP_SHA1_V_MATCH		BIT(19)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9290  #define  HDCP_SHA1_TEXT_32		(1 << 1)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9291  #define  HDCP_SHA1_COMPLETE_HASH	(2 << 1)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9292  #define  HDCP_SHA1_TEXT_24		(4 << 1)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9293  #define  HDCP_SHA1_TEXT_16		(5 << 1)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9294  #define  HDCP_SHA1_TEXT_8		(6 << 1)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9295  #define  HDCP_SHA1_TEXT_0		(7 << 1)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9296  #define HDCP_SHA_V_PRIME_H0		_MMIO(0x66d04)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9297  #define HDCP_SHA_V_PRIME_H1		_MMIO(0x66d08)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9298  #define HDCP_SHA_V_PRIME_H2		_MMIO(0x66d0C)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9299  #define HDCP_SHA_V_PRIME_H3		_MMIO(0x66d10)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9300  #define HDCP_SHA_V_PRIME_H4		_MMIO(0x66d14)
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   9301  #define HDCP_SHA_V_PRIME(h)		_MMIO((0x66d04 + (h) * 4))
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9302  #define HDCP_SHA_TEXT			_MMIO(0x66d18)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9303  
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9304  /* HDCP Auth Registers */
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9305  #define _PORTA_HDCP_AUTHENC		0x66800
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9306  #define _PORTB_HDCP_AUTHENC		0x66500
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9307  #define _PORTC_HDCP_AUTHENC		0x66600
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9308  #define _PORTD_HDCP_AUTHENC		0x66700
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9309  #define _PORTE_HDCP_AUTHENC		0x66A00
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9310  #define _PORTF_HDCP_AUTHENC		0x66900
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9311  #define _PORT_HDCP_AUTHENC(port, x)	_MMIO(_PICK(port, \
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9312  					  _PORTA_HDCP_AUTHENC, \
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9313  					  _PORTB_HDCP_AUTHENC, \
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9314  					  _PORTC_HDCP_AUTHENC, \
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9315  					  _PORTD_HDCP_AUTHENC, \
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9316  					  _PORTE_HDCP_AUTHENC, \
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   9317  					  _PORTF_HDCP_AUTHENC) + (x))
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9318  #define PORT_HDCP_CONF(port)		_PORT_HDCP_AUTHENC(port, 0x0)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9319  #define  HDCP_CONF_CAPTURE_AN		BIT(0)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9320  #define  HDCP_CONF_AUTH_AND_ENC		(BIT(1) | BIT(0))
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9321  #define PORT_HDCP_ANINIT(port)		_PORT_HDCP_AUTHENC(port, 0x4)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9322  #define PORT_HDCP_ANLO(port)		_PORT_HDCP_AUTHENC(port, 0x8)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9323  #define PORT_HDCP_ANHI(port)		_PORT_HDCP_AUTHENC(port, 0xC)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9324  #define PORT_HDCP_BKSVLO(port)		_PORT_HDCP_AUTHENC(port, 0x10)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9325  #define PORT_HDCP_BKSVHI(port)		_PORT_HDCP_AUTHENC(port, 0x14)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9326  #define PORT_HDCP_RPRIME(port)		_PORT_HDCP_AUTHENC(port, 0x18)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9327  #define PORT_HDCP_STATUS(port)		_PORT_HDCP_AUTHENC(port, 0x1C)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9328  #define  HDCP_STATUS_STREAM_A_ENC	BIT(31)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9329  #define  HDCP_STATUS_STREAM_B_ENC	BIT(30)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9330  #define  HDCP_STATUS_STREAM_C_ENC	BIT(29)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9331  #define  HDCP_STATUS_STREAM_D_ENC	BIT(28)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9332  #define  HDCP_STATUS_AUTH		BIT(21)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9333  #define  HDCP_STATUS_ENC		BIT(20)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9334  #define  HDCP_STATUS_RI_MATCH		BIT(19)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9335  #define  HDCP_STATUS_R0_READY		BIT(18)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9336  #define  HDCP_STATUS_AN_READY		BIT(17)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9337  #define  HDCP_STATUS_CIPHER		BIT(16)
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12   9338  #define  HDCP_STATUS_FRAME_CNT(x)	(((x) >> 8) & 0xff)
ee5e5e7a5e0fdec Sean Paul                     2018-01-08   9339  
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9340  /* HDCP2.2 Registers */
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9341  #define _PORTA_HDCP2_BASE		0x66800
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9342  #define _PORTB_HDCP2_BASE		0x66500
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9343  #define _PORTC_HDCP2_BASE		0x66600
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9344  #define _PORTD_HDCP2_BASE		0x66700
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9345  #define _PORTE_HDCP2_BASE		0x66A00
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9346  #define _PORTF_HDCP2_BASE		0x66900
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9347  #define _PORT_HDCP2_BASE(port, x)	_MMIO(_PICK((port), \
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9348  					  _PORTA_HDCP2_BASE, \
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9349  					  _PORTB_HDCP2_BASE, \
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9350  					  _PORTC_HDCP2_BASE, \
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9351  					  _PORTD_HDCP2_BASE, \
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9352  					  _PORTE_HDCP2_BASE, \
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9353  					  _PORTF_HDCP2_BASE) + (x))
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9354  
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9355  #define HDCP2_AUTH_DDI(port)		_PORT_HDCP2_BASE(port, 0x98)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9356  #define   AUTH_LINK_AUTHENTICATED	BIT(31)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9357  #define   AUTH_LINK_TYPE		BIT(30)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9358  #define   AUTH_FORCE_CLR_INPUTCTR	BIT(19)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9359  #define   AUTH_CLR_KEYS			BIT(18)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9360  
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9361  #define HDCP2_CTL_DDI(port)		_PORT_HDCP2_BASE(port, 0xB0)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9362  #define   CTL_LINK_ENCRYPTION_REQ	BIT(31)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9363  
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9364  #define HDCP2_STATUS_DDI(port)		_PORT_HDCP2_BASE(port, 0xB4)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9365  #define   STREAM_ENCRYPTION_STATUS_A	BIT(31)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9366  #define   STREAM_ENCRYPTION_STATUS_B	BIT(30)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9367  #define   STREAM_ENCRYPTION_STATUS_C	BIT(29)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9368  #define   LINK_TYPE_STATUS		BIT(22)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9369  #define   LINK_AUTH_STATUS		BIT(21)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9370  #define   LINK_ENCRYPTION_STATUS	BIT(20)
3ab0a6ed4ce5b60 Ramalingam C                  2018-10-29   9371  
e7e104c3785a5a8 Eugeni Dodonov                2012-03-29   9372  /* Per-pipe DDI Function Control */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9373  #define _TRANS_DDI_FUNC_CTL_A		0x60400
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9374  #define _TRANS_DDI_FUNC_CTL_B		0x61400
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9375  #define _TRANS_DDI_FUNC_CTL_C		0x62400
f1f1d4fa5869c8b Lucas De Marchi               2019-07-11   9376  #define _TRANS_DDI_FUNC_CTL_D		0x63400
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9377  #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
49edbd49786ee32 Madhav Chauhan                2018-10-15   9378  #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
49edbd49786ee32 Madhav Chauhan                2018-10-15   9379  #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9380  #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
a57c774ab2b849b Antti Koskipaa                2014-02-04   9381  
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9382  #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
e7e104c3785a5a8 Eugeni Dodonov                2012-03-29   9383  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9384  #define  TRANS_DDI_PORT_MASK		(7 << 28)
26804afd4b3c7a1 Daniel Vetter                 2014-06-25   9385  #define  TRANS_DDI_PORT_SHIFT		28
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9386  #define  TRANS_DDI_SELECT_PORT(x)	((x) << 28)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9387  #define  TRANS_DDI_PORT_NONE		(0 << 28)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9388  #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9389  #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9390  #define  TRANS_DDI_MODE_SELECT_DVI	(1 << 24)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9391  #define  TRANS_DDI_MODE_SELECT_DP_SST	(2 << 24)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9392  #define  TRANS_DDI_MODE_SELECT_DP_MST	(3 << 24)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9393  #define  TRANS_DDI_MODE_SELECT_FDI	(4 << 24)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9394  #define  TRANS_DDI_BPC_MASK		(7 << 20)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9395  #define  TRANS_DDI_BPC_8		(0 << 20)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9396  #define  TRANS_DDI_BPC_10		(1 << 20)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9397  #define  TRANS_DDI_BPC_6		(2 << 20)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9398  #define  TRANS_DDI_BPC_12		(3 << 20)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9399  #define  TRANS_DDI_PVSYNC		(1 << 17)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9400  #define  TRANS_DDI_PHSYNC		(1 << 16)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9401  #define  TRANS_DDI_EDP_INPUT_MASK	(7 << 12)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9402  #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9403  #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9404  #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9405  #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
2320175feb74a11 Sean Paul                     2018-01-08   9406  #define  TRANS_DDI_HDCP_SIGNALLING	(1 << 9)
01b887c36e12845 Dave Airlie                   2014-05-02   9407  #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1 << 8)
15953637886d88d Shashank Sharma               2017-03-13   9408  #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
15953637886d88d Shashank Sharma               2017-03-13   9409  #define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
ad80a810ec3ffa9 Paulo Zanoni                  2012-10-24   9410  #define  TRANS_DDI_BFI_ENABLE		(1 << 4)
15953637886d88d Shashank Sharma               2017-03-13   9411  #define  TRANS_DDI_HIGH_TMDS_CHAR_RATE	(1 << 4)
15953637886d88d Shashank Sharma               2017-03-13   9412  #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
15953637886d88d Shashank Sharma               2017-03-13   9413  #define  TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
15953637886d88d Shashank Sharma               2017-03-13   9414  					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
15953637886d88d Shashank Sharma               2017-03-13   9415  					| TRANS_DDI_HDMI_SCRAMBLING)
e7e104c3785a5a8 Eugeni Dodonov                2012-03-29   9416  
49edbd49786ee32 Madhav Chauhan                2018-10-15   9417  #define _TRANS_DDI_FUNC_CTL2_A		0x60404
49edbd49786ee32 Madhav Chauhan                2018-10-15   9418  #define _TRANS_DDI_FUNC_CTL2_B		0x61404
49edbd49786ee32 Madhav Chauhan                2018-10-15   9419  #define _TRANS_DDI_FUNC_CTL2_C		0x62404
49edbd49786ee32 Madhav Chauhan                2018-10-15   9420  #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
49edbd49786ee32 Madhav Chauhan                2018-10-15   9421  #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
49edbd49786ee32 Madhav Chauhan                2018-10-15   9422  #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
49edbd49786ee32 Madhav Chauhan                2018-10-15   9423  #define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
49edbd49786ee32 Madhav Chauhan                2018-10-15   9424  						     _TRANS_DDI_FUNC_CTL2_A)
49edbd49786ee32 Madhav Chauhan                2018-10-15   9425  #define  PORT_SYNC_MODE_ENABLE			(1 << 4)
7264aebb81d15aa Manasi Navare                 2019-03-19   9426  #define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) << 0)
49edbd49786ee32 Madhav Chauhan                2018-10-15   9427  #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)
49edbd49786ee32 Madhav Chauhan                2018-10-15   9428  #define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0
49edbd49786ee32 Madhav Chauhan                2018-10-15   9429  
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9430  /* DisplayPort Transport Control */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9431  #define _DP_TP_CTL_A			0x64040
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9432  #define _DP_TP_CTL_B			0x64140
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9433  #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9434  #define  DP_TP_CTL_ENABLE			(1 << 31)
5c44b938629a816 Anusha Srivatsa               2018-11-28   9435  #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9436  #define  DP_TP_CTL_MODE_SST			(0 << 27)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9437  #define  DP_TP_CTL_MODE_MST			(1 << 27)
01b887c36e12845 Dave Airlie                   2014-05-02   9438  #define  DP_TP_CTL_FORCE_ACT			(1 << 25)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9439  #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1 << 18)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9440  #define  DP_TP_CTL_FDI_AUTOTRAIN		(1 << 15)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9441  #define  DP_TP_CTL_LINK_TRAIN_MASK		(7 << 8)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9442  #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9443  #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1 << 8)
d6c0d722aea21d4 Paulo Zanoni                  2012-10-15   9444  #define  DP_TP_CTL_LINK_TRAIN_PAT3		(4 << 8)
2edd53272120ea3 Manasi Navare                 2018-06-11   9445  #define  DP_TP_CTL_LINK_TRAIN_PAT4		(5 << 8)
d6c0d722aea21d4 Paulo Zanoni                  2012-10-15   9446  #define  DP_TP_CTL_LINK_TRAIN_IDLE		(2 << 8)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9447  #define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3 << 8)
d6c0d722aea21d4 Paulo Zanoni                  2012-10-15   9448  #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1 << 7)
0e87f6679807a60 Eugeni Dodonov                2012-03-29   9449  
e411b2c116626e6 Eugeni Dodonov                2012-03-29   9450  /* DisplayPort Transport Status */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9451  #define _DP_TP_STATUS_A			0x64044
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9452  #define _DP_TP_STATUS_B			0x64144
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9453  #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
5c44b938629a816 Anusha Srivatsa               2018-11-28   9454  #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
d6c0d722aea21d4 Paulo Zanoni                  2012-10-15   9455  #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
01b887c36e12845 Dave Airlie                   2014-05-02   9456  #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
01b887c36e12845 Dave Airlie                   2014-05-02   9457  #define  DP_TP_STATUS_MODE_STATUS_MST		(1 << 23)
e411b2c116626e6 Eugeni Dodonov                2012-03-29   9458  #define  DP_TP_STATUS_AUTOTRAIN_DONE		(1 << 12)
01b887c36e12845 Dave Airlie                   2014-05-02   9459  #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2	(3 << 8)
01b887c36e12845 Dave Airlie                   2014-05-02   9460  #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1	(3 << 4)
01b887c36e12845 Dave Airlie                   2014-05-02   9461  #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
e411b2c116626e6 Eugeni Dodonov                2012-03-29   9462  
03f896a1aeff5bd Eugeni Dodonov                2012-03-29   9463  /* DDI Buffer Control */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9464  #define _DDI_BUF_CTL_A				0x64000
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9465  #define _DDI_BUF_CTL_B				0x64100
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9466  #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
03f896a1aeff5bd Eugeni Dodonov                2012-03-29   9467  #define  DDI_BUF_CTL_ENABLE			(1 << 31)
c5fe6a0637e8a9f Sonika Jindal                 2014-08-11   9468  #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
03f896a1aeff5bd Eugeni Dodonov                2012-03-29   9469  #define  DDI_BUF_EMP_MASK			(0xf << 24)
876a8cdf92b23d2 Damien Lespiau                2012-12-11   9470  #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
03f896a1aeff5bd Eugeni Dodonov                2012-03-29   9471  #define  DDI_BUF_IS_IDLE			(1 << 7)
79935fca3f1259e Paulo Zanoni                  2012-11-20   9472  #define  DDI_A_4_LANES				(1 << 4)
17aa6be9579eb20 Daniel Vetter                 2013-04-30   9473  #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
90a6b7b052b1aa1 Ville Syrjälä                 2015-07-06   9474  #define  DDI_PORT_WIDTH_MASK			(7 << 1)
90a6b7b052b1aa1 Ville Syrjälä                 2015-07-06   9475  #define  DDI_PORT_WIDTH_SHIFT			1
03f896a1aeff5bd Eugeni Dodonov                2012-03-29   9476  #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
03f896a1aeff5bd Eugeni Dodonov                2012-03-29   9477  
bb879a44ffd5f70 Eugeni Dodonov                2012-03-29   9478  /* DDI Buffer Translations */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9479  #define _DDI_BUF_TRANS_A		0x64E00
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9480  #define _DDI_BUF_TRANS_B		0x64E60
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9481  #define DDI_BUF_TRANS_LO(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
c110ae6cffddb81 Ville Syrjälä                 2016-07-12   9482  #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9483  #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
bb879a44ffd5f70 Eugeni Dodonov                2012-03-29   9484  
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9485  /* Sideband Interface (SBI) is programmed indirectly, via
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9486   * SBI_ADDR, which contains the register offset; and SBI_DATA,
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9487   * which contains the payload */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9488  #define SBI_ADDR			_MMIO(0xC6000)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9489  #define SBI_DATA			_MMIO(0xC6004)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9490  #define SBI_CTL_STAT			_MMIO(0xC6008)
988d6ee8b2e8694 Paulo Zanoni                  2012-12-01   9491  #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
988d6ee8b2e8694 Paulo Zanoni                  2012-12-01   9492  #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
988d6ee8b2e8694 Paulo Zanoni                  2012-12-01   9493  #define  SBI_CTL_OP_IORD		(0x2 << 8)
988d6ee8b2e8694 Paulo Zanoni                  2012-12-01   9494  #define  SBI_CTL_OP_IOWR		(0x3 << 8)
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9495  #define  SBI_CTL_OP_CRRD		(0x6 << 8)
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9496  #define  SBI_CTL_OP_CRWR		(0x7 << 8)
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9497  #define  SBI_RESPONSE_FAIL		(0x1 << 1)
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9498  #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9499  #define  SBI_BUSY			(0x1 << 0)
7501a4d846c9ca3 Eugeni Dodonov                2012-03-29   9500  #define  SBI_READY			(0x0 << 0)
52f025efa989318 Eugeni Dodonov                2012-03-29   9501  
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9502  /* SBI offsets */
f7be2c2150b0457 Ville Syrjälä                 2015-12-04   9503  #define  SBI_SSCDIVINTPHASE			0x0200
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9504  #define  SBI_SSCDIVINTPHASE6			0x0600
8802e5b6de51ebb Ville Syrjälä                 2016-02-17   9505  #define   SBI_SSCDIVINTPHASE_DIVSEL_SHIFT	1
8802e5b6de51ebb Ville Syrjälä                 2016-02-17   9506  #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9507  #define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x) << 1)
8802e5b6de51ebb Ville Syrjälä                 2016-02-17   9508  #define   SBI_SSCDIVINTPHASE_INCVAL_SHIFT	8
8802e5b6de51ebb Ville Syrjälä                 2016-02-17   9509  #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9510  #define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x) << 8)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9511  #define   SBI_SSCDIVINTPHASE_DIR(x)		((x) << 15)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9512  #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
f7be2c2150b0457 Ville Syrjälä                 2015-12-04   9513  #define  SBI_SSCDITHPHASE			0x0204
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9514  #define  SBI_SSCCTL				0x020c
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9515  #define  SBI_SSCCTL6				0x060C
dde86e2db54545e Paulo Zanoni                  2012-12-01   9516  #define   SBI_SSCCTL_PATHALT			(1 << 3)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9517  #define   SBI_SSCCTL_DISABLE			(1 << 0)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9518  #define  SBI_SSCAUXDIV6				0x0610
8802e5b6de51ebb Ville Syrjälä                 2016-02-17   9519  #define   SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT	4
8802e5b6de51ebb Ville Syrjälä                 2016-02-17   9520  #define   SBI_SSCAUXDIV_FINALDIV2SEL_MASK	(1 << 4)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9521  #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x) << 4)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9522  #define  SBI_DBUFF0				0x2a00
2fa86a1fea14c30 Paulo Zanoni                  2013-07-23   9523  #define  SBI_GEN0				0x1f00
2fa86a1fea14c30 Paulo Zanoni                  2013-07-23   9524  #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
ccf1c867ce049bf Eugeni Dodonov                2012-03-29   9525  
52f025efa989318 Eugeni Dodonov                2012-03-29   9526  /* LPT PIXCLK_GATE */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9527  #define PIXCLK_GATE			_MMIO(0xC6020)
745ca3be810b37f Paulo Zanoni                  2012-08-08   9528  #define  PIXCLK_GATE_UNGATE		(1 << 0)
745ca3be810b37f Paulo Zanoni                  2012-08-08   9529  #define  PIXCLK_GATE_GATE		(0 << 0)
52f025efa989318 Eugeni Dodonov                2012-03-29   9530  
e93ea06aa0436f6 Eugeni Dodonov                2012-03-29   9531  /* SPLL */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9532  #define SPLL_CTL			_MMIO(0x46020)
e93ea06aa0436f6 Eugeni Dodonov                2012-03-29   9533  #define  SPLL_PLL_ENABLE		(1 << 31)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9534  #define  SPLL_REF_BCLK			(0 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9535  #define  SPLL_REF_MUXED_SSC		(1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9536  #define  SPLL_REF_NON_SSC_HSW		(2 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9537  #define  SPLL_REF_PCH_SSC_BDW		(2 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9538  #define  SPLL_REF_LCPLL			(3 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9539  #define  SPLL_REF_MASK			(3 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9540  #define  SPLL_FREQ_810MHz		(0 << 26)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9541  #define  SPLL_FREQ_1350MHz		(1 << 26)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9542  #define  SPLL_FREQ_2700MHz		(2 << 26)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9543  #define  SPLL_FREQ_MASK			(3 << 26)
e93ea06aa0436f6 Eugeni Dodonov                2012-03-29   9544  
4dffc4043a392b4 Eugeni Dodonov                2012-03-29   9545  /* WRPLL */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9546  #define _WRPLL_CTL1			0x46040
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9547  #define _WRPLL_CTL2			0x46060
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9548  #define WRPLL_CTL(pll)			_MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
4dffc4043a392b4 Eugeni Dodonov                2012-03-29   9549  #define  WRPLL_PLL_ENABLE		(1 << 31)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9550  #define  WRPLL_REF_BCLK			(0 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9551  #define  WRPLL_REF_PCH_SSC		(1 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9552  #define  WRPLL_REF_MUXED_SSC_BDW	(2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9553  #define  WRPLL_REF_SPECIAL_HSW		(2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9554  #define  WRPLL_REF_LCPLL		(3 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9555  #define  WRPLL_REF_MASK			(3 << 28)
ef4d084fae9d471 Eugeni Dodonov                2012-04-13   9556  /* WRPLL divider programming */
ef4d084fae9d471 Eugeni Dodonov                2012-04-13   9557  #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
11578553d354f34 Jesse Barnes                  2014-01-21   9558  #define  WRPLL_DIVIDER_REF_MASK		(0xff)
ef4d084fae9d471 Eugeni Dodonov                2012-04-13   9559  #define  WRPLL_DIVIDER_POST(x)		((x) << 8)
11578553d354f34 Jesse Barnes                  2014-01-21   9560  #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
11578553d354f34 Jesse Barnes                  2014-01-21   9561  #define  WRPLL_DIVIDER_POST_SHIFT	8
ef4d084fae9d471 Eugeni Dodonov                2012-04-13   9562  #define  WRPLL_DIVIDER_FEEDBACK(x)	((x) << 16)
11578553d354f34 Jesse Barnes                  2014-01-21   9563  #define  WRPLL_DIVIDER_FB_SHIFT		16
11578553d354f34 Jesse Barnes                  2014-01-21   9564  #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
4dffc4043a392b4 Eugeni Dodonov                2012-03-29   9565  
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9566  /* Port clock selection */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9567  #define _PORT_CLK_SEL_A			0x46100
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9568  #define _PORT_CLK_SEL_B			0x46104
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9569  #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9570  #define  PORT_CLK_SEL_LCPLL_2700	(0 << 29)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9571  #define  PORT_CLK_SEL_LCPLL_1350	(1 << 29)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9572  #define  PORT_CLK_SEL_LCPLL_810		(2 << 29)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9573  #define  PORT_CLK_SEL_SPLL		(3 << 29)
716c2e55100ff55 Daniel Vetter                 2014-06-25   9574  #define  PORT_CLK_SEL_WRPLL(pll)	(((pll) + 4) << 29)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9575  #define  PORT_CLK_SEL_WRPLL1		(4 << 29)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9576  #define  PORT_CLK_SEL_WRPLL2		(5 << 29)
6441ab5f8ffdf7e Paulo Zanoni                  2012-10-05   9577  #define  PORT_CLK_SEL_NONE		(7 << 29)
11578553d354f34 Jesse Barnes                  2014-01-21   9578  #define  PORT_CLK_SEL_MASK		(7 << 29)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9579  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9580  /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9581  #define DDI_CLK_SEL(port)		PORT_CLK_SEL(port)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9582  #define  DDI_CLK_SEL_NONE		(0x0 << 28)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9583  #define  DDI_CLK_SEL_MG			(0x8 << 28)
1fa11ee2d9d0ccd Paulo Zanoni                  2018-05-21   9584  #define  DDI_CLK_SEL_TBT_162		(0xC << 28)
1fa11ee2d9d0ccd Paulo Zanoni                  2018-05-21   9585  #define  DDI_CLK_SEL_TBT_270		(0xD << 28)
1fa11ee2d9d0ccd Paulo Zanoni                  2018-05-21   9586  #define  DDI_CLK_SEL_TBT_540		(0xE << 28)
1fa11ee2d9d0ccd Paulo Zanoni                  2018-05-21   9587  #define  DDI_CLK_SEL_TBT_810		(0xF << 28)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9588  #define  DDI_CLK_SEL_MASK		(0xF << 28)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9589  
bb523fc08d4a4a7 Paulo Zanoni                  2012-10-23   9590  /* Transcoder clock selection */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9591  #define _TRANS_CLK_SEL_A		0x46140
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9592  #define _TRANS_CLK_SEL_B		0x46144
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9593  #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
bb523fc08d4a4a7 Paulo Zanoni                  2012-10-23   9594  /* For each transcoder, we need to select the corresponding port clock */
bb523fc08d4a4a7 Paulo Zanoni                  2012-10-23   9595  #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9596  #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
fec9181ca4bd700 Eugeni Dodonov                2012-03-29   9597  
7f1052a8fa38df6 Ville Syrjälä                 2016-04-26   9598  #define CDCLK_FREQ			_MMIO(0x46200)
7f1052a8fa38df6 Ville Syrjälä                 2016-04-26   9599  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9600  #define _TRANSA_MSA_MISC		0x60410
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9601  #define _TRANSB_MSA_MISC		0x61410
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9602  #define _TRANSC_MSA_MISC		0x62410
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9603  #define _TRANS_EDP_MSA_MISC		0x6f410
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9604  #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
a57c774ab2b849b Antti Koskipaa                2014-02-04   9605  
c9809791ae0ae3e Paulo Zanoni                  2012-10-23   9606  #define  TRANS_MSA_SYNC_CLK		(1 << 0)
668b6c176c33f44 Shashank Sharma               2018-10-12   9607  #define  TRANS_MSA_SAMPLING_444		(2 << 1)
668b6c176c33f44 Shashank Sharma               2018-10-12   9608  #define  TRANS_MSA_CLRSP_YCBCR		(2 << 3)
c9809791ae0ae3e Paulo Zanoni                  2012-10-23   9609  #define  TRANS_MSA_6_BPC		(0 << 5)
c9809791ae0ae3e Paulo Zanoni                  2012-10-23   9610  #define  TRANS_MSA_8_BPC		(1 << 5)
c9809791ae0ae3e Paulo Zanoni                  2012-10-23   9611  #define  TRANS_MSA_10_BPC		(2 << 5)
c9809791ae0ae3e Paulo Zanoni                  2012-10-23   9612  #define  TRANS_MSA_12_BPC		(3 << 5)
c9809791ae0ae3e Paulo Zanoni                  2012-10-23   9613  #define  TRANS_MSA_16_BPC		(4 << 5)
dc5977da99ea280 Jani Nikula                   2018-08-14   9614  #define  TRANS_MSA_CEA_RANGE		(1 << 3)
ec4401d3893c99b Gwan-gyeong Mun               2019-05-21   9615  #define  TRANS_MSA_USE_VSC_SDP		(1 << 14)
dae847991a4327b Paulo Zanoni                  2012-10-15   9616  
90e8d31c5389006 Eugeni Dodonov                2012-03-29   9617  /* LCPLL Control */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9618  #define LCPLL_CTL			_MMIO(0x130040)
90e8d31c5389006 Eugeni Dodonov                2012-03-29   9619  #define  LCPLL_PLL_DISABLE		(1 << 31)
90e8d31c5389006 Eugeni Dodonov                2012-03-29   9620  #define  LCPLL_PLL_LOCK			(1 << 30)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9621  #define  LCPLL_REF_NON_SSC		(0 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9622  #define  LCPLL_REF_BCLK			(2 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9623  #define  LCPLL_REF_PCH_SSC		(3 << 28)
4a95e36f0357ab4 Ville Syrjälä                 2019-06-10   9624  #define  LCPLL_REF_MASK			(3 << 28)
79f689aa6b14e05 Paulo Zanoni                  2012-10-05   9625  #define  LCPLL_CLK_FREQ_MASK		(3 << 26)
79f689aa6b14e05 Paulo Zanoni                  2012-10-05   9626  #define  LCPLL_CLK_FREQ_450		(0 << 26)
e39bf98a91abd5c Paulo Zanoni                  2013-11-02   9627  #define  LCPLL_CLK_FREQ_54O_BDW		(1 << 26)
e39bf98a91abd5c Paulo Zanoni                  2013-11-02   9628  #define  LCPLL_CLK_FREQ_337_5_BDW	(2 << 26)
e39bf98a91abd5c Paulo Zanoni                  2013-11-02   9629  #define  LCPLL_CLK_FREQ_675_BDW		(3 << 26)
90e8d31c5389006 Eugeni Dodonov                2012-03-29   9630  #define  LCPLL_CD_CLOCK_DISABLE		(1 << 25)
b432e5cfd5e9212 Ville Syrjälä                 2015-06-03   9631  #define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1 << 24)
90e8d31c5389006 Eugeni Dodonov                2012-03-29   9632  #define  LCPLL_CD2X_CLOCK_DISABLE	(1 << 23)
be256dc70284c02 Paulo Zanoni                  2013-07-23   9633  #define  LCPLL_POWER_DOWN_ALLOW		(1 << 22)
79f689aa6b14e05 Paulo Zanoni                  2012-10-05   9634  #define  LCPLL_CD_SOURCE_FCLK		(1 << 21)
be256dc70284c02 Paulo Zanoni                  2013-07-23   9635  #define  LCPLL_CD_SOURCE_FCLK_DONE	(1 << 19)
be256dc70284c02 Paulo Zanoni                  2013-07-23   9636  
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9637  /*
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9638   * SKL Clocks
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9639   */
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9640  
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9641  /* CDCLK_CTL */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9642  #define CDCLK_CTL			_MMIO(0x46000)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9643  #define  CDCLK_FREQ_SEL_MASK		(3 << 26)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9644  #define  CDCLK_FREQ_450_432		(0 << 26)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9645  #define  CDCLK_FREQ_540			(1 << 26)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9646  #define  CDCLK_FREQ_337_308		(2 << 26)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9647  #define  CDCLK_FREQ_675_617		(3 << 26)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9648  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9649  #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9650  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9651  #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9652  #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
7fe6275721c26ba Ville Syrjälä                 2016-05-11   9653  #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
53421c2fe99ce16 Lucas De Marchi               2017-12-04   9654  #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
7fe6275721c26ba Ville Syrjälä                 2016-05-11   9655  #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
186a277e317a14d Paulo Zanoni                  2018-02-06   9656  #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9657  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
7fe6275721c26ba Ville Syrjälä                 2016-05-11   9658  #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9659  
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9660  /* LCPLL_CTL */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9661  #define LCPLL1_CTL		_MMIO(0x46010)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9662  #define LCPLL2_CTL		_MMIO(0x46014)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9663  #define  LCPLL_PLL_ENABLE	(1 << 31)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9664  
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9665  /* DPLL control1 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9666  #define DPLL_CTRL1		_MMIO(0x6C058)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9667  #define  DPLL_CTRL1_HDMI_MODE(id)		(1 << ((id) * 6 + 5))
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9668  #define  DPLL_CTRL1_SSC(id)			(1 << ((id) * 6 + 4))
71cd8423cd874d1 Damien Lespiau                2015-04-30   9669  #define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7 << ((id) * 6 + 1))
71cd8423cd874d1 Damien Lespiau                2015-04-30   9670  #define  DPLL_CTRL1_LINK_RATE_SHIFT(id)		((id) * 6 + 1)
71cd8423cd874d1 Damien Lespiau                2015-04-30   9671  #define  DPLL_CTRL1_LINK_RATE(linkrate, id)	((linkrate) << ((id) * 6 + 1))
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9672  #define  DPLL_CTRL1_OVERRIDE(id)		(1 << ((id) * 6))
71cd8423cd874d1 Damien Lespiau                2015-04-30   9673  #define  DPLL_CTRL1_LINK_RATE_2700		0
71cd8423cd874d1 Damien Lespiau                2015-04-30   9674  #define  DPLL_CTRL1_LINK_RATE_1350		1
71cd8423cd874d1 Damien Lespiau                2015-04-30   9675  #define  DPLL_CTRL1_LINK_RATE_810		2
71cd8423cd874d1 Damien Lespiau                2015-04-30   9676  #define  DPLL_CTRL1_LINK_RATE_1620		3
71cd8423cd874d1 Damien Lespiau                2015-04-30   9677  #define  DPLL_CTRL1_LINK_RATE_1080		4
71cd8423cd874d1 Damien Lespiau                2015-04-30   9678  #define  DPLL_CTRL1_LINK_RATE_2160		5
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9679  
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9680  /* DPLL control2 */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9681  #define DPLL_CTRL2				_MMIO(0x6C05C)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9682  #define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1 << ((port) + 15))
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9683  #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3 << ((port) * 3 + 1))
540e732c8e2d90a Satheeshakrishna M            2014-11-13   9684  #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port) * 3 + 1)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9685  #define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk) << ((port) * 3 + 1))
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9686  #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1 << ((port) * 3))
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9687  
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9688  /* DPLL Status */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9689  #define DPLL_STATUS	_MMIO(0x6C060)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9690  #define  DPLL_LOCK(id) (1 << ((id) * 8))
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9691  
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9692  /* DPLL cfg */
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9693  #define _DPLL1_CFGCR1	0x6C040
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9694  #define _DPLL2_CFGCR1	0x6C048
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9695  #define _DPLL3_CFGCR1	0x6C050
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9696  #define  DPLL_CFGCR1_FREQ_ENABLE	(1 << 31)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9697  #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9698  #define  DPLL_CFGCR1_DCO_FRACTION(x)	((x) << 9)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9699  #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9700  
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9701  #define _DPLL1_CFGCR2	0x6C044
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9702  #define _DPLL2_CFGCR2	0x6C04C
086f8e84a085a43 Ville Syrjälä                 2015-11-04   9703  #define _DPLL3_CFGCR2	0x6C054
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9704  #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9705  #define  DPLL_CFGCR2_QDIV_RATIO(x)	((x) << 8)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9706  #define  DPLL_CFGCR2_QDIV_MODE(x)	((x) << 7)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9707  #define  DPLL_CFGCR2_KDIV_MASK		(3 << 5)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9708  #define  DPLL_CFGCR2_KDIV(x)		((x) << 5)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9709  #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9710  #define  DPLL_CFGCR2_KDIV_2 (1 << 5)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9711  #define  DPLL_CFGCR2_KDIV_3 (2 << 5)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9712  #define  DPLL_CFGCR2_KDIV_1 (3 << 5)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9713  #define  DPLL_CFGCR2_PDIV_MASK		(7 << 2)
68d9753837db0e4 Ville Syrjälä                 2015-09-18   9714  #define  DPLL_CFGCR2_PDIV(x)		((x) << 2)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9715  #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9716  #define  DPLL_CFGCR2_PDIV_2 (1 << 2)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9717  #define  DPLL_CFGCR2_PDIV_3 (2 << 2)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9718  #define  DPLL_CFGCR2_PDIV_7 (4 << 2)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9719  #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
326ac39b68e6aeb Satheeshakrishna M            2014-11-13   9720  
da3b891b0fb8860 Lyude                         2016-02-04   9721  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9722  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
540e732c8e2d90a Satheeshakrishna M            2014-11-13   9723  
555e38d2731720a Rodrigo Vivi                  2017-06-09   9724  /*
555e38d2731720a Rodrigo Vivi                  2017-06-09   9725   * CNL Clocks
555e38d2731720a Rodrigo Vivi                  2017-06-09   9726   */
555e38d2731720a Rodrigo Vivi                  2017-06-09   9727  #define DPCLKA_CFGCR0				_MMIO(0x6C200)
376faf8a3b2ff49 Rodrigo Vivi                  2018-01-29   9728  #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
376faf8a3b2ff49 Rodrigo Vivi                  2018-01-29   9729  						      (port) + 10))
376faf8a3b2ff49 Rodrigo Vivi                  2018-01-29   9730  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
376faf8a3b2ff49 Rodrigo Vivi                  2018-01-29   9731  						(port) * 2)
376faf8a3b2ff49 Rodrigo Vivi                  2018-01-29   9732  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
376faf8a3b2ff49 Rodrigo Vivi                  2018-01-29   9733  #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
555e38d2731720a Rodrigo Vivi                  2017-06-09   9734  
befa372b990a3c0 Matt Roper                    2019-07-09   9735  #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
befa372b990a3c0 Matt Roper                    2019-07-09   9736  #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
befa372b990a3c0 Matt Roper                    2019-07-09   9737  #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
befa372b990a3c0 Matt Roper                    2019-07-09   9738  						      21 : (tc_port) + 12))
befa372b990a3c0 Matt Roper                    2019-07-09   9739  #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
befa372b990a3c0 Matt Roper                    2019-07-09   9740  #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
befa372b990a3c0 Matt Roper                    2019-07-09   9741  #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
befa372b990a3c0 Matt Roper                    2019-07-09   9742  
a927c927de34652 Rodrigo Vivi                  2017-06-09   9743  /* CNL PLL */
a927c927de34652 Rodrigo Vivi                  2017-06-09   9744  #define DPLL0_ENABLE		0x46010
a927c927de34652 Rodrigo Vivi                  2017-06-09   9745  #define DPLL1_ENABLE		0x46014
a927c927de34652 Rodrigo Vivi                  2017-06-09   9746  #define  PLL_ENABLE		(1 << 31)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9747  #define  PLL_LOCK		(1 << 30)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9748  #define  PLL_POWER_ENABLE	(1 << 27)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9749  #define  PLL_POWER_STATE	(1 << 26)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9750  #define CNL_DPLL_ENABLE(pll)	_MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9751  
1fa11ee2d9d0ccd Paulo Zanoni                  2018-05-21   9752  #define TBT_PLL_ENABLE		_MMIO(0x46020)
1fa11ee2d9d0ccd Paulo Zanoni                  2018-05-21   9753  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9754  #define _MG_PLL1_ENABLE		0x46030
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9755  #define _MG_PLL2_ENABLE		0x46034
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9756  #define _MG_PLL3_ENABLE		0x46038
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9757  #define _MG_PLL4_ENABLE		0x4603C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9758  /* Bits are the same as DPLL0_ENABLE */
584fca111d0cf32 Lucas De Marchi               2019-01-25   9759  #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9760  					   _MG_PLL2_ENABLE)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9761  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9762  #define _MG_REFCLKIN_CTL_PORT1				0x16892C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9763  #define _MG_REFCLKIN_CTL_PORT2				0x16992C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9764  #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9765  #define _MG_REFCLKIN_CTL_PORT4				0x16B92C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9766  #define   MG_REFCLKIN_CTL_OD_2_MUX(x)			((x) << 8)
bd99ce085f165a0 Imre Deak                     2018-06-19   9767  #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9768  #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9769  					    _MG_REFCLKIN_CTL_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9770  					    _MG_REFCLKIN_CTL_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9771  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9772  #define _MG_CLKTOP2_CORECLKCTL1_PORT1			0x1688D8
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9773  #define _MG_CLKTOP2_CORECLKCTL1_PORT2			0x1698D8
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9774  #define _MG_CLKTOP2_CORECLKCTL1_PORT3			0x16A8D8
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9775  #define _MG_CLKTOP2_CORECLKCTL1_PORT4			0x16B8D8
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9776  #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)		((x) << 16)
bd99ce085f165a0 Imre Deak                     2018-06-19   9777  #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9778  #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)		((x) << 8)
bd99ce085f165a0 Imre Deak                     2018-06-19   9779  #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9780  #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9781  						   _MG_CLKTOP2_CORECLKCTL1_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9782  						   _MG_CLKTOP2_CORECLKCTL1_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9783  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9784  #define _MG_CLKTOP2_HSCLKCTL_PORT1			0x1688D4
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9785  #define _MG_CLKTOP2_HSCLKCTL_PORT2			0x1698D4
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9786  #define _MG_CLKTOP2_HSCLKCTL_PORT3			0x16A8D4
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9787  #define _MG_CLKTOP2_HSCLKCTL_PORT4			0x16B8D4
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9788  #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)		((x) << 16)
bd99ce085f165a0 Imre Deak                     2018-06-19   9789  #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9790  #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)	((x) << 14)
bd99ce085f165a0 Imre Deak                     2018-06-19   9791  #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
bd99ce085f165a0 Imre Deak                     2018-06-19   9792  #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
bcaad532974eb47 Manasi Navare                 2018-08-17   9793  #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
bcaad532974eb47 Manasi Navare                 2018-08-17   9794  #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3		(1 << 12)
bcaad532974eb47 Manasi Navare                 2018-08-17   9795  #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5		(2 << 12)
bcaad532974eb47 Manasi Navare                 2018-08-17   9796  #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7		(3 << 12)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9797  #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)
7b19f544ed90b7c Manasi Navare                 2018-08-17   9798  #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT		8
bd99ce085f165a0 Imre Deak                     2018-06-19   9799  #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9800  #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9801  						_MG_CLKTOP2_HSCLKCTL_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9802  						_MG_CLKTOP2_HSCLKCTL_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9803  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9804  #define _MG_PLL_DIV0_PORT1				0x168A00
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9805  #define _MG_PLL_DIV0_PORT2				0x169A00
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9806  #define _MG_PLL_DIV0_PORT3				0x16AA00
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9807  #define _MG_PLL_DIV0_PORT4				0x16BA00
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9808  #define   MG_PLL_DIV0_FRACNEN_H				(1 << 30)
7b19f544ed90b7c Manasi Navare                 2018-08-17   9809  #define   MG_PLL_DIV0_FBDIV_FRAC_MASK			(0x3fffff << 8)
7b19f544ed90b7c Manasi Navare                 2018-08-17   9810  #define   MG_PLL_DIV0_FBDIV_FRAC_SHIFT			8
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9811  #define   MG_PLL_DIV0_FBDIV_FRAC(x)			((x) << 8)
7b19f544ed90b7c Manasi Navare                 2018-08-17   9812  #define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9813  #define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9814  #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9815  					_MG_PLL_DIV0_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9816  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9817  #define _MG_PLL_DIV1_PORT1				0x168A04
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9818  #define _MG_PLL_DIV1_PORT2				0x169A04
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9819  #define _MG_PLL_DIV1_PORT3				0x16AA04
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9820  #define _MG_PLL_DIV1_PORT4				0x16BA04
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9821  #define   MG_PLL_DIV1_IREF_NDIVRATIO(x)			((x) << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9822  #define   MG_PLL_DIV1_DITHER_DIV_1			(0 << 12)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9823  #define   MG_PLL_DIV1_DITHER_DIV_2			(1 << 12)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9824  #define   MG_PLL_DIV1_DITHER_DIV_4			(2 << 12)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9825  #define   MG_PLL_DIV1_DITHER_DIV_8			(3 << 12)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9826  #define   MG_PLL_DIV1_NDIVRATIO(x)			((x) << 4)
7b19f544ed90b7c Manasi Navare                 2018-08-17   9827  #define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9828  #define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9829  #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9830  					_MG_PLL_DIV1_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9831  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9832  #define _MG_PLL_LF_PORT1				0x168A08
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9833  #define _MG_PLL_LF_PORT2				0x169A08
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9834  #define _MG_PLL_LF_PORT3				0x16AA08
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9835  #define _MG_PLL_LF_PORT4				0x16BA08
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9836  #define   MG_PLL_LF_TDCTARGETCNT(x)			((x) << 24)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9837  #define   MG_PLL_LF_AFCCNTSEL_256			(0 << 20)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9838  #define   MG_PLL_LF_AFCCNTSEL_512			(1 << 20)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9839  #define   MG_PLL_LF_GAINCTRL(x)				((x) << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9840  #define   MG_PLL_LF_INT_COEFF(x)			((x) << 8)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9841  #define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9842  #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9843  				      _MG_PLL_LF_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9844  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9845  #define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9846  #define _MG_PLL_FRAC_LOCK_PORT2				0x169A0C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9847  #define _MG_PLL_FRAC_LOCK_PORT3				0x16AA0C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9848  #define _MG_PLL_FRAC_LOCK_PORT4				0x16BA0C
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9849  #define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32		(1 << 18)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9850  #define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32		(1 << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9851  #define   MG_PLL_FRAC_LOCK_LOCKTHRESH(x)		((x) << 11)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9852  #define   MG_PLL_FRAC_LOCK_DCODITHEREN			(1 << 10)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9853  #define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN		(1 << 8)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9854  #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9855  #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9856  					     _MG_PLL_FRAC_LOCK_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9857  					     _MG_PLL_FRAC_LOCK_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9858  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9859  #define _MG_PLL_SSC_PORT1				0x168A10
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9860  #define _MG_PLL_SSC_PORT2				0x169A10
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9861  #define _MG_PLL_SSC_PORT3				0x16AA10
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9862  #define _MG_PLL_SSC_PORT4				0x16BA10
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9863  #define   MG_PLL_SSC_EN					(1 << 28)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9864  #define   MG_PLL_SSC_TYPE(x)				((x) << 26)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9865  #define   MG_PLL_SSC_STEPLENGTH(x)			((x) << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9866  #define   MG_PLL_SSC_STEPNUM(x)				((x) << 10)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9867  #define   MG_PLL_SSC_FLLEN				(1 << 9)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9868  #define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9869  #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9870  				       _MG_PLL_SSC_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9871  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9872  #define _MG_PLL_BIAS_PORT1				0x168A14
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9873  #define _MG_PLL_BIAS_PORT2				0x169A14
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9874  #define _MG_PLL_BIAS_PORT3				0x16AA14
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9875  #define _MG_PLL_BIAS_PORT4				0x16BA14
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9876  #define   MG_PLL_BIAS_BIAS_GB_SEL(x)			((x) << 30)
bd99ce085f165a0 Imre Deak                     2018-06-19   9877  #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK			(0x3 << 30)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9878  #define   MG_PLL_BIAS_INIT_DCOAMP(x)			((x) << 24)
bd99ce085f165a0 Imre Deak                     2018-06-19   9879  #define   MG_PLL_BIAS_INIT_DCOAMP_MASK			(0x3f << 24)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9880  #define   MG_PLL_BIAS_BIAS_BONUS(x)			((x) << 16)
bd99ce085f165a0 Imre Deak                     2018-06-19   9881  #define   MG_PLL_BIAS_BIAS_BONUS_MASK			(0xff << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9882  #define   MG_PLL_BIAS_BIASCAL_EN			(1 << 15)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9883  #define   MG_PLL_BIAS_CTRIM(x)				((x) << 8)
bd99ce085f165a0 Imre Deak                     2018-06-19   9884  #define   MG_PLL_BIAS_CTRIM_MASK			(0x1f << 8)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9885  #define   MG_PLL_BIAS_VREF_RDAC(x)			((x) << 5)
bd99ce085f165a0 Imre Deak                     2018-06-19   9886  #define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9887  #define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)
bd99ce085f165a0 Imre Deak                     2018-06-19   9888  #define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9889  #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9890  					_MG_PLL_BIAS_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9891  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9892  #define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9893  #define _MG_PLL_TDC_COLDST_BIAS_PORT2			0x169A18
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9894  #define _MG_PLL_TDC_COLDST_BIAS_PORT3			0x16AA18
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9895  #define _MG_PLL_TDC_COLDST_BIAS_PORT4			0x16BA18
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9896  #define   MG_PLL_TDC_COLDST_IREFINT_EN			(1 << 27)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9897  #define   MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)	((x) << 17)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9898  #define   MG_PLL_TDC_COLDST_COLDSTART			(1 << 16)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9899  #define   MG_PLL_TDC_TDCOVCCORR_EN			(1 << 2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9900  #define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)
584fca111d0cf32 Lucas De Marchi               2019-01-25   9901  #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9902  						   _MG_PLL_TDC_COLDST_BIAS_PORT1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9903  						   _MG_PLL_TDC_COLDST_BIAS_PORT2)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9904  
a927c927de34652 Rodrigo Vivi                  2017-06-09   9905  #define _CNL_DPLL0_CFGCR0		0x6C000
a927c927de34652 Rodrigo Vivi                  2017-06-09   9906  #define _CNL_DPLL1_CFGCR0		0x6C080
a927c927de34652 Rodrigo Vivi                  2017-06-09   9907  #define  DPLL_CFGCR0_HDMI_MODE		(1 << 30)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9908  #define  DPLL_CFGCR0_SSC_ENABLE		(1 << 29)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9909  #define  DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9910  #define  DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9911  #define  DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9912  #define  DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9913  #define  DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9914  #define  DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9915  #define  DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9916  #define  DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9917  #define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9918  #define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9919  #define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
442aa277c066cec Manasi Navare                 2017-09-14   9920  #define  DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9921  #define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9922  #define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9923  #define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9924  
a927c927de34652 Rodrigo Vivi                  2017-06-09   9925  #define _CNL_DPLL0_CFGCR1		0x6C004
a927c927de34652 Rodrigo Vivi                  2017-06-09   9926  #define _CNL_DPLL1_CFGCR1		0x6C084
a927c927de34652 Rodrigo Vivi                  2017-06-09   9927  #define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
a9701a897067db1 Rodrigo Vivi                  2017-07-06   9928  #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9929  #define  DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
51c83cfaf96382a Manasi Navare                 2018-05-23   9930  #define  DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9931  #define  DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9932  #define  DPLL_CFGCR1_KDIV_MASK		(7 << 6)
51c83cfaf96382a Manasi Navare                 2018-05-23   9933  #define  DPLL_CFGCR1_KDIV_SHIFT		(6)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9934  #define  DPLL_CFGCR1_KDIV(x)		((x) << 6)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9935  #define  DPLL_CFGCR1_KDIV_1		(1 << 6)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9936  #define  DPLL_CFGCR1_KDIV_2		(2 << 6)
2ee7fd1efe62557 Ville Syrjälä                 2019-02-07   9937  #define  DPLL_CFGCR1_KDIV_3		(4 << 6)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9938  #define  DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
51c83cfaf96382a Manasi Navare                 2018-05-23   9939  #define  DPLL_CFGCR1_PDIV_SHIFT		(2)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9940  #define  DPLL_CFGCR1_PDIV(x)		((x) << 2)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9941  #define  DPLL_CFGCR1_PDIV_2		(1 << 2)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9942  #define  DPLL_CFGCR1_PDIV_3		(2 << 2)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9943  #define  DPLL_CFGCR1_PDIV_5		(4 << 2)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9944  #define  DPLL_CFGCR1_PDIV_7		(8 << 2)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9945  #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9946  #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
a1c5f1510b3f39d José Roberto de Souza         2019-07-11   9947  #define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9948  #define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
a927c927de34652 Rodrigo Vivi                  2017-06-09   9949  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9950  #define _ICL_DPLL0_CFGCR0		0x164000
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9951  #define _ICL_DPLL1_CFGCR0		0x164080
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9952  #define ICL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9953  						  _ICL_DPLL1_CFGCR0)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9954  
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9955  #define _ICL_DPLL0_CFGCR1		0x164004
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9956  #define _ICL_DPLL1_CFGCR1		0x164084
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9957  #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9958  						  _ICL_DPLL1_CFGCR1)
78b60ce7b96cf18 Paulo Zanoni                  2018-03-28   9959  
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9960  #define _TGL_DPLL0_CFGCR0		0x164284
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9961  #define _TGL_DPLL1_CFGCR0		0x16428C
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9962  /* TODO: add DPLL4 */
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9963  #define _TGL_TBTPLL_CFGCR0		0x16429C
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9964  #define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9965  						  _TGL_DPLL1_CFGCR0, \
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9966  						  _TGL_TBTPLL_CFGCR0)
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9967  
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9968  #define _TGL_DPLL0_CFGCR1		0x164288
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9969  #define _TGL_DPLL1_CFGCR1		0x164290
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9970  /* TODO: add DPLL4 */
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9971  #define _TGL_TBTPLL_CFGCR1		0x1642A0
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9972  #define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9973  						   _TGL_DPLL1_CFGCR1, \
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9974  						   _TGL_TBTPLL_CFGCR1)
36ca5335f202bd5 Lucas De Marchi               2019-07-11   9975  
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9976  /* BXT display engine PLL */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9977  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9978  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9979  #define   BXT_DE_PLL_RATIO_MASK		0xff
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9980  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9981  #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9982  #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9983  #define   BXT_DE_PLL_LOCK		(1 << 30)
945f2672ccbb5c9 Ville Syrjälä                 2017-06-09   9984  #define   CNL_CDCLK_PLL_RATIO(x)	(x)
945f2672ccbb5c9 Ville Syrjälä                 2017-06-09   9985  #define   CNL_CDCLK_PLL_RATIO_MASK	0xff
f8437dd1b5a5a08 Vandana Kannan                2014-11-24   9986  
664326f8a5b7e4a A.Sunil Kamath                2014-11-24   9987  /* GEN9 DC */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9988  #define DC_STATE_EN			_MMIO(0x45504)
13ae3a0d5b139ad Imre Deak                     2015-11-04   9989  #define  DC_STATE_DISABLE		0
664326f8a5b7e4a A.Sunil Kamath                2014-11-24   9990  #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
664326f8a5b7e4a A.Sunil Kamath                2014-11-24   9991  #define  DC_STATE_EN_DC9		(1 << 3)
6b457d31ea0465f A.Sunil Kamath                2015-04-16   9992  #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
6b457d31ea0465f A.Sunil Kamath                2015-04-16   9993  #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
6b457d31ea0465f A.Sunil Kamath                2015-04-16   9994  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18   9995  #define  DC_STATE_DEBUG                  _MMIO(0x45520)
5b076889f6239f8 Mika Kuoppala                 2016-02-19   9996  #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
6b457d31ea0465f A.Sunil Kamath                2015-04-16   9997  #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
6b457d31ea0465f A.Sunil Kamath                2015-04-16   9998  
cbfa59d4b331046 Mahesh Kumar                  2018-08-24   9999  #define BXT_P_CR_MC_BIOS_REQ_0_0_0	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10000  #define  BXT_REQ_DATA_MASK			0x3F
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10001  #define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT		12
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10002  #define  BXT_DRAM_CHANNEL_ACTIVE_MASK		(0xF << 12)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10003  #define  BXT_MEMORY_FREQ_MULTIPLIER_HZ		133333333
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10004  
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10005  #define BXT_D_CR_DRP0_DUNIT8			0x1000
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10006  #define BXT_D_CR_DRP0_DUNIT9			0x1200
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10007  #define  BXT_D_CR_DRP0_DUNIT_START		8
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10008  #define  BXT_D_CR_DRP0_DUNIT_END		11
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10009  #define BXT_D_CR_DRP0_DUNIT(x)	_MMIO(MCHBAR_MIRROR_BASE_SNB + \
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10010  				      _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10011  						 BXT_D_CR_DRP0_DUNIT9))
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10012  #define  BXT_DRAM_RANK_MASK			0x3
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10013  #define  BXT_DRAM_RANK_SINGLE			0x1
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10014  #define  BXT_DRAM_RANK_DUAL			0x3
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10015  #define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10016  #define  BXT_DRAM_WIDTH_SHIFT			4
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10017  #define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10018  #define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10019  #define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10020  #define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10021  #define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10022  #define  BXT_DRAM_SIZE_SHIFT			6
8860343cc9a7f31 Ville Syrjälä                 2019-03-06  10023  #define  BXT_DRAM_SIZE_4GBIT			(0x0 << 6)
8860343cc9a7f31 Ville Syrjälä                 2019-03-06  10024  #define  BXT_DRAM_SIZE_6GBIT			(0x1 << 6)
8860343cc9a7f31 Ville Syrjälä                 2019-03-06  10025  #define  BXT_DRAM_SIZE_8GBIT			(0x2 << 6)
8860343cc9a7f31 Ville Syrjälä                 2019-03-06  10026  #define  BXT_DRAM_SIZE_12GBIT			(0x3 << 6)
8860343cc9a7f31 Ville Syrjälä                 2019-03-06  10027  #define  BXT_DRAM_SIZE_16GBIT			(0x4 << 6)
b185a35216c003f Ville Syrjälä                 2019-03-06  10028  #define  BXT_DRAM_TYPE_MASK			(0x7 << 22)
b185a35216c003f Ville Syrjälä                 2019-03-06  10029  #define  BXT_DRAM_TYPE_SHIFT			22
b185a35216c003f Ville Syrjälä                 2019-03-06  10030  #define  BXT_DRAM_TYPE_DDR3			(0x0 << 22)
b185a35216c003f Ville Syrjälä                 2019-03-06  10031  #define  BXT_DRAM_TYPE_LPDDR3			(0x1 << 22)
b185a35216c003f Ville Syrjälä                 2019-03-06  10032  #define  BXT_DRAM_TYPE_LPDDR4			(0x2 << 22)
b185a35216c003f Ville Syrjälä                 2019-03-06  10033  #define  BXT_DRAM_TYPE_DDR4			(0x4 << 22)
cbfa59d4b331046 Mahesh Kumar                  2018-08-24  10034  
5771caf885ae779 Mahesh Kumar                  2018-08-24  10035  #define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666
5771caf885ae779 Mahesh Kumar                  2018-08-24  10036  #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10037  #define  SKL_REQ_DATA_MASK			(0xF << 0)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10038  
b185a35216c003f Ville Syrjälä                 2019-03-06  10039  #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
b185a35216c003f Ville Syrjälä                 2019-03-06  10040  #define  SKL_DRAM_DDR_TYPE_MASK			(0x3 << 0)
b185a35216c003f Ville Syrjälä                 2019-03-06  10041  #define  SKL_DRAM_DDR_TYPE_DDR4			(0 << 0)
b185a35216c003f Ville Syrjälä                 2019-03-06  10042  #define  SKL_DRAM_DDR_TYPE_DDR3			(1 << 0)
b185a35216c003f Ville Syrjälä                 2019-03-06  10043  #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
b185a35216c003f Ville Syrjälä                 2019-03-06  10044  #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
b185a35216c003f Ville Syrjälä                 2019-03-06  10045  
5771caf885ae779 Mahesh Kumar                  2018-08-24  10046  #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10047  #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10048  #define  SKL_DRAM_S_SHIFT			16
5771caf885ae779 Mahesh Kumar                  2018-08-24  10049  #define  SKL_DRAM_SIZE_MASK			0x3F
5771caf885ae779 Mahesh Kumar                  2018-08-24  10050  #define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10051  #define  SKL_DRAM_WIDTH_SHIFT			8
5771caf885ae779 Mahesh Kumar                  2018-08-24  10052  #define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10053  #define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10054  #define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10055  #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10056  #define  SKL_DRAM_RANK_SHIFT			10
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10057  #define  SKL_DRAM_RANK_1			(0x0 << 10)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10058  #define  SKL_DRAM_RANK_2			(0x1 << 10)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10059  #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10060  #define  CNL_DRAM_SIZE_MASK			0x7F
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10061  #define  CNL_DRAM_WIDTH_MASK			(0x3 << 7)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10062  #define  CNL_DRAM_WIDTH_SHIFT			7
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10063  #define  CNL_DRAM_WIDTH_X8			(0x0 << 7)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10064  #define  CNL_DRAM_WIDTH_X16			(0x1 << 7)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10065  #define  CNL_DRAM_WIDTH_X32			(0x2 << 7)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10066  #define  CNL_DRAM_RANK_MASK			(0x3 << 9)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10067  #define  CNL_DRAM_RANK_SHIFT			9
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10068  #define  CNL_DRAM_RANK_1			(0x0 << 9)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10069  #define  CNL_DRAM_RANK_2			(0x1 << 9)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10070  #define  CNL_DRAM_RANK_3			(0x2 << 9)
6d9c1e92038507d Ville Syrjälä                 2019-03-06  10071  #define  CNL_DRAM_RANK_4			(0x3 << 9)
5771caf885ae779 Mahesh Kumar                  2018-08-24  10072  
9ccd5aeb2901aaa Paulo Zanoni                  2014-07-04  10073  /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
9ccd5aeb2901aaa Paulo Zanoni                  2014-07-04  10074   * since on HSW we can't write to it using I915_WRITE. */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10075  #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10076  #define D_COMP_BDW			_MMIO(0x138144)
be256dc70284c02 Paulo Zanoni                  2013-07-23  10077  #define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)
be256dc70284c02 Paulo Zanoni                  2013-07-23  10078  #define  D_COMP_COMP_FORCE		(1 << 8)
be256dc70284c02 Paulo Zanoni                  2013-07-23  10079  #define  D_COMP_COMP_DISABLE		(1 << 0)
90e8d31c5389006 Eugeni Dodonov                2012-03-29  10080  
69e94b7e0900293 Eugeni Dodonov                2012-03-29  10081  /* Pipe WM_LINETIME - watermark line time */
086f8e84a085a43 Ville Syrjälä                 2015-11-04  10082  #define _PIPE_WM_LINETIME_A		0x45270
086f8e84a085a43 Ville Syrjälä                 2015-11-04  10083  #define _PIPE_WM_LINETIME_B		0x45274
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10084  #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
69e94b7e0900293 Eugeni Dodonov                2012-03-29  10085  #define   PIPE_WM_LINETIME_MASK			(0x1ff)
69e94b7e0900293 Eugeni Dodonov                2012-03-29  10086  #define   PIPE_WM_LINETIME_TIME(x)		((x))
69e94b7e0900293 Eugeni Dodonov                2012-03-29  10087  #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff << 16)
69e94b7e0900293 Eugeni Dodonov                2012-03-29  10088  #define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x) << 16)
96d6e3506739c1c Eugeni Dodonov                2012-03-29  10089  
96d6e3506739c1c Eugeni Dodonov                2012-03-29  10090  /* SFUSE_STRAP */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10091  #define SFUSE_STRAP			_MMIO(0xc2014)
658ac4c6a29cfe7 Damien Lespiau                2014-02-10  10092  #define  SFUSE_STRAP_FUSE_LOCK		(1 << 13)
9d81a99713bc29b Rodrigo Vivi                  2017-06-02  10093  #define  SFUSE_STRAP_RAW_FREQUENCY	(1 << 8)
658ac4c6a29cfe7 Damien Lespiau                2014-02-10  10094  #define  SFUSE_STRAP_DISPLAY_DISABLED	(1 << 7)
65e472e43355488 Ville Syrjälä                 2015-12-01  10095  #define  SFUSE_STRAP_CRT_DISABLED	(1 << 6)
9787e835fa98bbc Rodrigo Vivi                  2018-01-29  10096  #define  SFUSE_STRAP_DDIF_DETECTED	(1 << 3)
96d6e3506739c1c Eugeni Dodonov                2012-03-29  10097  #define  SFUSE_STRAP_DDIB_DETECTED	(1 << 2)
96d6e3506739c1c Eugeni Dodonov                2012-03-29  10098  #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
96d6e3506739c1c Eugeni Dodonov                2012-03-29  10099  #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
96d6e3506739c1c Eugeni Dodonov                2012-03-29  10100  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10101  #define WM_MISC				_MMIO(0x45260)
801bcfffbb0721d Paulo Zanoni                  2013-05-31  10102  #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
801bcfffbb0721d Paulo Zanoni                  2013-05-31  10103  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10104  #define WM_DBG				_MMIO(0x45280)
1544d9d57396d5c Eugeni Dodonov                2012-07-02  10105  #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
1544d9d57396d5c Eugeni Dodonov                2012-07-02  10106  #define  WM_DBG_DISALLOW_MAXFIFO	(1 << 1)
1544d9d57396d5c Eugeni Dodonov                2012-07-02  10107  #define  WM_DBG_DISALLOW_SPRITE		(1 << 2)
1544d9d57396d5c Eugeni Dodonov                2012-07-02  10108  
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10109  /* pipe CSC */
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10110  #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10111  #define _PIPE_A_CSC_COEFF_BY	0x49014
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10112  #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10113  #define _PIPE_A_CSC_COEFF_BU	0x4901c
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10114  #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10115  #define _PIPE_A_CSC_COEFF_BV	0x49024
255fcfbc3c1893c Uma Shankar                   2019-02-11  10116  
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10117  #define _PIPE_A_CSC_MODE	0x49028
255fcfbc3c1893c Uma Shankar                   2019-02-11  10118  #define  ICL_CSC_ENABLE			(1 << 31)
a91de580541c37d Uma Shankar                   2019-02-11  10119  #define  ICL_OUTPUT_CSC_ENABLE		(1 << 30)
29a397ba7a4bded Ville Syrjälä                 2013-04-19  10120  #define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
29a397ba7a4bded Ville Syrjälä                 2013-04-19  10121  #define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
29a397ba7a4bded Ville Syrjälä                 2013-04-19  10122  #define  CSC_MODE_YUV_TO_RGB		(1 << 0)
255fcfbc3c1893c Uma Shankar                   2019-02-11  10123  
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10124  #define _PIPE_A_CSC_PREOFF_HI	0x49030
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10125  #define _PIPE_A_CSC_PREOFF_ME	0x49034
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10126  #define _PIPE_A_CSC_PREOFF_LO	0x49038
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10127  #define _PIPE_A_CSC_POSTOFF_HI	0x49040
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10128  #define _PIPE_A_CSC_POSTOFF_ME	0x49044
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10129  #define _PIPE_A_CSC_POSTOFF_LO	0x49048
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10130  
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10131  #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10132  #define _PIPE_B_CSC_COEFF_BY	0x49114
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10133  #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10134  #define _PIPE_B_CSC_COEFF_BU	0x4911c
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10135  #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10136  #define _PIPE_B_CSC_COEFF_BV	0x49124
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10137  #define _PIPE_B_CSC_MODE	0x49128
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10138  #define _PIPE_B_CSC_PREOFF_HI	0x49130
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10139  #define _PIPE_B_CSC_PREOFF_ME	0x49134
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10140  #define _PIPE_B_CSC_PREOFF_LO	0x49138
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10141  #define _PIPE_B_CSC_POSTOFF_HI	0x49140
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10142  #define _PIPE_B_CSC_POSTOFF_ME	0x49144
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10143  #define _PIPE_B_CSC_POSTOFF_LO	0x49148
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10144  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10145  #define PIPE_CSC_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10146  #define PIPE_CSC_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10147  #define PIPE_CSC_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10148  #define PIPE_CSC_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10149  #define PIPE_CSC_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10150  #define PIPE_CSC_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10151  #define PIPE_CSC_MODE(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10152  #define PIPE_CSC_PREOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10153  #define PIPE_CSC_PREOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10154  #define PIPE_CSC_PREOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10155  #define PIPE_CSC_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10156  #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10157  #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
86d3efce2c37d3f Ville Syrjälä                 2013-01-18  10158  
a91de580541c37d Uma Shankar                   2019-02-11  10159  /* Pipe Output CSC */
a91de580541c37d Uma Shankar                   2019-02-11  10160  #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
a91de580541c37d Uma Shankar                   2019-02-11  10161  #define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
a91de580541c37d Uma Shankar                   2019-02-11  10162  #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
a91de580541c37d Uma Shankar                   2019-02-11  10163  #define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
a91de580541c37d Uma Shankar                   2019-02-11  10164  #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
a91de580541c37d Uma Shankar                   2019-02-11  10165  #define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
a91de580541c37d Uma Shankar                   2019-02-11  10166  #define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
a91de580541c37d Uma Shankar                   2019-02-11  10167  #define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
a91de580541c37d Uma Shankar                   2019-02-11  10168  #define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
a91de580541c37d Uma Shankar                   2019-02-11  10169  #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
a91de580541c37d Uma Shankar                   2019-02-11  10170  #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
a91de580541c37d Uma Shankar                   2019-02-11  10171  #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
a91de580541c37d Uma Shankar                   2019-02-11  10172  
a91de580541c37d Uma Shankar                   2019-02-11  10173  #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
a91de580541c37d Uma Shankar                   2019-02-11  10174  #define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
a91de580541c37d Uma Shankar                   2019-02-11  10175  #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
a91de580541c37d Uma Shankar                   2019-02-11  10176  #define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
a91de580541c37d Uma Shankar                   2019-02-11  10177  #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
a91de580541c37d Uma Shankar                   2019-02-11  10178  #define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
a91de580541c37d Uma Shankar                   2019-02-11  10179  #define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
a91de580541c37d Uma Shankar                   2019-02-11  10180  #define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
a91de580541c37d Uma Shankar                   2019-02-11  10181  #define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
a91de580541c37d Uma Shankar                   2019-02-11  10182  #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
a91de580541c37d Uma Shankar                   2019-02-11  10183  #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
a91de580541c37d Uma Shankar                   2019-02-11  10184  #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
a91de580541c37d Uma Shankar                   2019-02-11  10185  
a91de580541c37d Uma Shankar                   2019-02-11  10186  #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe,\
a91de580541c37d Uma Shankar                   2019-02-11  10187  							   _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
a91de580541c37d Uma Shankar                   2019-02-11  10188  							   _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
a91de580541c37d Uma Shankar                   2019-02-11  10189  #define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10190  							   _PIPE_A_OUTPUT_CSC_COEFF_BY, \
a91de580541c37d Uma Shankar                   2019-02-11  10191  							   _PIPE_B_OUTPUT_CSC_COEFF_BY)
a91de580541c37d Uma Shankar                   2019-02-11  10192  #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10193  							   _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
a91de580541c37d Uma Shankar                   2019-02-11  10194  							   _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
a91de580541c37d Uma Shankar                   2019-02-11  10195  #define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10196  							   _PIPE_A_OUTPUT_CSC_COEFF_BU, \
a91de580541c37d Uma Shankar                   2019-02-11  10197  							   _PIPE_B_OUTPUT_CSC_COEFF_BU)
a91de580541c37d Uma Shankar                   2019-02-11  10198  #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10199  							   _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
a91de580541c37d Uma Shankar                   2019-02-11  10200  							   _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
a91de580541c37d Uma Shankar                   2019-02-11  10201  #define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10202  							   _PIPE_A_OUTPUT_CSC_COEFF_BV, \
a91de580541c37d Uma Shankar                   2019-02-11  10203  							   _PIPE_B_OUTPUT_CSC_COEFF_BV)
a91de580541c37d Uma Shankar                   2019-02-11  10204  #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10205  							   _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
a91de580541c37d Uma Shankar                   2019-02-11  10206  							   _PIPE_B_OUTPUT_CSC_PREOFF_HI)
a91de580541c37d Uma Shankar                   2019-02-11  10207  #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)		_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10208  							   _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
a91de580541c37d Uma Shankar                   2019-02-11  10209  							   _PIPE_B_OUTPUT_CSC_PREOFF_ME)
a91de580541c37d Uma Shankar                   2019-02-11  10210  #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10211  							   _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
a91de580541c37d Uma Shankar                   2019-02-11  10212  							   _PIPE_B_OUTPUT_CSC_PREOFF_LO)
a91de580541c37d Uma Shankar                   2019-02-11  10213  #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10214  							   _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
a91de580541c37d Uma Shankar                   2019-02-11  10215  							   _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
a91de580541c37d Uma Shankar                   2019-02-11  10216  #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10217  							   _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
a91de580541c37d Uma Shankar                   2019-02-11  10218  							   _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
a91de580541c37d Uma Shankar                   2019-02-11  10219  #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, \
a91de580541c37d Uma Shankar                   2019-02-11  10220  							   _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
a91de580541c37d Uma Shankar                   2019-02-11  10221  							   _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
a91de580541c37d Uma Shankar                   2019-02-11  10222  
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10223  /* pipe degamma/gamma LUTs on IVB+ */
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10224  #define _PAL_PREC_INDEX_A	0x4A400
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10225  #define _PAL_PREC_INDEX_B	0x4AC00
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10226  #define _PAL_PREC_INDEX_C	0x4B400
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10227  #define   PAL_PREC_10_12_BIT		(0 << 31)
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10228  #define   PAL_PREC_SPLIT_MODE		(1 << 31)
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10229  #define   PAL_PREC_AUTO_INCREMENT	(1 << 15)
2fcb206654e8b38 Ander Conselvan de Oliveira   2017-01-26  10230  #define   PAL_PREC_INDEX_VALUE_MASK	(0x3ff << 0)
5bda1aca5d9475e Ville Syrjälä                 2019-04-01  10231  #define   PAL_PREC_INDEX_VALUE(x)	((x) << 0)
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10232  #define _PAL_PREC_DATA_A	0x4A404
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10233  #define _PAL_PREC_DATA_B	0x4AC04
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10234  #define _PAL_PREC_DATA_C	0x4B404
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10235  #define _PAL_PREC_GC_MAX_A	0x4A410
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10236  #define _PAL_PREC_GC_MAX_B	0x4AC10
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10237  #define _PAL_PREC_GC_MAX_C	0x4B410
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10238  #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10239  #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10240  #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10241  #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10242  #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10243  #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10244  
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10245  #define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10246  #define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10247  #define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10248  #define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
502da13a72dad49 Uma Shankar                   2019-03-29  10249  #define PREC_PAL_EXT2_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
82cf435b3134a5f Lionel Landwerlin             2016-03-16  10250  
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10251  #define _PRE_CSC_GAMC_INDEX_A	0x4A484
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10252  #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10253  #define _PRE_CSC_GAMC_INDEX_C	0x4B484
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10254  #define   PRE_CSC_GAMC_AUTO_INCREMENT	(1 << 10)
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10255  #define _PRE_CSC_GAMC_DATA_A	0x4A488
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10256  #define _PRE_CSC_GAMC_DATA_B	0x4AC88
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10257  #define _PRE_CSC_GAMC_DATA_C	0x4B488
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10258  
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10259  #define PRE_CSC_GAMC_INDEX(pipe)	_MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10260  #define PRE_CSC_GAMC_DATA(pipe)		_MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
9751bafc43d5992 Ander Conselvan de Oliveira   2017-01-27  10261  
377c70edd486754 Uma Shankar                   2019-06-12  10262  /* ICL Multi segmented gamma */
377c70edd486754 Uma Shankar                   2019-06-12  10263  #define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
377c70edd486754 Uma Shankar                   2019-06-12  10264  #define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
377c70edd486754 Uma Shankar                   2019-06-12  10265  #define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT		REG_BIT(15)
377c70edd486754 Uma Shankar                   2019-06-12  10266  #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK	REG_GENMASK(4, 0)
377c70edd486754 Uma Shankar                   2019-06-12  10267  
377c70edd486754 Uma Shankar                   2019-06-12  10268  #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
377c70edd486754 Uma Shankar                   2019-06-12  10269  #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
377c70edd486754 Uma Shankar                   2019-06-12  10270  
377c70edd486754 Uma Shankar                   2019-06-12  10271  #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
377c70edd486754 Uma Shankar                   2019-06-12  10272  					_PAL_PREC_MULTI_SEG_INDEX_A, \
377c70edd486754 Uma Shankar                   2019-06-12  10273  					_PAL_PREC_MULTI_SEG_INDEX_B)
377c70edd486754 Uma Shankar                   2019-06-12  10274  #define PREC_PAL_MULTI_SEG_DATA(pipe)	_MMIO_PIPE(pipe, \
377c70edd486754 Uma Shankar                   2019-06-12  10275  					_PAL_PREC_MULTI_SEG_DATA_A, \
377c70edd486754 Uma Shankar                   2019-06-12  10276  					_PAL_PREC_MULTI_SEG_DATA_B)
377c70edd486754 Uma Shankar                   2019-06-12  10277  
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10278  /* pipe CSC & degamma/gamma LUTs on CHV */
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10279  #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10280  #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10281  #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10282  #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10283  #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10284  #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10285  #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10286  #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10287  #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10288  #define   CGM_PIPE_MODE_CSC	(1 << 1)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10289  #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10290  
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10291  #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10292  #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10293  #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10294  #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10295  #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10296  #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10297  #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10298  #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10299  
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10300  #define CGM_PIPE_CSC_COEFF01(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10301  #define CGM_PIPE_CSC_COEFF23(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10302  #define CGM_PIPE_CSC_COEFF45(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10303  #define CGM_PIPE_CSC_COEFF67(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10304  #define CGM_PIPE_CSC_COEFF8(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10305  #define CGM_PIPE_DEGAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10306  #define CGM_PIPE_GAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10307  #define CGM_PIPE_MODE(pipe)		_MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
29dc3739e50da35 Lionel Landwerlin             2016-03-16  10308  
e7d7cad08d35329 Jani Nikula                   2014-11-14  10309  /* MIPI DSI registers */
e7d7cad08d35329 Jani Nikula                   2014-11-14  10310  
0ad4dc887d41684 Hans de Goede                 2017-05-18  10311  #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10312  #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
3230bf14c14e04d Jani Nikula                   2013-08-27  10313  
292272ee7e9e41e Madhav Chauhan                2018-10-15  10314  /* Gen11 DSI */
292272ee7e9e41e Madhav Chauhan                2018-10-15  10315  #define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
292272ee7e9e41e Madhav Chauhan                2018-10-15  10316  						    dsi0, dsi1)
292272ee7e9e41e Madhav Chauhan                2018-10-15  10317  
bcc65700484115d Deepak M                      2017-02-17  10318  #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
bcc65700484115d Deepak M                      2017-02-17  10319  #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
bcc65700484115d Deepak M                      2017-02-17  10320  #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
bcc65700484115d Deepak M                      2017-02-17  10321  #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
bcc65700484115d Deepak M                      2017-02-17  10322  
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10323  #define _ICL_DSI_ESC_CLK_DIV0		0x6b090
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10324  #define _ICL_DSI_ESC_CLK_DIV1		0x6b890
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10325  #define ICL_DSI_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10326  							_ICL_DSI_ESC_CLK_DIV0, \
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10327  							_ICL_DSI_ESC_CLK_DIV1)
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10328  #define _ICL_DPHY_ESC_CLK_DIV0		0x162190
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10329  #define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10330  #define ICL_DPHY_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10331  						_ICL_DPHY_ESC_CLK_DIV0, \
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10332  						_ICL_DPHY_ESC_CLK_DIV1)
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10333  #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10334  #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10335  #define  ICL_ESC_CLK_DIV_MASK			0x1ff
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10336  #define  ICL_ESC_CLK_DIV_SHIFT			0
fcfe0bdcb1911a4 Madhav Chauhan                2018-07-05  10337  #define DSI_MAX_ESC_CLK			20000		/* in KHz */
27efd2566cb89b7 Madhav Chauhan                2018-07-05  10338  
aec0246f3e38820 Uma Shankar                   2017-09-25  10339  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
aec0246f3e38820 Uma Shankar                   2017-09-25  10340  #define GEN4_TIMESTAMP		_MMIO(0x2358)
aec0246f3e38820 Uma Shankar                   2017-09-25  10341  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
aec0246f3e38820 Uma Shankar                   2017-09-25  10342  #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
aec0246f3e38820 Uma Shankar                   2017-09-25  10343  
dab91783338bd3d Lionel Landwerlin             2017-11-10  10344  #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
dab91783338bd3d Lionel Landwerlin             2017-11-10  10345  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
dab91783338bd3d Lionel Landwerlin             2017-11-10  10346  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
dab91783338bd3d Lionel Landwerlin             2017-11-10  10347  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT	12
dab91783338bd3d Lionel Landwerlin             2017-11-10  10348  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
dab91783338bd3d Lionel Landwerlin             2017-11-10  10349  
aec0246f3e38820 Uma Shankar                   2017-09-25  10350  #define _PIPE_FRMTMSTMP_A		0x70048
aec0246f3e38820 Uma Shankar                   2017-09-25  10351  #define PIPE_FRMTMSTMP(pipe)		\
aec0246f3e38820 Uma Shankar                   2017-09-25  10352  			_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
aec0246f3e38820 Uma Shankar                   2017-09-25  10353  
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10354  /* BXT MIPI clock controls */
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10355  #define BXT_MAX_VAR_OUTPUT_KHZ			39500
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10356  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10357  #define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10358  #define  BXT_MIPI1_DIV_SHIFT			26
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10359  #define  BXT_MIPI2_DIV_SHIFT			10
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10360  #define  BXT_MIPI_DIV_SHIFT(port)		\
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10361  			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10362  					BXT_MIPI2_DIV_SHIFT)
782d25cac637345 Deepak M                      2016-02-15  10363  
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10364  /* TX control divider to select actual TX clock output from (8x/var) */
782d25cac637345 Deepak M                      2016-02-15  10365  #define  BXT_MIPI1_TX_ESCLK_SHIFT		26
782d25cac637345 Deepak M                      2016-02-15  10366  #define  BXT_MIPI2_TX_ESCLK_SHIFT		10
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10367  #define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10368  			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10369  					BXT_MIPI2_TX_ESCLK_SHIFT)
782d25cac637345 Deepak M                      2016-02-15  10370  #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
782d25cac637345 Deepak M                      2016-02-15  10371  #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10372  #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10373  			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10374  					BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
782d25cac637345 Deepak M                      2016-02-15  10375  #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)	\
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12  10376  		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
782d25cac637345 Deepak M                      2016-02-15  10377  /* RX upper control divider to select actual RX clock output from 8x */
782d25cac637345 Deepak M                      2016-02-15  10378  #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT		21
782d25cac637345 Deepak M                      2016-02-15  10379  #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT		5
782d25cac637345 Deepak M                      2016-02-15  10380  #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)		\
782d25cac637345 Deepak M                      2016-02-15  10381  			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
782d25cac637345 Deepak M                      2016-02-15  10382  					BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
782d25cac637345 Deepak M                      2016-02-15  10383  #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 21)
782d25cac637345 Deepak M                      2016-02-15  10384  #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 5)
782d25cac637345 Deepak M                      2016-02-15  10385  #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)	\
782d25cac637345 Deepak M                      2016-02-15  10386  			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
782d25cac637345 Deepak M                      2016-02-15  10387  					BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
782d25cac637345 Deepak M                      2016-02-15  10388  #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)	\
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12  10389  		(((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
782d25cac637345 Deepak M                      2016-02-15  10390  /* 8/3X divider to select the actual 8/3X clock output from 8x */
782d25cac637345 Deepak M                      2016-02-15  10391  #define  BXT_MIPI1_8X_BY3_SHIFT                19
782d25cac637345 Deepak M                      2016-02-15  10392  #define  BXT_MIPI2_8X_BY3_SHIFT                3
782d25cac637345 Deepak M                      2016-02-15  10393  #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
782d25cac637345 Deepak M                      2016-02-15  10394  			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
782d25cac637345 Deepak M                      2016-02-15  10395  					BXT_MIPI2_8X_BY3_SHIFT)
782d25cac637345 Deepak M                      2016-02-15  10396  #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
782d25cac637345 Deepak M                      2016-02-15  10397  #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
782d25cac637345 Deepak M                      2016-02-15  10398  #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
782d25cac637345 Deepak M                      2016-02-15  10399  			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
782d25cac637345 Deepak M                      2016-02-15  10400  						BXT_MIPI2_8X_BY3_DIVIDER_MASK)
782d25cac637345 Deepak M                      2016-02-15  10401  #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12  10402  			(((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
782d25cac637345 Deepak M                      2016-02-15  10403  /* RX lower control divider to select actual RX clock output from 8x */
782d25cac637345 Deepak M                      2016-02-15  10404  #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT		16
782d25cac637345 Deepak M                      2016-02-15  10405  #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
782d25cac637345 Deepak M                      2016-02-15  10406  #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)		\
782d25cac637345 Deepak M                      2016-02-15  10407  			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
782d25cac637345 Deepak M                      2016-02-15  10408  					BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
782d25cac637345 Deepak M                      2016-02-15  10409  #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 16)
782d25cac637345 Deepak M                      2016-02-15  10410  #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
782d25cac637345 Deepak M                      2016-02-15  10411  #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)	\
782d25cac637345 Deepak M                      2016-02-15  10412  			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
782d25cac637345 Deepak M                      2016-02-15  10413  					BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
782d25cac637345 Deepak M                      2016-02-15  10414  #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)	\
9e8789ec967a2d5 Paulo Zanoni                  2018-06-12  10415  		(((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
782d25cac637345 Deepak M                      2016-02-15  10416  
782d25cac637345 Deepak M                      2016-02-15  10417  #define RX_DIVIDER_BIT_1_2                     0x3
782d25cac637345 Deepak M                      2016-02-15  10418  #define RX_DIVIDER_BIT_3_4                     0xC
11b8e4f58e1baa9 Shashank Sharma               2015-09-23  10419  
d2e08c0f34438af Shashank Sharma               2015-09-01  10420  /* BXT MIPI mode configure */
d2e08c0f34438af Shashank Sharma               2015-09-01  10421  #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
d2e08c0f34438af Shashank Sharma               2015-09-01  10422  #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10423  #define  BXT_MIPI_TRANS_HACTIVE(tc)	_MMIO_MIPI(tc, \
d2e08c0f34438af Shashank Sharma               2015-09-01  10424  		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
d2e08c0f34438af Shashank Sharma               2015-09-01  10425  
d2e08c0f34438af Shashank Sharma               2015-09-01  10426  #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
d2e08c0f34438af Shashank Sharma               2015-09-01  10427  #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10428  #define  BXT_MIPI_TRANS_VACTIVE(tc)	_MMIO_MIPI(tc, \
d2e08c0f34438af Shashank Sharma               2015-09-01  10429  		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
d2e08c0f34438af Shashank Sharma               2015-09-01  10430  
d2e08c0f34438af Shashank Sharma               2015-09-01  10431  #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
d2e08c0f34438af Shashank Sharma               2015-09-01  10432  #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10433  #define  BXT_MIPI_TRANS_VTOTAL(tc)	_MMIO_MIPI(tc, \
d2e08c0f34438af Shashank Sharma               2015-09-01  10434  		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
d2e08c0f34438af Shashank Sharma               2015-09-01  10435  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10436  #define BXT_DSI_PLL_CTL			_MMIO(0x161000)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10437  #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10438  #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10439  #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
f340c2ff5ebdd21 Deepak M                      2017-02-17  10440  #define  BXT_DSIC_16X_BY1		(0 << 10)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10441  #define  BXT_DSIC_16X_BY2		(1 << 10)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10442  #define  BXT_DSIC_16X_BY3		(2 << 10)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10443  #define  BXT_DSIC_16X_BY4		(3 << 10)
db18b6a64ca3fb2 Imre Deak                     2016-03-24  10444  #define  BXT_DSIC_16X_MASK		(3 << 10)
f340c2ff5ebdd21 Deepak M                      2017-02-17  10445  #define  BXT_DSIA_16X_BY1		(0 << 8)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10446  #define  BXT_DSIA_16X_BY2		(1 << 8)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10447  #define  BXT_DSIA_16X_BY3		(2 << 8)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10448  #define  BXT_DSIA_16X_BY4		(3 << 8)
db18b6a64ca3fb2 Imre Deak                     2016-03-24  10449  #define  BXT_DSIA_16X_MASK		(3 << 8)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10450  #define  BXT_DSI_FREQ_SEL_SHIFT		8
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10451  #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10452  
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10453  #define BXT_DSI_PLL_RATIO_MAX		0x7D
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10454  #define BXT_DSI_PLL_RATIO_MIN		0x22
f340c2ff5ebdd21 Deepak M                      2017-02-17  10455  #define GLK_DSI_PLL_RATIO_MAX		0x6F
f340c2ff5ebdd21 Deepak M                      2017-02-17  10456  #define GLK_DSI_PLL_RATIO_MIN		0x22
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10457  #define BXT_DSI_PLL_RATIO_MASK		0xFF
61ad992875639b0 Deepak M                      2015-12-04  10458  #define BXT_REF_CLOCK_KHZ		19200
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10459  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10460  #define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10461  #define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10462  #define  BXT_DSI_PLL_LOCKED		(1 << 30)
cfe01a5eba1ff57 Shashank Sharma               2015-09-01  10463  
3230bf14c14e04d Jani Nikula                   2013-08-27  10464  #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10465  #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10466  #define MIPI_PORT_CTRL(port)	_MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
37ab0810c9b7e06 Shashank Sharma               2015-09-01  10467  
37ab0810c9b7e06 Shashank Sharma               2015-09-01  10468   /* BXT port control */
37ab0810c9b7e06 Shashank Sharma               2015-09-01  10469  #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
37ab0810c9b7e06 Shashank Sharma               2015-09-01  10470  #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10471  #define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
37ab0810c9b7e06 Shashank Sharma               2015-09-01  10472  
21652f3b0d48749 Madhav Chauhan                2018-07-05  10473  /* ICL DSI MODE control */
21652f3b0d48749 Madhav Chauhan                2018-07-05  10474  #define _ICL_DSI_IO_MODECTL_0				0x6B094
21652f3b0d48749 Madhav Chauhan                2018-07-05  10475  #define _ICL_DSI_IO_MODECTL_1				0x6B894
21652f3b0d48749 Madhav Chauhan                2018-07-05  10476  #define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
21652f3b0d48749 Madhav Chauhan                2018-07-05  10477  						    _ICL_DSI_IO_MODECTL_0, \
21652f3b0d48749 Madhav Chauhan                2018-07-05  10478  						    _ICL_DSI_IO_MODECTL_1)
21652f3b0d48749 Madhav Chauhan                2018-07-05  10479  #define  COMBO_PHY_MODE_DSI				(1 << 0)
21652f3b0d48749 Madhav Chauhan                2018-07-05  10480  
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10481  /* Display Stream Splitter Control */
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10482  #define DSS_CTL1				_MMIO(0x67400)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10483  #define  SPLITTER_ENABLE			(1 << 31)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10484  #define  JOINER_ENABLE				(1 << 30)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10485  #define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10486  #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10487  #define  OVERLAP_PIXELS_MASK			(0xf << 16)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10488  #define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10489  #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10490  #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10491  #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10492  
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10493  #define DSS_CTL2				_MMIO(0x67404)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10494  #define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10495  #define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10496  #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10497  #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10498  
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10499  #define _ICL_PIPE_DSS_CTL1_PB			0x78200
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10500  #define _ICL_PIPE_DSS_CTL1_PC			0x78400
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10501  #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10502  							   _ICL_PIPE_DSS_CTL1_PB, \
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10503  							   _ICL_PIPE_DSS_CTL1_PC)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10504  #define  BIG_JOINER_ENABLE			(1 << 29)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10505  #define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10506  #define  VGA_CENTERING_ENABLE			(1 << 27)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10507  
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10508  #define _ICL_PIPE_DSS_CTL2_PB			0x78204
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10509  #define _ICL_PIPE_DSS_CTL2_PC			0x78404
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10510  #define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10511  							   _ICL_PIPE_DSS_CTL2_PB, \
18cde299df33ff7 Anusha Srivatsa               2018-11-01  10512  							   _ICL_PIPE_DSS_CTL2_PC)
8b1b558d690aa37 Anusha Srivatsa               2018-10-30  10513  
1881a4234ef0375 Uma Shankar                   2017-01-25  10514  #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
1881a4234ef0375 Uma Shankar                   2017-01-25  10515  #define  STAP_SELECT					(1 << 0)
1881a4234ef0375 Uma Shankar                   2017-01-25  10516  
1881a4234ef0375 Uma Shankar                   2017-01-25  10517  #define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
1881a4234ef0375 Uma Shankar                   2017-01-25  10518  #define  HS_IO_CTRL_SELECT				(1 << 0)
1881a4234ef0375 Uma Shankar                   2017-01-25  10519  
e7d7cad08d35329 Jani Nikula                   2014-11-14  10520  #define  DPI_ENABLE					(1 << 31) /* A + C */
3230bf14c14e04d Jani Nikula                   2013-08-27  10521  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
3230bf14c14e04d Jani Nikula                   2013-08-27  10522  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
369602d370fac9d Gaurav K Singh                2014-12-05  10523  #define  DUAL_LINK_MODE_SHIFT				26
3230bf14c14e04d Jani Nikula                   2013-08-27  10524  #define  DUAL_LINK_MODE_MASK				(1 << 26)
3230bf14c14e04d Jani Nikula                   2013-08-27  10525  #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
3230bf14c14e04d Jani Nikula                   2013-08-27  10526  #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10527  #define  DITHERING_ENABLE				(1 << 25) /* A + C */
3230bf14c14e04d Jani Nikula                   2013-08-27  10528  #define  FLOPPED_HSTX					(1 << 23)
3230bf14c14e04d Jani Nikula                   2013-08-27  10529  #define  DE_INVERT					(1 << 19) /* XXX */
3230bf14c14e04d Jani Nikula                   2013-08-27  10530  #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
3230bf14c14e04d Jani Nikula                   2013-08-27  10531  #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
3230bf14c14e04d Jani Nikula                   2013-08-27  10532  #define  AFE_LATCHOUT					(1 << 17)
3230bf14c14e04d Jani Nikula                   2013-08-27  10533  #define  LP_OUTPUT_HOLD					(1 << 16)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10534  #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
e7d7cad08d35329 Jani Nikula                   2014-11-14  10535  #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10536  #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
e7d7cad08d35329 Jani Nikula                   2014-11-14  10537  #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
3230bf14c14e04d Jani Nikula                   2013-08-27  10538  #define  CSB_SHIFT					9
3230bf14c14e04d Jani Nikula                   2013-08-27  10539  #define  CSB_MASK					(3 << 9)
3230bf14c14e04d Jani Nikula                   2013-08-27  10540  #define  CSB_20MHZ					(0 << 9)
3230bf14c14e04d Jani Nikula                   2013-08-27  10541  #define  CSB_10MHZ					(1 << 9)
3230bf14c14e04d Jani Nikula                   2013-08-27  10542  #define  CSB_40MHZ					(2 << 9)
3230bf14c14e04d Jani Nikula                   2013-08-27  10543  #define  BANDGAP_MASK					(1 << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10544  #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10545  #define  BANDGAP_LNC_CIRCUIT				(1 << 8)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10546  #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
e7d7cad08d35329 Jani Nikula                   2014-11-14  10547  #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10548  #define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
e7d7cad08d35329 Jani Nikula                   2014-11-14  10549  #define  TEARING_EFFECT_SHIFT				2 /* A + C */
3230bf14c14e04d Jani Nikula                   2013-08-27  10550  #define  TEARING_EFFECT_MASK				(3 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10551  #define  TEARING_EFFECT_OFF				(0 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10552  #define  TEARING_EFFECT_DSI				(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10553  #define  TEARING_EFFECT_GPIO				(2 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10554  #define  LANE_CONFIGURATION_SHIFT			0
3230bf14c14e04d Jani Nikula                   2013-08-27  10555  #define  LANE_CONFIGURATION_MASK			(3 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10556  #define  LANE_CONFIGURATION_4LANE			(0 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10557  #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10558  #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10559  
3230bf14c14e04d Jani Nikula                   2013-08-27  10560  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10561  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10562  #define MIPI_TEARING_CTRL(port)			_MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
3230bf14c14e04d Jani Nikula                   2013-08-27  10563  #define  TEARING_EFFECT_DELAY_SHIFT			0
3230bf14c14e04d Jani Nikula                   2013-08-27  10564  #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10565  
3230bf14c14e04d Jani Nikula                   2013-08-27  10566  /* XXX: all bits reserved */
3230bf14c14e04d Jani Nikula                   2013-08-27  10567  #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10568  
3230bf14c14e04d Jani Nikula                   2013-08-27  10569  /* MIPI DSI Controller and D-PHY registers */
3230bf14c14e04d Jani Nikula                   2013-08-27  10570  
4ad83e94059969b Shashank Sharma               2014-06-02  10571  #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10572  #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10573  #define MIPI_DEVICE_READY(port)		_MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
3230bf14c14e04d Jani Nikula                   2013-08-27  10574  #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
3230bf14c14e04d Jani Nikula                   2013-08-27  10575  #define  ULPS_STATE_MASK				(3 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10576  #define  ULPS_STATE_ENTER				(2 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10577  #define  ULPS_STATE_EXIT				(1 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10578  #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10579  #define  DEVICE_READY					(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10580  
4ad83e94059969b Shashank Sharma               2014-06-02  10581  #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10582  #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10583  #define MIPI_INTR_STAT(port)		_MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
4ad83e94059969b Shashank Sharma               2014-06-02  10584  #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10585  #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10586  #define MIPI_INTR_EN(port)		_MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
3230bf14c14e04d Jani Nikula                   2013-08-27  10587  #define  TEARING_EFFECT					(1 << 31)
3230bf14c14e04d Jani Nikula                   2013-08-27  10588  #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
3230bf14c14e04d Jani Nikula                   2013-08-27  10589  #define  GEN_READ_DATA_AVAIL				(1 << 29)
3230bf14c14e04d Jani Nikula                   2013-08-27  10590  #define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
3230bf14c14e04d Jani Nikula                   2013-08-27  10591  #define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
3230bf14c14e04d Jani Nikula                   2013-08-27  10592  #define  RX_PROT_VIOLATION				(1 << 26)
3230bf14c14e04d Jani Nikula                   2013-08-27  10593  #define  RX_INVALID_TX_LENGTH				(1 << 25)
3230bf14c14e04d Jani Nikula                   2013-08-27  10594  #define  ACK_WITH_NO_ERROR				(1 << 24)
3230bf14c14e04d Jani Nikula                   2013-08-27  10595  #define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
3230bf14c14e04d Jani Nikula                   2013-08-27  10596  #define  LP_RX_TIMEOUT					(1 << 22)
3230bf14c14e04d Jani Nikula                   2013-08-27  10597  #define  HS_TX_TIMEOUT					(1 << 21)
3230bf14c14e04d Jani Nikula                   2013-08-27  10598  #define  DPI_FIFO_UNDERRUN				(1 << 20)
3230bf14c14e04d Jani Nikula                   2013-08-27  10599  #define  LOW_CONTENTION					(1 << 19)
3230bf14c14e04d Jani Nikula                   2013-08-27  10600  #define  HIGH_CONTENTION				(1 << 18)
3230bf14c14e04d Jani Nikula                   2013-08-27  10601  #define  TXDSI_VC_ID_INVALID				(1 << 17)
3230bf14c14e04d Jani Nikula                   2013-08-27  10602  #define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
3230bf14c14e04d Jani Nikula                   2013-08-27  10603  #define  TXCHECKSUM_ERROR				(1 << 15)
3230bf14c14e04d Jani Nikula                   2013-08-27  10604  #define  TXECC_MULTIBIT_ERROR				(1 << 14)
3230bf14c14e04d Jani Nikula                   2013-08-27  10605  #define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10606  #define  TXFALSE_CONTROL_ERROR				(1 << 12)
3230bf14c14e04d Jani Nikula                   2013-08-27  10607  #define  RXDSI_VC_ID_INVALID				(1 << 11)
3230bf14c14e04d Jani Nikula                   2013-08-27  10608  #define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
3230bf14c14e04d Jani Nikula                   2013-08-27  10609  #define  RXCHECKSUM_ERROR				(1 << 9)
3230bf14c14e04d Jani Nikula                   2013-08-27  10610  #define  RXECC_MULTIBIT_ERROR				(1 << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10611  #define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
3230bf14c14e04d Jani Nikula                   2013-08-27  10612  #define  RXFALSE_CONTROL_ERROR				(1 << 6)
3230bf14c14e04d Jani Nikula                   2013-08-27  10613  #define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  10614  #define  RX_LP_TX_SYNC_ERROR				(1 << 4)
3230bf14c14e04d Jani Nikula                   2013-08-27  10615  #define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  10616  #define  RXEOT_SYNC_ERROR				(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10617  #define  RXSOT_SYNC_ERROR				(1 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10618  #define  RXSOT_ERROR					(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10619  
4ad83e94059969b Shashank Sharma               2014-06-02  10620  #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10621  #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10622  #define MIPI_DSI_FUNC_PRG(port)		_MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
3230bf14c14e04d Jani Nikula                   2013-08-27  10623  #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10624  #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10625  #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10626  #define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10627  #define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10628  #define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10629  #define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
3230bf14c14e04d Jani Nikula                   2013-08-27  10630  #define  VID_MODE_FORMAT_MASK				(0xf << 7)
3230bf14c14e04d Jani Nikula                   2013-08-27  10631  #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
3230bf14c14e04d Jani Nikula                   2013-08-27  10632  #define  VID_MODE_FORMAT_RGB565				(1 << 7)
42c151e65e80d22 Jani Nikula                   2016-03-16  10633  #define  VID_MODE_FORMAT_RGB666_PACKED			(2 << 7)
42c151e65e80d22 Jani Nikula                   2016-03-16  10634  #define  VID_MODE_FORMAT_RGB666				(3 << 7)
3230bf14c14e04d Jani Nikula                   2013-08-27  10635  #define  VID_MODE_FORMAT_RGB888				(4 << 7)
3230bf14c14e04d Jani Nikula                   2013-08-27  10636  #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
3230bf14c14e04d Jani Nikula                   2013-08-27  10637  #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  10638  #define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
3230bf14c14e04d Jani Nikula                   2013-08-27  10639  #define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  10640  #define  DATA_LANES_PRG_REG_SHIFT			0
3230bf14c14e04d Jani Nikula                   2013-08-27  10641  #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10642  
4ad83e94059969b Shashank Sharma               2014-06-02  10643  #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10644  #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10645  #define MIPI_HS_TX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10646  #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
3230bf14c14e04d Jani Nikula                   2013-08-27  10647  
4ad83e94059969b Shashank Sharma               2014-06-02  10648  #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10649  #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10650  #define MIPI_LP_RX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10651  #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
3230bf14c14e04d Jani Nikula                   2013-08-27  10652  
4ad83e94059969b Shashank Sharma               2014-06-02  10653  #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10654  #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10655  #define MIPI_TURN_AROUND_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10656  #define  TURN_AROUND_TIMEOUT_MASK			0x3f
3230bf14c14e04d Jani Nikula                   2013-08-27  10657  
4ad83e94059969b Shashank Sharma               2014-06-02  10658  #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10659  #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10660  #define MIPI_DEVICE_RESET_TIMER(port)	_MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
3230bf14c14e04d Jani Nikula                   2013-08-27  10661  #define  DEVICE_RESET_TIMER_MASK			0xffff
3230bf14c14e04d Jani Nikula                   2013-08-27  10662  
4ad83e94059969b Shashank Sharma               2014-06-02  10663  #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10664  #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10665  #define MIPI_DPI_RESOLUTION(port)	_MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
3230bf14c14e04d Jani Nikula                   2013-08-27  10666  #define  VERTICAL_ADDRESS_SHIFT				16
3230bf14c14e04d Jani Nikula                   2013-08-27  10667  #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
3230bf14c14e04d Jani Nikula                   2013-08-27  10668  #define  HORIZONTAL_ADDRESS_SHIFT			0
3230bf14c14e04d Jani Nikula                   2013-08-27  10669  #define  HORIZONTAL_ADDRESS_MASK			0xffff
3230bf14c14e04d Jani Nikula                   2013-08-27  10670  
4ad83e94059969b Shashank Sharma               2014-06-02  10671  #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10672  #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10673  #define MIPI_DBI_FIFO_THROTTLE(port)	_MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
3230bf14c14e04d Jani Nikula                   2013-08-27  10674  #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10675  #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10676  #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10677  
3230bf14c14e04d Jani Nikula                   2013-08-27  10678  /* regs below are bits 15:0 */
4ad83e94059969b Shashank Sharma               2014-06-02  10679  #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10680  #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10681  #define MIPI_HSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10682  
4ad83e94059969b Shashank Sharma               2014-06-02  10683  #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10684  #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10685  #define MIPI_HBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10686  
4ad83e94059969b Shashank Sharma               2014-06-02  10687  #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10688  #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10689  #define MIPI_HFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10690  
4ad83e94059969b Shashank Sharma               2014-06-02  10691  #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10692  #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10693  #define MIPI_HACTIVE_AREA_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10694  
4ad83e94059969b Shashank Sharma               2014-06-02  10695  #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10696  #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10697  #define MIPI_VSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10698  
4ad83e94059969b Shashank Sharma               2014-06-02  10699  #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10700  #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10701  #define MIPI_VBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10702  
4ad83e94059969b Shashank Sharma               2014-06-02  10703  #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10704  #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10705  #define MIPI_VFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10706  
4ad83e94059969b Shashank Sharma               2014-06-02  10707  #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10708  #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10709  #define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MMIO_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
4ad83e94059969b Shashank Sharma               2014-06-02  10710  
3230bf14c14e04d Jani Nikula                   2013-08-27  10711  /* regs above are bits 15:0 */
3230bf14c14e04d Jani Nikula                   2013-08-27  10712  
4ad83e94059969b Shashank Sharma               2014-06-02  10713  #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10714  #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10715  #define MIPI_DPI_CONTROL(port)		_MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
3230bf14c14e04d Jani Nikula                   2013-08-27  10716  #define  DPI_LP_MODE					(1 << 6)
3230bf14c14e04d Jani Nikula                   2013-08-27  10717  #define  BACKLIGHT_OFF					(1 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  10718  #define  BACKLIGHT_ON					(1 << 4)
3230bf14c14e04d Jani Nikula                   2013-08-27  10719  #define  COLOR_MODE_OFF					(1 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  10720  #define  COLOR_MODE_ON					(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10721  #define  TURN_ON					(1 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10722  #define  SHUTDOWN					(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10723  
4ad83e94059969b Shashank Sharma               2014-06-02  10724  #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10725  #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10726  #define MIPI_DPI_DATA(port)		_MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
3230bf14c14e04d Jani Nikula                   2013-08-27  10727  #define  COMMAND_BYTE_SHIFT				0
3230bf14c14e04d Jani Nikula                   2013-08-27  10728  #define  COMMAND_BYTE_MASK				(0x3f << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10729  
4ad83e94059969b Shashank Sharma               2014-06-02  10730  #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10731  #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10732  #define MIPI_INIT_COUNT(port)		_MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10733  #define  MASTER_INIT_TIMER_SHIFT			0
3230bf14c14e04d Jani Nikula                   2013-08-27  10734  #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10735  
4ad83e94059969b Shashank Sharma               2014-06-02  10736  #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10737  #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10738  #define MIPI_MAX_RETURN_PKT_SIZE(port)	_MMIO_MIPI(port, \
e7d7cad08d35329 Jani Nikula                   2014-11-14  10739  			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
3230bf14c14e04d Jani Nikula                   2013-08-27  10740  #define  MAX_RETURN_PKT_SIZE_SHIFT			0
3230bf14c14e04d Jani Nikula                   2013-08-27  10741  #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10742  
4ad83e94059969b Shashank Sharma               2014-06-02  10743  #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10744  #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10745  #define MIPI_VIDEO_MODE_FORMAT(port)	_MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10746  #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
3230bf14c14e04d Jani Nikula                   2013-08-27  10747  #define  DISABLE_VIDEO_BTA				(1 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  10748  #define  IP_TG_CONFIG					(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10749  #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10750  #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10751  #define  VIDEO_MODE_BURST				(3 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10752  
4ad83e94059969b Shashank Sharma               2014-06-02  10753  #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10754  #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10755  #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
f90e8c36c886447 Jani Nikula                   2016-06-03  10756  #define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
f90e8c36c886447 Jani Nikula                   2016-06-03  10757  #define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10758  #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
3230bf14c14e04d Jani Nikula                   2013-08-27  10759  #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
3230bf14c14e04d Jani Nikula                   2013-08-27  10760  #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  10761  #define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
3230bf14c14e04d Jani Nikula                   2013-08-27  10762  #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  10763  #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10764  #define  CLOCKSTOP					(1 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10765  #define  EOT_DISABLE					(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10766  
4ad83e94059969b Shashank Sharma               2014-06-02  10767  #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10768  #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10769  #define MIPI_LP_BYTECLK(port)		_MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
3230bf14c14e04d Jani Nikula                   2013-08-27  10770  #define  LP_BYTECLK_SHIFT				0
3230bf14c14e04d Jani Nikula                   2013-08-27  10771  #define  LP_BYTECLK_MASK				(0xffff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10772  
b426f985158d9a7 Deepak M                      2017-02-17  10773  #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
b426f985158d9a7 Deepak M                      2017-02-17  10774  #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
b426f985158d9a7 Deepak M                      2017-02-17  10775  #define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
b426f985158d9a7 Deepak M                      2017-02-17  10776  
b426f985158d9a7 Deepak M                      2017-02-17  10777  #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
b426f985158d9a7 Deepak M                      2017-02-17  10778  #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
b426f985158d9a7 Deepak M                      2017-02-17  10779  #define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
b426f985158d9a7 Deepak M                      2017-02-17  10780  
3230bf14c14e04d Jani Nikula                   2013-08-27  10781  /* bits 31:0 */
4ad83e94059969b Shashank Sharma               2014-06-02  10782  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10783  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10784  #define MIPI_LP_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
3230bf14c14e04d Jani Nikula                   2013-08-27  10785  
3230bf14c14e04d Jani Nikula                   2013-08-27  10786  /* bits 31:0 */
4ad83e94059969b Shashank Sharma               2014-06-02  10787  #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10788  #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10789  #define MIPI_HS_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
3230bf14c14e04d Jani Nikula                   2013-08-27  10790  
4ad83e94059969b Shashank Sharma               2014-06-02  10791  #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10792  #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10793  #define MIPI_LP_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
4ad83e94059969b Shashank Sharma               2014-06-02  10794  #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10795  #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10796  #define MIPI_HS_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
3230bf14c14e04d Jani Nikula                   2013-08-27  10797  #define  LONG_PACKET_WORD_COUNT_SHIFT			8
3230bf14c14e04d Jani Nikula                   2013-08-27  10798  #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10799  #define  SHORT_PACKET_PARAM_SHIFT			8
3230bf14c14e04d Jani Nikula                   2013-08-27  10800  #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10801  #define  VIRTUAL_CHANNEL_SHIFT				6
3230bf14c14e04d Jani Nikula                   2013-08-27  10802  #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
3230bf14c14e04d Jani Nikula                   2013-08-27  10803  #define  DATA_TYPE_SHIFT				0
395b2913e36ffb6 Ville Syrjälä                 2015-09-18  10804  #define  DATA_TYPE_MASK					(0x3f << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10805  /* data type values, see include/video/mipi_display.h */
3230bf14c14e04d Jani Nikula                   2013-08-27  10806  
4ad83e94059969b Shashank Sharma               2014-06-02  10807  #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10808  #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10809  #define MIPI_GEN_FIFO_STAT(port)	_MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
3230bf14c14e04d Jani Nikula                   2013-08-27  10810  #define  DPI_FIFO_EMPTY					(1 << 28)
3230bf14c14e04d Jani Nikula                   2013-08-27  10811  #define  DBI_FIFO_EMPTY					(1 << 27)
3230bf14c14e04d Jani Nikula                   2013-08-27  10812  #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
3230bf14c14e04d Jani Nikula                   2013-08-27  10813  #define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
3230bf14c14e04d Jani Nikula                   2013-08-27  10814  #define  LP_CTRL_FIFO_FULL				(1 << 24)
3230bf14c14e04d Jani Nikula                   2013-08-27  10815  #define  HS_CTRL_FIFO_EMPTY				(1 << 18)
3230bf14c14e04d Jani Nikula                   2013-08-27  10816  #define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
3230bf14c14e04d Jani Nikula                   2013-08-27  10817  #define  HS_CTRL_FIFO_FULL				(1 << 16)
3230bf14c14e04d Jani Nikula                   2013-08-27  10818  #define  LP_DATA_FIFO_EMPTY				(1 << 10)
3230bf14c14e04d Jani Nikula                   2013-08-27  10819  #define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
3230bf14c14e04d Jani Nikula                   2013-08-27  10820  #define  LP_DATA_FIFO_FULL				(1 << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10821  #define  HS_DATA_FIFO_EMPTY				(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  10822  #define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  10823  #define  HS_DATA_FIFO_FULL				(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10824  
4ad83e94059969b Shashank Sharma               2014-06-02  10825  #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10826  #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10827  #define MIPI_HS_LP_DBI_ENABLE(port)	_MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
3230bf14c14e04d Jani Nikula                   2013-08-27  10828  #define  DBI_HS_LP_MODE_MASK				(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10829  #define  DBI_LP_MODE					(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10830  #define  DBI_HS_MODE					(0 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10831  
4ad83e94059969b Shashank Sharma               2014-06-02  10832  #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
e7d7cad08d35329 Jani Nikula                   2014-11-14  10833  #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  10834  #define MIPI_DPHY_PARAM(port)		_MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
3230bf14c14e04d Jani Nikula                   2013-08-27  10835  #define  EXIT_ZERO_COUNT_SHIFT				24
3230bf14c14e04d Jani Nikula                   2013-08-27  10836  #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
3230bf14c14e04d Jani Nikula                   2013-08-27  10837  #define  TRAIL_COUNT_SHIFT				16
3230bf14c14e04d Jani Nikula                   2013-08-27  10838  #define  TRAIL_COUNT_MASK				(0x1f << 16)
3230bf14c14e04d Jani Nikula                   2013-08-27  10839  #define  CLK_ZERO_COUNT_SHIFT				8
3230bf14c14e04d Jani Nikula                   2013-08-27  10840  #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  10841  #define  PREPARE_COUNT_SHIFT				0
3230bf14c14e04d Jani Nikula                   2013-08-27  10842  #define  PREPARE_COUNT_MASK				(0x3f << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  10843  
146cdf3fad9c4b4 Madhav Chauhan                2018-07-10  10844  #define _ICL_DSI_T_INIT_MASTER_0	0x6b088
146cdf3fad9c4b4 Madhav Chauhan                2018-07-10  10845  #define _ICL_DSI_T_INIT_MASTER_1	0x6b888
146cdf3fad9c4b4 Madhav Chauhan                2018-07-10  10846  #define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
146cdf3fad9c4b4 Madhav Chauhan                2018-07-10  10847  						   _ICL_DSI_T_INIT_MASTER_0,\
146cdf3fad9c4b4 Madhav Chauhan                2018-07-10  10848  						   _ICL_DSI_T_INIT_MASTER_1)
146cdf3fad9c4b4 Madhav Chauhan                2018-07-10  10849  
33868a91c1d9627 Madhav Chauhan                2018-09-16  10850  #define _DPHY_CLK_TIMING_PARAM_0	0x162180
33868a91c1d9627 Madhav Chauhan                2018-09-16  10851  #define _DPHY_CLK_TIMING_PARAM_1	0x6c180
33868a91c1d9627 Madhav Chauhan                2018-09-16  10852  #define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10853  						   _DPHY_CLK_TIMING_PARAM_0,\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10854  						   _DPHY_CLK_TIMING_PARAM_1)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10855  #define _DSI_CLK_TIMING_PARAM_0		0x6b080
33868a91c1d9627 Madhav Chauhan                2018-09-16  10856  #define _DSI_CLK_TIMING_PARAM_1		0x6b880
33868a91c1d9627 Madhav Chauhan                2018-09-16  10857  #define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10858  						   _DSI_CLK_TIMING_PARAM_0,\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10859  						   _DSI_CLK_TIMING_PARAM_1)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10860  #define  CLK_PREPARE_OVERRIDE		(1 << 31)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10861  #define  CLK_PREPARE(x)		((x) << 28)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10862  #define  CLK_PREPARE_MASK		(0x7 << 28)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10863  #define  CLK_PREPARE_SHIFT		28
33868a91c1d9627 Madhav Chauhan                2018-09-16  10864  #define  CLK_ZERO_OVERRIDE		(1 << 27)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10865  #define  CLK_ZERO(x)			((x) << 20)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10866  #define  CLK_ZERO_MASK			(0xf << 20)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10867  #define  CLK_ZERO_SHIFT		20
33868a91c1d9627 Madhav Chauhan                2018-09-16  10868  #define  CLK_PRE_OVERRIDE		(1 << 19)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10869  #define  CLK_PRE(x)			((x) << 16)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10870  #define  CLK_PRE_MASK			(0x3 << 16)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10871  #define  CLK_PRE_SHIFT			16
33868a91c1d9627 Madhav Chauhan                2018-09-16  10872  #define  CLK_POST_OVERRIDE		(1 << 15)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10873  #define  CLK_POST(x)			((x) << 8)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10874  #define  CLK_POST_MASK			(0x7 << 8)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10875  #define  CLK_POST_SHIFT		8
33868a91c1d9627 Madhav Chauhan                2018-09-16  10876  #define  CLK_TRAIL_OVERRIDE		(1 << 7)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10877  #define  CLK_TRAIL(x)			((x) << 0)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10878  #define  CLK_TRAIL_MASK		(0xf << 0)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10879  #define  CLK_TRAIL_SHIFT		0
33868a91c1d9627 Madhav Chauhan                2018-09-16  10880  
33868a91c1d9627 Madhav Chauhan                2018-09-16  10881  #define _DPHY_DATA_TIMING_PARAM_0	0x162184
33868a91c1d9627 Madhav Chauhan                2018-09-16  10882  #define _DPHY_DATA_TIMING_PARAM_1	0x6c184
33868a91c1d9627 Madhav Chauhan                2018-09-16  10883  #define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10884  						   _DPHY_DATA_TIMING_PARAM_0,\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10885  						   _DPHY_DATA_TIMING_PARAM_1)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10886  #define _DSI_DATA_TIMING_PARAM_0	0x6B084
33868a91c1d9627 Madhav Chauhan                2018-09-16  10887  #define _DSI_DATA_TIMING_PARAM_1	0x6B884
33868a91c1d9627 Madhav Chauhan                2018-09-16  10888  #define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10889  						   _DSI_DATA_TIMING_PARAM_0,\
33868a91c1d9627 Madhav Chauhan                2018-09-16  10890  						   _DSI_DATA_TIMING_PARAM_1)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10891  #define  HS_PREPARE_OVERRIDE		(1 << 31)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10892  #define  HS_PREPARE(x)			((x) << 24)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10893  #define  HS_PREPARE_MASK		(0x7 << 24)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10894  #define  HS_PREPARE_SHIFT		24
33868a91c1d9627 Madhav Chauhan                2018-09-16  10895  #define  HS_ZERO_OVERRIDE		(1 << 23)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10896  #define  HS_ZERO(x)			((x) << 16)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10897  #define  HS_ZERO_MASK			(0xf << 16)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10898  #define  HS_ZERO_SHIFT			16
33868a91c1d9627 Madhav Chauhan                2018-09-16  10899  #define  HS_TRAIL_OVERRIDE		(1 << 15)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10900  #define  HS_TRAIL(x)			((x) << 8)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10901  #define  HS_TRAIL_MASK			(0x7 << 8)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10902  #define  HS_TRAIL_SHIFT		8
33868a91c1d9627 Madhav Chauhan                2018-09-16  10903  #define  HS_EXIT_OVERRIDE		(1 << 7)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10904  #define  HS_EXIT(x)			((x) << 0)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10905  #define  HS_EXIT_MASK			(0x7 << 0)
33868a91c1d9627 Madhav Chauhan                2018-09-16  10906  #define  HS_EXIT_SHIFT			0
33868a91c1d9627 Madhav Chauhan                2018-09-16  10907  
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10908  #define _DPHY_TA_TIMING_PARAM_0		0x162188
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10909  #define _DPHY_TA_TIMING_PARAM_1		0x6c188
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10910  #define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10911  						   _DPHY_TA_TIMING_PARAM_0,\
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10912  						   _DPHY_TA_TIMING_PARAM_1)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10913  #define _DSI_TA_TIMING_PARAM_0		0x6b098
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10914  #define _DSI_TA_TIMING_PARAM_1		0x6b898
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10915  #define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10916  						   _DSI_TA_TIMING_PARAM_0,\
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10917  						   _DSI_TA_TIMING_PARAM_1)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10918  #define  TA_SURE_OVERRIDE		(1 << 31)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10919  #define  TA_SURE(x)			((x) << 16)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10920  #define  TA_SURE_MASK			(0x1f << 16)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10921  #define  TA_SURE_SHIFT			16
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10922  #define  TA_GO_OVERRIDE		(1 << 15)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10923  #define  TA_GO(x)			((x) << 8)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10924  #define  TA_GO_MASK			(0xf << 8)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10925  #define  TA_GO_SHIFT			8
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10926  #define  TA_GET_OVERRIDE		(1 << 7)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10927  #define  TA_GET(x)			((x) << 0)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10928  #define  TA_GET_MASK			(0xf << 0)
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10929  #define  TA_GET_SHIFT			0
35c37ade79cdfe7 Madhav Chauhan                2018-09-16  10930  
5ffce2546233e0a Madhav Chauhan                2018-10-15  10931  /* DSI transcoder configuration */
5ffce2546233e0a Madhav Chauhan                2018-10-15  10932  #define _DSI_TRANS_FUNC_CONF_0		0x6b030
5ffce2546233e0a Madhav Chauhan                2018-10-15  10933  #define _DSI_TRANS_FUNC_CONF_1		0x6b830
5ffce2546233e0a Madhav Chauhan                2018-10-15  10934  #define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
5ffce2546233e0a Madhav Chauhan                2018-10-15  10935  						  _DSI_TRANS_FUNC_CONF_0,\
5ffce2546233e0a Madhav Chauhan                2018-10-15  10936  						  _DSI_TRANS_FUNC_CONF_1)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10937  #define  OP_MODE_MASK			(0x3 << 28)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10938  #define  OP_MODE_SHIFT			28
5ffce2546233e0a Madhav Chauhan                2018-10-15  10939  #define  CMD_MODE_NO_GATE		(0x0 << 28)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10940  #define  CMD_MODE_TE_GATE		(0x1 << 28)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10941  #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10942  #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10943  #define  LINK_READY			(1 << 20)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10944  #define  PIX_FMT_MASK			(0x3 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10945  #define  PIX_FMT_SHIFT			16
5ffce2546233e0a Madhav Chauhan                2018-10-15  10946  #define  PIX_FMT_RGB565			(0x0 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10947  #define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10948  #define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10949  #define  PIX_FMT_RGB888			(0x3 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10950  #define  PIX_FMT_RGB101010		(0x4 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10951  #define  PIX_FMT_RGB121212		(0x5 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10952  #define  PIX_FMT_COMPRESSED		(0x6 << 16)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10953  #define  BGR_TRANSMISSION		(1 << 15)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10954  #define  PIX_VIRT_CHAN(x)		((x) << 12)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10955  #define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10956  #define  PIX_VIRT_CHAN_SHIFT		12
5ffce2546233e0a Madhav Chauhan                2018-10-15  10957  #define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10958  #define  PIX_BUF_THRESHOLD_SHIFT	10
5ffce2546233e0a Madhav Chauhan                2018-10-15  10959  #define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10960  #define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10961  #define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10962  #define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10963  #define  CONTINUOUS_CLK_MASK		(0x3 << 8)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10964  #define  CONTINUOUS_CLK_SHIFT		8
5ffce2546233e0a Madhav Chauhan                2018-10-15  10965  #define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10966  #define  CLK_HS_OR_LP			(0x2 << 8)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10967  #define  CLK_HS_CONTINUOUS		(0x3 << 8)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10968  #define  LINK_CALIBRATION_MASK		(0x3 << 4)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10969  #define  LINK_CALIBRATION_SHIFT		4
5ffce2546233e0a Madhav Chauhan                2018-10-15  10970  #define  CALIBRATION_DISABLED		(0x0 << 4)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10971  #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10972  #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10973  #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10974  #define  EOTP_DISABLED			(1 << 0)
5ffce2546233e0a Madhav Chauhan                2018-10-15  10975  
60230aacd528ac3 Madhav Chauhan                2018-10-15  10976  #define _DSI_CMD_RXCTL_0		0x6b0d4
60230aacd528ac3 Madhav Chauhan                2018-10-15  10977  #define _DSI_CMD_RXCTL_1		0x6b8d4
60230aacd528ac3 Madhav Chauhan                2018-10-15  10978  #define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
60230aacd528ac3 Madhav Chauhan                2018-10-15  10979  						  _DSI_CMD_RXCTL_0,\
60230aacd528ac3 Madhav Chauhan                2018-10-15  10980  						  _DSI_CMD_RXCTL_1)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10981  #define  READ_UNLOADS_DW		(1 << 16)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10982  #define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10983  #define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10984  #define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10985  #define  RECEIVED_RESET_TRIGGER		(1 << 12)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10986  #define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10987  #define  RECEIVED_CRC_WAS_LOST		(1 << 10)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10988  #define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10989  #define  NUMBER_RX_PLOAD_DW_SHIFT	0
60230aacd528ac3 Madhav Chauhan                2018-10-15  10990  
60230aacd528ac3 Madhav Chauhan                2018-10-15  10991  #define _DSI_CMD_TXCTL_0		0x6b0d0
60230aacd528ac3 Madhav Chauhan                2018-10-15  10992  #define _DSI_CMD_TXCTL_1		0x6b8d0
60230aacd528ac3 Madhav Chauhan                2018-10-15  10993  #define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
60230aacd528ac3 Madhav Chauhan                2018-10-15  10994  						  _DSI_CMD_TXCTL_0,\
60230aacd528ac3 Madhav Chauhan                2018-10-15  10995  						  _DSI_CMD_TXCTL_1)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10996  #define  KEEP_LINK_IN_HS		(1 << 24)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10997  #define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
60230aacd528ac3 Madhav Chauhan                2018-10-15  10998  #define  FREE_HEADER_CREDIT_SHIFT	0x8
60230aacd528ac3 Madhav Chauhan                2018-10-15  10999  #define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
60230aacd528ac3 Madhav Chauhan                2018-10-15  11000  #define  FREE_PLOAD_CREDIT_SHIFT	0
60230aacd528ac3 Madhav Chauhan                2018-10-15  11001  #define  MAX_HEADER_CREDIT		0x10
60230aacd528ac3 Madhav Chauhan                2018-10-15  11002  #define  MAX_PLOAD_CREDIT		0x40
60230aacd528ac3 Madhav Chauhan                2018-10-15  11003  
808517e2c378650 Madhav Chauhan                2018-10-30  11004  #define _DSI_CMD_TXHDR_0		0x6b100
808517e2c378650 Madhav Chauhan                2018-10-30  11005  #define _DSI_CMD_TXHDR_1		0x6b900
808517e2c378650 Madhav Chauhan                2018-10-30  11006  #define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
808517e2c378650 Madhav Chauhan                2018-10-30  11007  						  _DSI_CMD_TXHDR_0,\
808517e2c378650 Madhav Chauhan                2018-10-30  11008  						  _DSI_CMD_TXHDR_1)
808517e2c378650 Madhav Chauhan                2018-10-30  11009  #define  PAYLOAD_PRESENT		(1 << 31)
808517e2c378650 Madhav Chauhan                2018-10-30  11010  #define  LP_DATA_TRANSFER		(1 << 30)
808517e2c378650 Madhav Chauhan                2018-10-30  11011  #define  VBLANK_FENCE			(1 << 29)
808517e2c378650 Madhav Chauhan                2018-10-30  11012  #define  PARAM_WC_MASK			(0xffff << 8)
808517e2c378650 Madhav Chauhan                2018-10-30  11013  #define  PARAM_WC_LOWER_SHIFT		8
808517e2c378650 Madhav Chauhan                2018-10-30  11014  #define  PARAM_WC_UPPER_SHIFT		16
808517e2c378650 Madhav Chauhan                2018-10-30  11015  #define  VC_MASK			(0x3 << 6)
808517e2c378650 Madhav Chauhan                2018-10-30  11016  #define  VC_SHIFT			6
808517e2c378650 Madhav Chauhan                2018-10-30  11017  #define  DT_MASK			(0x3f << 0)
808517e2c378650 Madhav Chauhan                2018-10-30  11018  #define  DT_SHIFT			0
808517e2c378650 Madhav Chauhan                2018-10-30  11019  
808517e2c378650 Madhav Chauhan                2018-10-30  11020  #define _DSI_CMD_TXPYLD_0		0x6b104
808517e2c378650 Madhav Chauhan                2018-10-30  11021  #define _DSI_CMD_TXPYLD_1		0x6b904
808517e2c378650 Madhav Chauhan                2018-10-30  11022  #define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
808517e2c378650 Madhav Chauhan                2018-10-30  11023  						  _DSI_CMD_TXPYLD_0,\
808517e2c378650 Madhav Chauhan                2018-10-30  11024  						  _DSI_CMD_TXPYLD_1)
808517e2c378650 Madhav Chauhan                2018-10-30  11025  
60230aacd528ac3 Madhav Chauhan                2018-10-15  11026  #define _DSI_LP_MSG_0			0x6b0d8
60230aacd528ac3 Madhav Chauhan                2018-10-15  11027  #define _DSI_LP_MSG_1			0x6b8d8
60230aacd528ac3 Madhav Chauhan                2018-10-15  11028  #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
60230aacd528ac3 Madhav Chauhan                2018-10-15  11029  						  _DSI_LP_MSG_0,\
60230aacd528ac3 Madhav Chauhan                2018-10-15  11030  						  _DSI_LP_MSG_1)
60230aacd528ac3 Madhav Chauhan                2018-10-15  11031  #define  LPTX_IN_PROGRESS		(1 << 17)
60230aacd528ac3 Madhav Chauhan                2018-10-15  11032  #define  LINK_IN_ULPS			(1 << 16)
60230aacd528ac3 Madhav Chauhan                2018-10-15  11033  #define  LINK_ULPS_TYPE_LP11		(1 << 8)
60230aacd528ac3 Madhav Chauhan                2018-10-15  11034  #define  LINK_ENTER_ULPS		(1 << 0)
60230aacd528ac3 Madhav Chauhan                2018-10-15  11035  
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11036  /* DSI timeout registers */
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11037  #define _DSI_HSTX_TO_0			0x6b044
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11038  #define _DSI_HSTX_TO_1			0x6b844
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11039  #define DSI_HSTX_TO(tc)			_MMIO_DSI(tc,	\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11040  						  _DSI_HSTX_TO_0,\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11041  						  _DSI_HSTX_TO_1)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11042  #define  HSTX_TIMEOUT_VALUE_MASK	(0xffff << 16)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11043  #define  HSTX_TIMEOUT_VALUE_SHIFT	16
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11044  #define  HSTX_TIMEOUT_VALUE(x)		((x) << 16)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11045  #define  HSTX_TIMED_OUT			(1 << 0)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11046  
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11047  #define _DSI_LPRX_HOST_TO_0		0x6b048
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11048  #define _DSI_LPRX_HOST_TO_1		0x6b848
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11049  #define DSI_LPRX_HOST_TO(tc)		_MMIO_DSI(tc,	\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11050  						  _DSI_LPRX_HOST_TO_0,\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11051  						  _DSI_LPRX_HOST_TO_1)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11052  #define  LPRX_TIMED_OUT			(1 << 16)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11053  #define  LPRX_TIMEOUT_VALUE_MASK	(0xffff << 0)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11054  #define  LPRX_TIMEOUT_VALUE_SHIFT	0
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11055  #define  LPRX_TIMEOUT_VALUE(x)		((x) << 0)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11056  
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11057  #define _DSI_PWAIT_TO_0			0x6b040
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11058  #define _DSI_PWAIT_TO_1			0x6b840
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11059  #define DSI_PWAIT_TO(tc)		_MMIO_DSI(tc,	\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11060  						  _DSI_PWAIT_TO_0,\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11061  						  _DSI_PWAIT_TO_1)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11062  #define  PRESET_TIMEOUT_VALUE_MASK	(0xffff << 16)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11063  #define  PRESET_TIMEOUT_VALUE_SHIFT	16
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11064  #define  PRESET_TIMEOUT_VALUE(x)	((x) << 16)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11065  #define  PRESPONSE_TIMEOUT_VALUE_MASK	(0xffff << 0)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11066  #define  PRESPONSE_TIMEOUT_VALUE_SHIFT	0
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11067  #define  PRESPONSE_TIMEOUT_VALUE(x)	((x) << 0)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11068  
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11069  #define _DSI_TA_TO_0			0x6b04c
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11070  #define _DSI_TA_TO_1			0x6b84c
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11071  #define DSI_TA_TO(tc)			_MMIO_DSI(tc,	\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11072  						  _DSI_TA_TO_0,\
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11073  						  _DSI_TA_TO_1)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11074  #define  TA_TIMED_OUT			(1 << 16)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11075  #define  TA_TIMEOUT_VALUE_MASK		(0xffff << 0)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11076  #define  TA_TIMEOUT_VALUE_SHIFT		0
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11077  #define  TA_TIMEOUT_VALUE(x)		((x) << 0)
8bffd204ded8dd5 Madhav Chauhan                2018-10-30  11078  
3230bf14c14e04d Jani Nikula                   2013-08-27  11079  /* bits 31:0 */
4ad83e94059969b Shashank Sharma               2014-06-02  11080  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11081  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11082  #define MIPI_DBI_BW_CTRL(port)		_MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11083  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11084  #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11085  #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11086  #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
3230bf14c14e04d Jani Nikula                   2013-08-27  11087  #define  LP_HS_SSW_CNT_SHIFT				16
3230bf14c14e04d Jani Nikula                   2013-08-27  11088  #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
3230bf14c14e04d Jani Nikula                   2013-08-27  11089  #define  HS_LP_PWR_SW_CNT_SHIFT				0
3230bf14c14e04d Jani Nikula                   2013-08-27  11090  #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  11091  
4ad83e94059969b Shashank Sharma               2014-06-02  11092  #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11093  #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11094  #define MIPI_STOP_STATE_STALL(port)	_MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
3230bf14c14e04d Jani Nikula                   2013-08-27  11095  #define  STOP_STATE_STALL_COUNTER_SHIFT			0
3230bf14c14e04d Jani Nikula                   2013-08-27  11096  #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  11097  
4ad83e94059969b Shashank Sharma               2014-06-02  11098  #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11099  #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11100  #define MIPI_INTR_STAT_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
4ad83e94059969b Shashank Sharma               2014-06-02  11101  #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11102  #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11103  #define MIPI_INTR_EN_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
3230bf14c14e04d Jani Nikula                   2013-08-27  11104  #define  RX_CONTENTION_DETECTED				(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  11105  
3230bf14c14e04d Jani Nikula                   2013-08-27  11106  /* XXX: only pipe A ?!? */
4ad83e94059969b Shashank Sharma               2014-06-02  11107  #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
3230bf14c14e04d Jani Nikula                   2013-08-27  11108  #define  DBI_TYPEC_ENABLE				(1 << 31)
3230bf14c14e04d Jani Nikula                   2013-08-27  11109  #define  DBI_TYPEC_WIP					(1 << 30)
3230bf14c14e04d Jani Nikula                   2013-08-27  11110  #define  DBI_TYPEC_OPTION_SHIFT				28
3230bf14c14e04d Jani Nikula                   2013-08-27  11111  #define  DBI_TYPEC_OPTION_MASK				(3 << 28)
3230bf14c14e04d Jani Nikula                   2013-08-27  11112  #define  DBI_TYPEC_FREQ_SHIFT				24
3230bf14c14e04d Jani Nikula                   2013-08-27  11113  #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
3230bf14c14e04d Jani Nikula                   2013-08-27  11114  #define  DBI_TYPEC_OVERRIDE				(1 << 8)
3230bf14c14e04d Jani Nikula                   2013-08-27  11115  #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
3230bf14c14e04d Jani Nikula                   2013-08-27  11116  #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  11117  
3230bf14c14e04d Jani Nikula                   2013-08-27  11118  
3230bf14c14e04d Jani Nikula                   2013-08-27  11119  /* MIPI adapter registers */
3230bf14c14e04d Jani Nikula                   2013-08-27  11120  
4ad83e94059969b Shashank Sharma               2014-06-02  11121  #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11122  #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11123  #define MIPI_CTRL(port)			_MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
3230bf14c14e04d Jani Nikula                   2013-08-27  11124  #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
3230bf14c14e04d Jani Nikula                   2013-08-27  11125  #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  11126  #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  11127  #define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  11128  #define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  11129  #define  READ_REQUEST_PRIORITY_SHIFT			3
3230bf14c14e04d Jani Nikula                   2013-08-27  11130  #define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  11131  #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  11132  #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
3230bf14c14e04d Jani Nikula                   2013-08-27  11133  #define  RGB_FLIP_TO_BGR				(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  11134  
6b93e9c89ee553c Jani Nikula                   2016-03-15  11135  #define  BXT_PIPE_SELECT_SHIFT				7
d2e08c0f34438af Shashank Sharma               2015-09-01  11136  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
56c48978413ec5a Deepak M                      2015-12-09  11137  #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
093d680a482f5c8 Deepak M                      2016-12-15  11138  #define  GLK_PHY_STATUS_PORT_READY			(1 << 31) /* RO */
093d680a482f5c8 Deepak M                      2016-12-15  11139  #define  GLK_ULPS_NOT_ACTIVE				(1 << 30) /* RO */
093d680a482f5c8 Deepak M                      2016-12-15  11140  #define  GLK_MIPIIO_RESET_RELEASED			(1 << 28)
093d680a482f5c8 Deepak M                      2016-12-15  11141  #define  GLK_CLOCK_LANE_STOP_STATE			(1 << 27) /* RO */
093d680a482f5c8 Deepak M                      2016-12-15  11142  #define  GLK_DATA_LANE_STOP_STATE			(1 << 26) /* RO */
093d680a482f5c8 Deepak M                      2016-12-15  11143  #define  GLK_LP_WAKE					(1 << 22)
093d680a482f5c8 Deepak M                      2016-12-15  11144  #define  GLK_LP11_LOW_PWR_MODE				(1 << 21)
093d680a482f5c8 Deepak M                      2016-12-15  11145  #define  GLK_LP00_LOW_PWR_MODE				(1 << 20)
093d680a482f5c8 Deepak M                      2016-12-15  11146  #define  GLK_FIREWALL_ENABLE				(1 << 16)
093d680a482f5c8 Deepak M                      2016-12-15  11147  #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
093d680a482f5c8 Deepak M                      2016-12-15  11148  #define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
093d680a482f5c8 Deepak M                      2016-12-15  11149  #define  BXT_DSC_ENABLE					(1 << 3)
093d680a482f5c8 Deepak M                      2016-12-15  11150  #define  BXT_RGB_FLIP					(1 << 2)
093d680a482f5c8 Deepak M                      2016-12-15  11151  #define  GLK_MIPIIO_PORT_POWERED			(1 << 1) /* RO */
093d680a482f5c8 Deepak M                      2016-12-15  11152  #define  GLK_MIPIIO_ENABLE				(1 << 0)
d2e08c0f34438af Shashank Sharma               2015-09-01  11153  
4ad83e94059969b Shashank Sharma               2014-06-02  11154  #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11155  #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11156  #define MIPI_DATA_ADDRESS(port)		_MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
3230bf14c14e04d Jani Nikula                   2013-08-27  11157  #define  DATA_MEM_ADDRESS_SHIFT				5
3230bf14c14e04d Jani Nikula                   2013-08-27  11158  #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  11159  #define  DATA_VALID					(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  11160  
4ad83e94059969b Shashank Sharma               2014-06-02  11161  #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11162  #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11163  #define MIPI_DATA_LENGTH(port)		_MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
3230bf14c14e04d Jani Nikula                   2013-08-27  11164  #define  DATA_LENGTH_SHIFT				0
3230bf14c14e04d Jani Nikula                   2013-08-27  11165  #define  DATA_LENGTH_MASK				(0xfffff << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  11166  
4ad83e94059969b Shashank Sharma               2014-06-02  11167  #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11168  #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11169  #define MIPI_COMMAND_ADDRESS(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
3230bf14c14e04d Jani Nikula                   2013-08-27  11170  #define  COMMAND_MEM_ADDRESS_SHIFT			5
3230bf14c14e04d Jani Nikula                   2013-08-27  11171  #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
3230bf14c14e04d Jani Nikula                   2013-08-27  11172  #define  AUTO_PWG_ENABLE				(1 << 2)
3230bf14c14e04d Jani Nikula                   2013-08-27  11173  #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
3230bf14c14e04d Jani Nikula                   2013-08-27  11174  #define  COMMAND_VALID					(1 << 0)
3230bf14c14e04d Jani Nikula                   2013-08-27  11175  
4ad83e94059969b Shashank Sharma               2014-06-02  11176  #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11177  #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11178  #define MIPI_COMMAND_LENGTH(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
3230bf14c14e04d Jani Nikula                   2013-08-27  11179  #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
3230bf14c14e04d Jani Nikula                   2013-08-27  11180  #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
3230bf14c14e04d Jani Nikula                   2013-08-27  11181  
4ad83e94059969b Shashank Sharma               2014-06-02  11182  #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11183  #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11184  #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
3230bf14c14e04d Jani Nikula                   2013-08-27  11185  
4ad83e94059969b Shashank Sharma               2014-06-02  11186  #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
e7d7cad08d35329 Jani Nikula                   2014-11-14  11187  #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11188  #define MIPI_READ_DATA_VALID(port)	_MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
3230bf14c14e04d Jani Nikula                   2013-08-27  11189  #define  READ_DATA_VALID(n)				(1 << (n))
3230bf14c14e04d Jani Nikula                   2013-08-27  11190  
3bbaba0ceaa254c Peter Antoine                 2015-07-10  11191  /* MOCS (Memory Object Control State) registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11192  #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
3bbaba0ceaa254c Peter Antoine                 2015-07-10  11193  
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11194  #define GEN9_GFX_MOCS(i)	_MMIO(0xc800 + (i) * 4)	/* Graphics MOCS registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11195  #define GEN9_MFX0_MOCS(i)	_MMIO(0xc900 + (i) * 4)	/* Media 0 MOCS registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11196  #define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11197  #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
f0f59a00a1c9be1 Ville Syrjälä                 2015-11-18  11198  #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
74ba22ead5971e2 Tomasz Lis                    2018-05-02  11199  /* Media decoder 2 MOCS registers */
74ba22ead5971e2 Tomasz Lis                    2018-05-02  11200  #define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
3bbaba0ceaa254c Peter Antoine                 2015-07-10  11201  
73f4e8a338da114 Oscar Mateo                   2018-05-08  11202  #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
73f4e8a338da114 Oscar Mateo                   2018-05-08  11203  #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
73f4e8a338da114 Oscar Mateo                   2018-05-08  11204  #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
73f4e8a338da114 Oscar Mateo                   2018-05-08  11205  #define   PMFLUSHDONE_LNEBLK		(1 << 22)
73f4e8a338da114 Oscar Mateo                   2018-05-08  11206  
d5165ebd527c54b Tim Gore                      2016-02-04  11207  /* gamt regs */
d5165ebd527c54b Tim Gore                      2016-02-04  11208  #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
d5165ebd527c54b Tim Gore                      2016-02-04  11209  #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
d5165ebd527c54b Tim Gore                      2016-02-04  11210  #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
d5165ebd527c54b Tim Gore                      2016-02-04  11211  #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
d5165ebd527c54b Tim Gore                      2016-02-04  11212  #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
d5165ebd527c54b Tim Gore                      2016-02-04  11213  
93564044fb2c938 Ville Syrjälä                 2017-08-24  11214  #define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
93564044fb2c938 Ville Syrjälä                 2017-08-24  11215  #define  MMCD_PCLA		(1 << 31)
93564044fb2c938 Ville Syrjälä                 2017-08-24  11216  #define  MMCD_HOTSPOT_EN	(1 << 27)
93564044fb2c938 Ville Syrjälä                 2017-08-24  11217  
ad186f3fd98a958 Paulo Zanoni                  2018-02-05  11218  #define _ICL_PHY_MISC_A		0x64C00
ad186f3fd98a958 Paulo Zanoni                  2018-02-05  11219  #define _ICL_PHY_MISC_B		0x64C04
ad186f3fd98a958 Paulo Zanoni                  2018-02-05  11220  #define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
ad186f3fd98a958 Paulo Zanoni                  2018-02-05  11221  						 _ICL_PHY_MISC_B)
bdeb18dbcf8227e Matt Roper                    2019-06-18  11222  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
ad186f3fd98a958 Paulo Zanoni                  2018-02-05  11223  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
ad186f3fd98a958 Paulo Zanoni                  2018-02-05  11224  
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11225  /* Icelake Display Stream Compression Registers */
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11226  #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11227  #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11228  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11229  #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11230  #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11231  #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11232  #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11233  							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11234  							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11235  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11236  							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11237  							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11238  #define  DSC_VBR_ENABLE			(1 << 19)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11239  #define  DSC_422_ENABLE			(1 << 18)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11240  #define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11241  #define  DSC_BLOCK_PREDICTION		(1 << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11242  #define  DSC_LINE_BUF_DEPTH_SHIFT	12
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11243  #define  DSC_BPC_SHIFT			8
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11244  #define  DSC_VER_MIN_SHIFT		4
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11245  #define  DSC_VER_MAJ			(0x1 << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11246  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11247  #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11248  #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11249  #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11250  #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11251  #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11252  #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11253  #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11254  							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11255  							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11256  #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11257  							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11258  							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11259  #define  DSC_BPP(bpp)				((bpp) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11260  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11261  #define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11262  #define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11263  #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11264  #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11265  #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11266  #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11267  #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11268  							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11269  							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11270  #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11271  					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11272  					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11273  #define  DSC_PIC_WIDTH(pic_width)	((pic_width) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11274  #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11275  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11276  #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11277  #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11278  #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11279  #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11280  #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11281  #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11282  #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11283  							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11284  							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11285  #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11286  							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11287  							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11288  #define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11289  #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11290  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11291  #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11292  #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11293  #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11294  #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11295  #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11296  #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11297  #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11298  							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11299  							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11300  #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
5df52391ddbed86 Manasi Navare                 2018-08-23  11301  							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11302  							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11303  #define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11304  #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11305  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11306  #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11307  #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11308  #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11309  #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11310  #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11311  #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11312  #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11313  							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11314  							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11315  #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
5df52391ddbed86 Manasi Navare                 2018-08-23  11316  							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11317  							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11318  #define  DSC_SCALE_DEC_INT(scale_dec)	((scale_dec) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11319  #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11320  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11321  #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11322  #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11323  #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11324  #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11325  #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11326  #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11327  #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11328  							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11329  							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11330  #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11331  							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11332  							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11333  #define  DSC_FLATNESS_MAX_QP(max_qp)		((max_qp) << 24)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11334  #define  DSC_FLATNESS_MIN_QP(min_qp)		((min_qp) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11335  #define  DSC_FIRST_LINE_BPG_OFFSET(offset)	((offset) << 8)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11336  #define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11337  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11338  #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11339  #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11340  #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11341  #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11342  #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11343  #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11344  #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11345  							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11346  							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11347  #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11348  							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11349  							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11350  #define  DSC_NFL_BPG_OFFSET(bpg_offset)		((bpg_offset) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11351  #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11352  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11353  #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11354  #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11355  #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11356  #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11357  #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11358  #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11359  #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11360  							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11361  							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11362  #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11363  							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11364  							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11365  #define  DSC_INITIAL_OFFSET(initial_offset)		((initial_offset) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11366  #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11367  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11368  #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11369  #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11370  #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11371  #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11372  #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11373  #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11374  #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11375  							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11376  							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11377  #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11378  							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11379  							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11380  #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	((rc_edge_fact) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11381  #define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11382  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11383  #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11384  #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11385  #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11386  #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11387  #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11388  #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11389  #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11390  							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11391  							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11392  #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11393  							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11394  							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11395  #define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		((rc_tgt_off_low) << 20)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11396  #define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	((rc_tgt_off_high) << 16)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11397  #define  DSC_RC_QUANT_INC_LIMIT1(lim)			((lim) << 8)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11398  #define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11399  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11400  #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11401  #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11402  #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11403  #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11404  #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11405  #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11406  #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11407  							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11408  							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11409  #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11410  							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11411  							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11412  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11413  #define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11414  #define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11415  #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11416  #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11417  #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11418  #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11419  #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11420  							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11421  							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11422  #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11423  							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11424  							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11425  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11426  #define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11427  #define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11428  #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11429  #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11430  #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11431  #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11432  #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11433  							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11434  							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11435  #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11436  							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11437  							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11438  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11439  #define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11440  #define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11441  #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11442  #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11443  #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11444  #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11445  #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11446  							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11447  							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11448  #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11449  							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11450  							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11451  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11452  #define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11453  #define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11454  #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11455  #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11456  #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11457  #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11458  #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11459  							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11460  							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11461  #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11462  							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11463  							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11464  
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11465  #define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11466  #define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11467  #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11468  #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11469  #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11470  #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11471  #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11472  							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11473  							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11474  #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11475  							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11476  							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
35b876db4a425e5 Anusha Srivatsa               2018-10-30  11477  #define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11478  #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
6f15a7de86c8cf2 Anusha Srivatsa               2018-07-20  11479  #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
2efbb2f099fb75d Anusha Srivatsa               2018-07-17  11480  
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11481  /* Icelake Rate Control Buffer Threshold Registers */
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11482  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11483  #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11484  #define DSCC_RC_BUF_THRESH_0			_MMIO(0x6BA30)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11485  #define DSCC_RC_BUF_THRESH_0_UDW		_MMIO(0x6BA30 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11486  #define _ICL_DSC0_RC_BUF_THRESH_0_PB		(0x78254)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11487  #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB	(0x78254 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11488  #define _ICL_DSC1_RC_BUF_THRESH_0_PB		(0x78354)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11489  #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB	(0x78354 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11490  #define _ICL_DSC0_RC_BUF_THRESH_0_PC		(0x78454)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11491  #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC	(0x78454 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11492  #define _ICL_DSC1_RC_BUF_THRESH_0_PC		(0x78554)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11493  #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC	(0x78554 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11494  #define ICL_DSC0_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11495  						_ICL_DSC0_RC_BUF_THRESH_0_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11496  						_ICL_DSC0_RC_BUF_THRESH_0_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11497  #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11498  						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11499  						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11500  #define ICL_DSC1_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11501  						_ICL_DSC1_RC_BUF_THRESH_0_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11502  						_ICL_DSC1_RC_BUF_THRESH_0_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11503  #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11504  						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11505  						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11506  
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11507  #define DSCA_RC_BUF_THRESH_1			_MMIO(0x6B238)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11508  #define DSCA_RC_BUF_THRESH_1_UDW		_MMIO(0x6B238 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11509  #define DSCC_RC_BUF_THRESH_1			_MMIO(0x6BA38)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11510  #define DSCC_RC_BUF_THRESH_1_UDW		_MMIO(0x6BA38 + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11511  #define _ICL_DSC0_RC_BUF_THRESH_1_PB		(0x7825C)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11512  #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB	(0x7825C + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11513  #define _ICL_DSC1_RC_BUF_THRESH_1_PB		(0x7835C)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11514  #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB	(0x7835C + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11515  #define _ICL_DSC0_RC_BUF_THRESH_1_PC		(0x7845C)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11516  #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC	(0x7845C + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11517  #define _ICL_DSC1_RC_BUF_THRESH_1_PC		(0x7855C)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11518  #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC	(0x7855C + 4)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11519  #define ICL_DSC0_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11520  						_ICL_DSC0_RC_BUF_THRESH_1_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11521  						_ICL_DSC0_RC_BUF_THRESH_1_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11522  #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11523  						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11524  						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11525  #define ICL_DSC1_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11526  						_ICL_DSC1_RC_BUF_THRESH_1_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11527  						_ICL_DSC1_RC_BUF_THRESH_1_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11528  #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11529  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11530  						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
dbda5111e2d85ff Anusha Srivatsa               2018-07-17  11531  
0caf625777300d3 Anusha Srivatsa               2019-07-11  11532  #define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
0caf625777300d3 Anusha Srivatsa               2019-07-11  11533  #define   MODULAR_FIA_MASK			(1 << 4)
b9fcddab4afbac6 Paulo Zanoni                  2018-07-25  11534  #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
b9fcddab4afbac6 Paulo Zanoni                  2018-07-25  11535  #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
db7295c2c4efb56 Animesh Manna                 2018-07-24  11536  #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
db7295c2c4efb56 Animesh Manna                 2018-07-24  11537  #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
db7295c2c4efb56 Animesh Manna                 2018-07-24  11538  #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
b9fcddab4afbac6 Paulo Zanoni                  2018-07-25  11539  
0caf625777300d3 Anusha Srivatsa               2019-07-11  11540  #define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
39d1e234e1e13f6 Paulo Zanoni                  2018-08-01  11541  #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))
39d1e234e1e13f6 Paulo Zanoni                  2018-08-01  11542  
0caf625777300d3 Anusha Srivatsa               2019-07-11  11543  #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
39d1e234e1e13f6 Paulo Zanoni                  2018-08-01  11544  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
39d1e234e1e13f6 Paulo Zanoni                  2018-08-01  11545  
585fb111348f7cd Jesse Barnes                  2008-07-29  11546  #endif /* _I915_REG_H_ */

:::::: The code at line 185 was first introduced by commit
:::::: f0f59a00a1c9be11038bef5aa735ed7dd985f9cf drm/i915: Type safe register read/write

:::::: TO: Ville Syrjälä <ville.syrjala at linux.intel.com>
:::::: CC: Ville Syrjälä <ville.syrjala at linux.intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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