[PATCH v2] drm/i915/gvt: rename F_IN_CTX flag to F_IN_CTX_SR
Zhenyu Wang
zhenyuw at linux.intel.com
Wed Jun 19 02:48:25 UTC 2019
On 2019.06.17 04:11:50 -0400, Yan Zhao wrote:
> F_IN_CTX is an inaccurate flag name, because people may falsly think all
falsly -> falsely
> mmios in context image are of this flag. But actually, this flag is only
> for mmios both in GVT's save-restore list and in hardare logical
> context's image.
>
> v2: rename F_IN_SRLIST_AND_CTX to F_IN_CTX_SR (zhenyu wang)
>
> Signed-off-by: Yan Zhao <yan.y.zhao at intel.com>
Good to me.
Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> ---
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
> drivers/gpu/drm/i915/gvt/gvt.h | 23 ++++++++++++++---------
> drivers/gpu/drm/i915/gvt/mmio_context.c | 3 ++-
> 3 files changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 6ea88270c818..78b8c9b6b2bc 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -906,7 +906,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
> * inhibit context will restore with correct values
> */
> if (IS_GEN(gvt->dev_priv, 9) &&
> - intel_gvt_mmio_is_in_ctx(gvt, offset) &&
> + intel_gvt_mmio_is_in_ctx_sr(gvt, offset) &&
> !strncmp(cmd, "lri", 3)) {
> intel_gvt_hypervisor_read_gpa(s->vgpu,
> s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> index b54f2bdc13a4..a4bec5086e35 100644
> --- a/drivers/gpu/drm/i915/gvt/gvt.h
> +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> @@ -271,8 +271,10 @@ struct intel_gvt_mmio {
> #define F_CMD_ACCESSED (1 << 5)
> /* This reg could be accessed by unaligned address */
> #define F_UNALIGN (1 << 6)
> -/* This reg is saved/restored in context */
> -#define F_IN_CTX (1 << 7)
> +/* This reg is in GVT's mmio save-restor list and in hardware
> + * logical context image
> + */
> +#define F_IN_CTX_SR (1 << 7)
>
> struct gvt_mmio_block *mmio_block;
> unsigned int num_mmio_block;
> @@ -656,30 +658,33 @@ static inline bool intel_gvt_mmio_has_mode_mask(
> }
>
> /**
> - * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask
> + * intel_gvt_mmio_is_in_ctx_sr -
> + * check if an MMIO has in-ctx-sr mask
> * @gvt: a GVT device
> * @offset: register offset
> *
> * Returns:
> - * True if a MMIO has a in-context mask, false if it isn't.
> + * True if an MMIO has a in-context-sr mask, false if it isn't.
> *
> */
> -static inline bool intel_gvt_mmio_is_in_ctx(
> +static inline bool intel_gvt_mmio_is_in_ctx_sr(
> struct intel_gvt *gvt, unsigned int offset)
> {
> - return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX;
> + return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX_SR;
> }
>
> /**
> - * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context
> + * intel_gvt_mmio_set_in_ctx_sr -
> + * mask an MMIO in GVT's mmio save-restore list and also
> + * in hardware logical context image
> * @gvt: a GVT device
> * @offset: register offset
> *
> */
> -static inline void intel_gvt_mmio_set_in_ctx(
> +static inline void intel_gvt_mmio_set_in_ctx_sr(
> struct intel_gvt *gvt, unsigned int offset)
> {
> - gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX;
> + gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX_SR;
> }
>
> int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 2998999e8568..3958cce88c41 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -574,7 +574,8 @@ void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
> i915_mmio_reg_valid(mmio->reg); mmio++) {
> if (mmio->in_context) {
> gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
> - intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
> + intel_gvt_mmio_set_in_ctx_sr(gvt,
> + mmio->reg.reg);
> }
> }
> }
> --
> 2.17.1
>
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