[PATCH v6 2/2] drm/i915/gvt: call common mmio rw routine for vreg update in lri cmd parser
Yuan, Hang
hang.yuan at intel.com
Mon Mar 11 09:17:52 UTC 2019
Just have concern that intel_vgpu_mmio_reg_rw()does emulate register's behavior as well but cmd_reg_handler() just saves register's value in vreg.
Regards,
Henry
> -----Original Message-----
> From: intel-gvt-dev [mailto:intel-gvt-dev-bounces at lists.freedesktop.org] On
> Behalf Of Yan Zhao
> Sent: Monday, March 11, 2019 12:52 PM
> To: intel-gvt-dev at lists.freedesktop.org
> Cc: Zhao, Yan Y <yan.y.zhao at intel.com>
> Subject: [PATCH v6 2/2] drm/i915/gvt: call common mmio rw routine for vreg
> update in lri cmd parser
>
> in cmd parser, when there's a need to update vregs according to commands
> being parsed, do not create a separate function
> intel_vgpu_mask_mmio_write(), but call intel_vgpu_mmio_reg_rw() to keep
> consistent with handling behavior for CPU read/write of mmio.
>
> This patch is a code refinement to
> commit 6cef21a19649 ("drm/i915/gvt: update vreg on inhibit context lri
> command")
>
> v6: update commit message (zhenyu wang)
> v5: remove intel_vgpu_mask_mmio_write in mmio.h
> v4: check return value of intel_vgpu_mmio_reg_rw()
>
> Signed-off-by: Yan Zhao <yan.y.zhao at intel.com>
> ---
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 11 +++++------
> drivers/gpu/drm/i915/gvt/handlers.c | 24 ------------------------
> drivers/gpu/drm/i915/gvt/mmio.h | 2 --
> 3 files changed, 5 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 3592d04c33b2..26a6bfc7065c 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -909,13 +909,12 @@ static int cmd_reg_handler(struct
> parser_exec_state *s,
> s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
> /* check inhibit context */
> if (ctx_sr_ctl & 1) {
> + int ret = 0;
> u32 data = cmd_val(s, index + 1);
> -
> - if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt,
> offset))
> - intel_vgpu_mask_mmio_write(vgpu,
> - offset, &data, 4);
> - else
> - vgpu_vreg(vgpu, offset) = data;
> + ret = intel_vgpu_mmio_reg_rw(s->vgpu, offset,
> + &data, 4, false);
> + if (ret)
> + return ret;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
> b/drivers/gpu/drm/i915/gvt/handlers.c
> index 54bd0b033298..545154af93e9 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -3401,30 +3401,6 @@ int intel_vgpu_default_mmio_write(struct
> intel_vgpu *vgpu, unsigned int offset,
> return 0;
> }
>
> -/**
> - * intel_vgpu_mask_mmio_write - write mask register
> - * @vgpu: a vGPU
> - * @offset: access offset
> - * @p_data: write data buffer
> - * @bytes: access data length
> - *
> - * Returns:
> - * Zero on success, negative error code if failed.
> - */
> -int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int
> offset,
> - void *p_data, unsigned int bytes)
> -{
> - u32 mask, old_vreg;
> -
> - old_vreg = vgpu_vreg(vgpu, offset);
> - write_vreg(vgpu, offset, p_data, bytes);
> - mask = vgpu_vreg(vgpu, offset) >> 16;
> - vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
> - (vgpu_vreg(vgpu, offset) & mask);
> -
> - return 0;
> -}
> -
> /**
> * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
> * force-nopriv register
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.h
> b/drivers/gpu/drm/i915/gvt/mmio.h index 5874f1cb4306..2a8ae8898265
> 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.h
> +++ b/drivers/gpu/drm/i915/gvt/mmio.h
> @@ -100,6 +100,4 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct
> intel_gvt *gvt, int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu,
> unsigned int offset,
> void *pdata, unsigned int bytes, bool is_read);
>
> -int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int
> offset,
> - void *p_data, unsigned int bytes);
> #endif
> --
> 2.17.1
>
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