[PATCH] drm/i915/gvt: replaced register address with name
Zhenyu Wang
zhenyuw at linux.intel.com
Fri Mar 29 02:41:01 UTC 2019
On 2019.03.20 13:14:03 -0400, Xiaolin Zhang wrote:
> in init_skil_mmio_info, replaced register address with the known
> name from i915_reg.h definition to improve code readbility.
>
> Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
> ---
Thanks, it's always good to use defined name instead of open code.
Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> drivers/gpu/drm/i915/gvt/handlers.c | 79 +++++++++++++++++++------------------
> 1 file changed, 40 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 63418c8..02e7420 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2827,26 +2827,26 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
>
> MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>
> - MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL);
> - MMIO_D(_MMIO(0x45504), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x45520), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x46000), D_SKL_PLUS);
> - MMIO_DH(_MMIO(0x46010), D_SKL_PLUS, NULL, skl_lcpll_write);
> - MMIO_DH(_MMIO(0x46014), D_SKL_PLUS, NULL, skl_lcpll_write);
> - MMIO_D(_MMIO(0x6C040), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6C048), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6C050), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6C044), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6C04C), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6C054), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6c058), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6c05c), D_SKL_PLUS);
> - MMIO_DH(_MMIO(0x6c060), D_SKL_PLUS, dpll_status_read, NULL);
> + MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>
> MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> @@ -2965,40 +2965,41 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_D(_MMIO(0x70380), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x71380), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x7039c), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>
> - MMIO_D(_MMIO(0x8f074), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x8f004), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x8f034), D_SKL_PLUS);
> + MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
> + MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
> + MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
>
> - MMIO_D(_MMIO(0xb11c), D_SKL_PLUS);
> + MMIO_D(BDW_SCRATCH1, D_SKL_PLUS);
>
> - MMIO_D(_MMIO(0x51000), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS);
> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>
> - MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> NULL, NULL);
> - MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> NULL, NULL);
>
> MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> - MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
> - MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, F_MODE_MASK,
> + NULL, NULL);
> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> NULL, NULL);
>
> /* TRTT */
> - MMIO_DFH(_MMIO(0x4de0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x4de4), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x4de8), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x4dec), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x4df0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x4df4), D_SKL_PLUS, F_CMD_ACCESS,
> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
> NULL, gen9_trtte_write);
> MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
>
> @@ -3011,7 +3012,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>
> MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x1082c0), D_SKL_PLUS);
> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> @@ -3042,8 +3043,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> NULL, NULL);
>
> - MMIO_D(_MMIO(0x4ab8), D_KBL | D_CFL);
> - MMIO_D(_MMIO(0x2248), D_SKL_PLUS);
> + MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
>
> return 0;
> }
> --
> 1.8.3.1
>
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
--
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