[PATCH v4] drm/i915/gvt: save RING_HEAD into vreg when vgpu switched out

[Xiaolin Zhang]

Save RING_HEAD into vgpu reg when vgpu switched out and report
it's value back to guest.

v4: updated HEAD/TAIL with guest value, not host value. (Yan Zhao)
v3: save RING HEAD/TAIL vgpu reg in save_ring_hw_state. (Zhenyu Wang)
v2: save RING_TAIL as well during vgpu mmio switch to meet ring_is_idle
condition. (Fred Gao)
v1: based on input from Weinan. (Weinan Li)

[zhenyuw: Include this fix for possible future guest kernel that
would utilize RING_HEAD for hangcheck.]

Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
---
 drivers/gpu/drm/i915/gvt/scheduler.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 38897d2..49f6604 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -793,10 +793,19 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
 	void *src;
 	unsigned long context_gpa, context_page_num;
 	int i;
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+	i915_reg_t reg;
+	u32 ring_base;
 
 	gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
 		      workload->ctx_desc.lrca);
 
+	ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
+	reg = RING_TAIL(ring_base);
+	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = workload->rb_tail;
+	reg = RING_HEAD(ring_base);
+	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = workload->rb_tail;
+
 	context_page_num = rq->engine->context_size;
 	context_page_num = context_page_num >> PAGE_SHIFT;
 
-- 
2.7.4